What is an Embedded System<br />      An Embedded System is a microprocessor based system that is embedded as a subsystem,...
Application areas<br />Automotive electronics<br />Aircraft electronics<br />Trains<br />Telecommunication<br />
Design challenge optimizing design metrics<br />Obvious design goal:<br />Construct an implementation with desired functio...
Common metrics<br />Unit cost: the monetary cost of manufacturing each copy of the system, excluding NRE cost<br />NRE cos...
IC technology<br />Three types of IC technologies<br />Full-custom/VLSI<br />Semi-custom ASIC (gate array and standard cel...
Full-custom/VLSI<br />All layers are optimized for an embedded system’s particular digital implementation<br />Placing tra...
Semi-custom<br />Lower layers are fully or partially built<br />Designers are left with routing of wires and maybe placing...
PLD (Programmable Logic Device)<br />All layers already exist<br />Designers can purchase an IC<br />Connections on the IC...
FPGA<br />OTP    One time Programmed<br />MTP   Multi-Time Programmed<br />
RS-232 based FPGA boards<br />
Design Methodology<br />
Levels of Abstraction<br />
CMOS transistor on silicon<br />source<br />gate<br />Conducts<br />if gate=1<br />drain<br />1<br />gate<br />oxide<br />...
CMOS transistor implementations<br />source<br />source<br />gate<br />Conducts<br />if gate=0<br />gate<br />Conducts<br ...
Basic logic gates<br />x<br />x<br />F<br />F<br />x<br />x<br />F<br />x<br />F<br />y<br />x<br />F<br />x<br />y<br />x...
Introduction to VHDL<br />
What is VHDL?<br />A very verbose, complex, and powerful language <br />    for design, simulation, verification and synth...
What is VHDL?<br />Just as high-level programming languages allow complex design concepts to be expressed as computer prog...
History of VHDL <br />1980: The USA department of defense (DOD) wanted to make circuit design self documenting. <br />1983...
Verilog<br />Verilog was introduced first before VHDL, thus established itself as the de facto standard language for ASIC ...
History of Verilog<br />1981: A CAE (Computer Aided Engineering) software company called Gateway Design Automation was fou...
VHDL<br />VHDL is a programming language that allows one to model and develop complex digital systems in a dynamic environ...
Let’s Write a VHDL Model ...<br />ENTITY full_adder IS<br />PORT ( A, B, Cin : IN BIT;<br />      Sum, Cout : OUT BIT );<b...
Full Adder Architecture<br />for Cout (I.e. Carry Out):<br />Cin (I.e. Carry In)<br />A B<br />0<br />1<br />0 0<br />0<br...
Two Full Adder Processes<br />Summation:<br />PROCESS( A, B, Cin)<br />BEGIN<br /> 	Sum <= A XOR B XOR Cin;<br />END PROCE...
Full Adder<br />CIN<br />entityFull_Adderis<br />port (A, B,CIN: in BIT;<br />	         SUM, COUT: out BIT);<br />endFull_...
Basic Design Methodology<br />Requirements<br />Simulate<br />RTL Model<br />Synthesize<br />Gate-levelModel<br />Simulate...
Design Flow<br />Reading preliminary Specs. From Customer<br />Define the full definition of the problem<br />Detailed spe...
Upcoming SlideShare
Loading in …5
×

Embedded system

700 views
598 views

Published on

Published in: Education, Technology, Design
0 Comments
3 Likes
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total views
700
On SlideShare
0
From Embeds
0
Number of Embeds
13
Actions
Shares
0
Downloads
0
Comments
0
Likes
3
Embeds 0
No embeds

No notes for slide

Embedded system

  1. 1. What is an Embedded System<br /> An Embedded System is a microprocessor based system that is embedded as a subsystem, in a larger system (which may or may not be a computer system).<br />O<br />I<br />
  2. 2. Application areas<br />Automotive electronics<br />Aircraft electronics<br />Trains<br />Telecommunication<br />
  3. 3. Design challenge optimizing design metrics<br />Obvious design goal:<br />Construct an implementation with desired functionality<br />Key design challenge:<br />Simultaneously optimize numerous design metrics<br />Design metric<br /> A measurable feature of a system’s implementation<br />Optimizing design metrics is a key challenge<br />
  4. 4. Common metrics<br />Unit cost: the monetary cost of manufacturing each copy of the system, excluding NRE cost<br />NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the system<br />Size: the physical space required by the system<br />Performance: the execution time or throughput of the system<br />Power: the amount of power consumed by the system<br />Flexibility: the ability to change the functionality of the system without incurring heavy NRE cost<br />Design challenge optimizing design metrics<br />
  5. 5. IC technology<br />Three types of IC technologies<br />Full-custom/VLSI<br />Semi-custom ASIC (gate array and standard cell)<br />PLD (Programmable Logic Device)<br />
  6. 6. Full-custom/VLSI<br />All layers are optimized for an embedded system’s particular digital implementation<br />Placing transistors<br />Sizing transistors<br />Routing wires<br />Benefits<br />Excellent performance, small size, low power<br />Drawbacks<br />High NRE cost (e.g., $300k), long time-to-market<br />
  7. 7. Semi-custom<br />Lower layers are fully or partially built<br />Designers are left with routing of wires and maybe placing some blocks<br />Benefits<br />Good performance, good size, less NRE cost than a full-custom implementation (perhaps $10k to $100k)<br />Drawbacks<br />Still require weeks to months to develop<br />
  8. 8. PLD (Programmable Logic Device)<br />All layers already exist<br />Designers can purchase an IC<br />Connections on the IC are either created or destroyed to implement desired functionality<br />Field-Programmable Gate Array (FPGA) very popular<br />Benefits<br />Low NRE costs, almost instant IC availability<br />Drawbacks<br />Bigger, expensive (perhaps $30 per unit), power hungry, slower<br />
  9. 9. FPGA<br />OTP One time Programmed<br />MTP Multi-Time Programmed<br />
  10. 10. RS-232 based FPGA boards<br />
  11. 11. Design Methodology<br />
  12. 12. Levels of Abstraction<br />
  13. 13. CMOS transistor on silicon<br />source<br />gate<br />Conducts<br />if gate=1<br />drain<br />1<br />gate<br />oxide<br />IC package<br />IC <br />source<br />channel<br />drain<br />Silicon substrate<br />Transistor<br />The basic electrical component in digital systems<br />Acts as an on/off switch<br />Voltage at “gate” controls whether current flows from source to drain<br />Don’t confuse this “gate” with a logic gate<br />
  14. 14. CMOS transistor implementations<br />source<br />source<br />gate<br />Conducts<br />if gate=0<br />gate<br />Conducts<br />if gate=1<br />drain<br />drain<br />pMOS<br />nMOS<br />1<br />1<br />1<br />x<br />x<br />y<br />x<br />F = x'<br />y<br />F = (xy)'<br />x<br />F = (x+y)'<br />y<br />0<br />x<br />y<br />0<br />0<br />NOR gate<br />inverter<br />NAND gate<br />Complementary Metal Oxide Semiconductor<br />We refer to logic levels<br />Typically 0 is 0V, 1 is 5V<br />Two basic CMOS types<br />nMOS conducts if gate=1<br />pMOS conducts if gate=0<br />Hence “complementary”<br />Basic gates<br />Inverter, NAND, NOR<br />
  15. 15.
  16. 16. Basic logic gates<br />x<br />x<br />F<br />F<br />x<br />x<br />F<br />x<br />F<br />y<br />x<br />F<br />x<br />y<br />x<br />y<br />x<br />y<br />x<br />y<br />x<br />y<br />x<br />y<br />F<br />F<br />F<br />F<br />F<br />F<br />y<br />0<br />0<br />0<br />1<br />F<br />y<br />0<br />0<br />0<br />0<br />0<br />0<br />0<br />0<br />0<br />0<br />0<br />1<br />0<br />0<br />1<br />0<br />0<br />1<br />1<br />1<br />1<br />0<br />0<br />1<br />0<br />0<br />1<br />1<br />0<br />1<br />1<br />0<br />1<br />0<br />0<br />1<br />1<br />0<br />1<br />0<br />1<br />0<br />0<br />1<br />0<br />1<br />1<br />0<br />1<br />1<br />0<br />0<br />1<br />0<br />1<br />1<br />0<br />0<br />1<br />1<br />1<br />1<br />1<br />1<br />1<br />1<br />0<br />1<br />1<br />1<br />1<br />1<br />0<br />1<br />1<br />0<br />x<br />x<br />x<br />F<br />x<br />F<br />F<br />F<br />y<br />y<br />y<br />F = x y<br />XNOR<br />F = x y<br />AND<br />F = x  y<br />XOR<br />F = x<br />Driver<br />F = x + y<br />OR<br />F = (x y)’<br />NAND<br />F = x’<br />Inverter<br />F = (x+y)’<br />NOR<br />
  17. 17. Introduction to VHDL<br />
  18. 18. What is VHDL?<br />A very verbose, complex, and powerful language <br /> for design, simulation, verification and synthesis of digital systems<br />Supports many levels of abstraction, ranging from algorithm level to gate level<br />Can model concurrentand sequential behaviors of digital systems<br />Supports design hierarchy as interconnections of components<br />Can explicitly model the timing of digital systems<br />
  19. 19. What is VHDL?<br />Just as high-level programming languages allow complex design concepts to be expressed as computer programs, VHDL allows the behavior of complex electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. <br /> Like Pascal, C and C++, VHDL includes features useful for structured design techniques, and offers a rich set of control and data representation features. Unlike these other programming languages, VHDL provides features allowing concurrent events to be described. This is important because the hardware described using VHDL is inherently concurrent in its operation.<br />
  20. 20. History of VHDL <br />1980: The USA department of defense (DOD) wanted to make circuit design self documenting. <br />1983: The development of VHDL began with a joint effort by IBM, Texas Instruments and Inter-metrics. <br />1987: The institute of Electrical and Electronics Engineers (IEEE) was presented with a proposal to standardize the language. The resulting standard, IEEE 1076-1987, is the basis for virtually every simulation and synthesis product sold today. <br />1993: The VHDL language was revised to IEEE 1076-1993 <br />1996: A VHDL package for use with synthesis tools become part of the IEEE 1076 standard, specifically it is 1076.3. This greatly improved the portability of designs between different synthesis vendor tools. Another part of the standard, IEEE 1076.4 (VITAL), has been completed and sets a new standard for modeling ASIC and FPGA libraries in VHDL. This made life considerably easier for ASIC, FPGA and EDA tools vendors. <br />
  21. 21. Verilog<br />Verilog was introduced first before VHDL, thus established itself as the de facto standard language for ASIC simulation libraries; Verilog has some advantage in availability of simulation models.<br /> Another important feature that is defined in Verilog is a programming language interface PLI. The PLI makes it possible for simluation model writers to go outside of Verilog when necessary to create faster simulation models, or to create functions (using the C language) that would be difficult or inefficient to implement directly in Verilog. <br />
  22. 22. History of Verilog<br />1981: A CAE (Computer Aided Engineering) software company called Gateway Design Automation was founded by PrabhuGoel. <br />1983: Gateway released the Verilog hardware description language known as “Verilog HDL” together with a Verilog simulator. <br />1985: The language and simulator has enhanced; the new version of the simulator was called “Verilog-XL”. <br />1987: Verilog-XL was becoming very popular and has been used by many ASIC vendors. Another start-up company, Synopsys, began to use the proprietary Verilog behavioral language as an input to their synthesis product. <br />1989: Cadence bought Gateway. <br />1995: The Verilog language was reviewed and adopted by IEEE as IEEE standard 1364.<br />
  23. 23. VHDL<br />VHDL is a programming language that allows one to model and develop complex digital systems in a dynamic environment.<br />3 ways to DO IT -- the VHDL way<br />Geometric<br />Functional (Behavioral)<br />Structural<br />
  24. 24. Let’s Write a VHDL Model ...<br />ENTITY full_adder IS<br />PORT ( A, B, Cin : IN BIT;<br /> Sum, Cout : OUT BIT );<br />END full_adder;<br />Can we build the Full Adder’s architecture using these gates?<br />
  25. 25. Full Adder Architecture<br />for Cout (I.e. Carry Out):<br />Cin (I.e. Carry In)<br />A B<br />0<br />1<br />0 0<br />0<br />0<br />0 1<br />0<br />1<br />1 1<br />1<br />1<br />1 0<br />0<br />1<br />for Sum:<br />Cin (I.e. Carry In):<br />SUM<br />A B<br />0<br />1<br />CIN<br />0 0<br />0<br />1<br />0 1<br />1<br />0<br />A<br />COUT<br />1 1<br />0<br />1<br />1 0<br />1<br />0<br />B<br />
  26. 26. Two Full Adder Processes<br />Summation:<br />PROCESS( A, B, Cin)<br />BEGIN<br /> Sum <= A XOR B XOR Cin;<br />END PROCESS Summation;<br />Carry:<br />PROCESS( A, B, Cin)<br />BEGIN <br />Cout <= (A AND B) OR <br /> (A AND Cin) OR <br /> (B AND Cin);<br />END PROCESS Carry;<br />
  27. 27. Full Adder<br />CIN<br />entityFull_Adderis<br />port (A, B,CIN: in BIT;<br /> SUM, COUT: out BIT);<br />endFull_Adder;<br />architectureFull_AdderofFull_Adderis<br />begin<br /> SUM <= A xor B xor CIN after 15ns;<br /> COUT <= (A and B) or (B and CIN) or (CIN and A) after 10ns;<br />endFull_Adder;<br />SUM<br />Full_Adder<br />A<br />B<br />COUT<br />
  28. 28. Basic Design Methodology<br />Requirements<br />Simulate<br />RTL Model<br />Synthesize<br />Gate-levelModel<br />Simulate<br />Test Bench<br />ASIC or FPGA<br />Place & Route<br />TimingModel<br />Simulate<br />
  29. 29. Design Flow<br />Reading preliminary Specs. From Customer<br />Define the full definition of the problem<br />Detailed specification and architecture of the design.<br />Detailed test structure for Specs. And Architecture.<br />Design S.W. to prove the idea “C, Matlab, …” (Emulation)<br />Top-Down Design “HDL, FSM, Flowchart,…”<br />Functional simulation<br />Logic synthesis: analysis<br />Place and route<br />Real timing optimization<br />Download design on the FPGA<br />Hardware testing. <br />

×