New Development inNitride Storage Devices Rich Liu Emerging Central LabMacronix International Co., Ltd.
NBit / NROM and BeyondDespite the challenges that come with the use of BTBT HH forerasing, NBit/NROM has been successful in delivering 2-bit/cellhigh density parts.Even 4-bit/cell high density parts are feasible.However, this success is only the beginning.Beyond conventional NBit/NROM: PHINES – high programming/erase speed for both code and data Flash P-poly device – (almost) infinite endurance P-poly device with CHISEL – high programming/erase speed
Introduction to NBit / NROM Device (1): Program and Erase Band-To-Band Tunneling InducedChannel Hot Electron (CHE) Injection Hot-Hole Injection (BTBTHH) Gate = +10 V Gate = - 5 V N+-poly N+-poly OX OX SIN SIN OX Deep depletion OX n+ n+ n+ n+ P-sub=0 V P-sub=0 VSource = 0 V Drain= +5 V Source = 0 V Drain = +5 V Programming Method Erasing Method
Introduction to NBit / NROM Device (2): Read 0.0 Reverse Read Method VG=1, NA=5E17, Le=600 A, Nt=6E12 -0.5 Surface potential, -ϕs (V) Gate= +3 V -1.0 -2ψB N+-poly -1.5 VD=0 VD=0.4 OX -2.0 VD=0.8 VD=1.2 SIN Drain=1.6 V -2.5 VD=1.6 OX VD=2.0 Vbi+VD n+ n+ -3.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 P-sub=0 VSource=0 V Drain side Y position (um) Depletion region The local potential barrier induced by the extends due to the injected electrons can be shielded by the drain voltage drain voltage (DIBL). Reverse read is a local DIBL effect.
Challenges (1):The Mismatch of Electron and Hole Injections Gate Gate N+-poly N+-poly After P/E Cycling OX OX SIN SIN OX OX n+ n+ n+ n+ P-sub P-sub Injection Point Electron and Mismatch hole accumulation
Challenges (2):Retention Properties after Cycling Model A Model B Gate Gate N+-poly N+-poly OX OX SIN SIN OX OX n+ n+ n+ n+ P-sub P-sub Hole Lateral movement Hole-assisted electron during baking de-trappingExcess hole traps cause retention challenges!
Challenges (3): Hard-to-Erase and Over-Erase Hard-to-Erase Over-Erase Gate Gate N+-poly N+-poly OX OX SIN SIN OX OX n+ n+ n+ n+ P-sub P-subA small amount of electrons For a short channel device,accumulate above the channel the excess hole traps maycenter, unreachable by the BTBT lower the Vt below the EVhot-hole erase. level.
Engineering SolutionsProfiles of electrons and holes do not match: Improve interface properties Parts qualifiedData retention loss due to hole-mismatch or hole-assisted tunneling: Improve interface properties Parts qualifiedHard-to-erase and over-erase: Clever algorithms and circuit designs Parts qualified
New Solutions to Nitride Storage Device Challenges Profiles of electrons and holes do not match: Find a less localized way to erase. Fowler-Nordheim (-FN) erase. Data retention loss due to hole-mismatch or hole-assisted tunneling: Find a way that does not use hole for erase, or Find a way to eliminate excess holes Fowler-Nordheim (-FN) erase. Hard-to-erase and over-erase: Find a way to eliminate electrons from channel center; Find a way to neutralize holes from channel edge. Fowler-Nordheim (-FN) erase. However, there is a problem! -FN erase is too slow (~ 1 sec).
The Concept of –FN Erase: Dynamic Balance 7 + -FN dynamics N gate 6 VG= -18 V VG= -19 V Gate= -21 V 5 VG= -20 V Gate injection 4 + P gate J2 Vt (V) OX VG= -18 V 3 VG= -19 V J1 SIN OX Electron de-trapping VG= -20 V 2 n+ n+ 1 P-sub=0VSource=0V Drain=0V 0 10-6 10-5 10-4 10-3 10-2 10-1 100 101 Time (sec) Under –FN, dynamic balance is reached between gate injection (J2) and electron de-trapping (J1) balance point determines the final Vt. Poly work function determines the final Vt p-poly device.
Self-Converging Characteristics of –FN 6 VG=-20V 5 4 Vt (V) 3 2 1 10-6 10-5 10-4 10-3 10-2 10-1 100 101 -FN reset time (sec) No matter what is the initial Vt, after –FN RESETthe final Vt is always the dynamic balance point –self-converging Vt.
How –FN Eliminates Excess Charges -FN dynamics -FN erase after CHE or Hot-hole injection Gate= - 21 V Gate= - 21 V Gate injection J2 OX OX Hole traps J1 SIN SIN OX Electron de-trapping CHE injected electrons OX n+ n+ n+ n+ P-sub=0V P-sub=0VSource=0V Drain=0V Source=0V Drain=0V The RESET/ERASE state Vt is the dynamic balance of the gate injection (J2) and electron de-trapping (J1). Erase – Excess electrons by CHE are expelled out of nitride by –FN operation and the device can be restored to the erased state. Anneal – Excess holes in the nitride after P/E cycling are compensated by the gate injected electrons. No matter what is the initial state, the final state is the RESET state Vt.
Use P–FN to Improve Endurance and Retention Fresh device Use –FN periodically to improve reliability (P-FN) -FN reset, Vt = RV Period ~ 1,000 P/E cycles Device operates in high Vt CHE Program, Vt > PV state Use p+ poly lowers the Vt BTBT- HH Erase, Vt < EV Biases Prog. Erase Reset Read NO VG 10V -3V -10V 4.2V Conditions valid for –FN VD 5V 5V 10V 0V reset VS 0V 0V 10V 1.6V Yes VB 0V 0V 10V 0V -FN reset, Vt = RV
P–FN Improves Endurance and Retention Greatly 6.0 1 bit/cell performance Programm state Erase state 5.5 Up to 10M cycles 5.0 PV Adjustable Fixed Vt window 1.1V after 10M Vt (V) P/E pulses P/E pulses 4.5 cycles 4.0 EV 3.5 2 bits/cell performance 3.0 Up to 1M, Vt window 0.9V 100 101 102 103 104 105 106 107 400mV 2nd bit effect after P/E Cycles 1M cycles. 5.5 5.0 PV=5.2V Program Bit-1, read Bit-1 Program Bit-1, read Bit-2Highest endurance Vt (V) 4.5 Program Bit-2, read Bit-1 Program Bit-2, read Bit-2 Erase Bit-1cycle ever reported !!! 4.0 EV=3.7V 3.5 100 101 102 103 104 105 106 P/E cycles
Soft –FN Erase: A Path to Higher Performance -FN erase is slow Takes ~ 1 second. Can only be used periodically. There is another way: Hard sector erase (by BTBT HH) first Soft –FN erase for a short time (50ms) For the entire sector Soft erase eliminates hard-to-erase electrons/holes CHISEL can be used for programming CHISEL is more efficient than CHE High programming speed > 2MB/s.(CHISEL = Channel Induced Secondary Electron)
The Soft Erase Method Key = do not brutalforce = be smart. Erase Start (N=0) Use BTBT HH to domost of the erasework. Hot-Hole Erase Use –FN only forrepairing the damage. N=N+1 Sector Verify? The algorithm of Pass Pre-EV levelthis “soft erase”method resembles thatfor the “soft program” Soft Erase 50 msec -FNtechnique in floating VG= -21 V, VD/VS/VB=0 Vgate devices. Implementation in EV levelcircuits is straight Erase Doneforward.
CHISEL Programming 3.0 1.2 VG=11, Vd=4.8, Vb=0 1.0 VG=11, Vd=4.8, Vb=-1 2.5 VG=11, Vd=4.8, Vb=-2Delta VT of 1st bit (V) VG=11, Vd=4.8, Vb=-3 Delta VT (2nd Bit) 2.0 0.8 VG=11, Vd=4.3, Vb=-3 1.5 0.6 VG=11, VD=4.8, Vb=0 1.0 VG=11, Vd=4.8, Vb=-1 0.4 VG=11, Vd=4.8, Vb=-2 VG=11, Vd=4.8, Vb=-3 0.5 VG=11, Vd=4.3, Vb=-3 0.2 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Programming Time (usec) Delta VT (1st Bit) CHISEL faster programming speed with lower power consumption (body effect decreases the channel current) Increased programming throughput The second bit effect is slightly larger than CHE injection.
P/E Cycling of CHISEL Programmed Cells With 50 msec soft erase after hot-hole erase Without soft erase after hot-hole erase 6.0 5.5 5.8 5.6 5.4 CHISEL Programming: 5.0 Program 1st Bit, read 1st bit Hot-hole Erase: Program 1st Bit, read 2nd bit 5.2 1st bit: VG/VD/VS/VB=11.5/5/0/-2.5, 0.1 us VG/VD/VS/VB= -1.8/6/0/0, 1 ms Program 2nd Bit, read 1st bit 2nd bit: VG/VD/VS/VB=11.5/0/5.5/-2.5, 0.1 us VG/VD/VS/VB= -1.8/0/6/0, 1 ms 5.0 Hot-Hole Erase: Program 2nd Bit, read 2nd bitVT (V) VT (V) Soft Erase: 4.8 1st bit: VG/VD/VS/VB= -1.8/6/0/0, 1 ms Erase, read 1st bit VG= -21 V, 50 msec 4.5 Erase, read 2nd bit 4.6 2nd bit: VG/VD/VS/VB= -1.8/0/6/0, 1 ms 4.4 Program 1st bit condition: Program 2nd bit condition: VG/VD/VS/VB=11.5/0/5.5/-2.5, 0.1 us 4.2 VG/VD/VS/VB=11.5/5/0/-2.5, 0.1 us Program 1st bit, read 1st bit 4.0 4.0 Program1st bit, read 2nd bit Program 2nd bit, read 1st bit 3.8 Program 2nd bit, read 2nd bit 3.6 Erase, read 1st bit Erase, read 2nd bit 3.4 3.5 100 101 102 103 104 105 100 101 102 103 104 P/E Cycle Numbers P/E Cycle Number Only one-shot program and one-shot erase were used during P/E cycles without any P/E verify and stepping algorithm. CHISEL programming without soft erase has severe erase degradation (hard-to-erase) in less than 100 cycles. Soft erase greatly reduces the hard-to-erase. CHISEL must be used with soft erase.
Mixed Mode Flash MemoryNAND Flash:FN program, FN erase – requires small current Can program large sector simultaneously Mixed mode High program speed NROM Suitable for data. High speed X No random access – unsuitable for code. Random AccessNOR Flash:CHE program, FN erase – requires large current X Slow programming – not suitable for data Random access – suitable for code.
PHINES + FN + FN Channel BTBTHH Channel FN RESET program FN RESET (2-bits/cell) (Erase)PHINES (Program by Hole Injection Nitride Electron Storage)FN reset, BTBTHH program, FN erase – all small current Fast programming – suitable for data. Random access – suitable for code. Two-bits/cell – high density. No hard-to-erase, no over-erase – good endurance. Combines the benefits of NAND & NOR.
SummaryNBit/NROM is a low-cost, high-density, 2-bit/cell technology.Using engineering solutions, NBit/NROM delivers its promises.Beyond NBit/NROM PHINES shows promise for mixed mode Flash (both code and data). –FN and P-poly devices are also promising: Use –FN periodically (1,000 P/E cycles) gives excellent endurance and data retention. Soft erase (a short –FN) after the sector erase also works Using soft-erase, we can improve the programming speed – both code and data Flash.NBit/NROM’s success is only the beginning.
NBit / NROM Scalability (I)Left and right bits merge Charge distribution is ~ 20-30 nm Does this imply scaling is impossible below 60nm? However, this is not the issue Reverse read – long channel deviceInformation is still retrievableeven after the left and right bitsstart to merge.Scalable to < 40 nm(corresponding to < 30nmtechnology node). Reverse read – Short channel device
NBit / NROM Scalability (II) Second-bit effect Shorter channel Incomplete local DIBL Vt (Left bit) shielding Vt (left) shifts up when right bit is programmed Causes Vt window loss More severe for short channel device Vt (Right bit) Scaling below 30 nmVt (Left bit) Increase read drain voltage SOI device Higher Vd Double gate structure Vt (Right bit)
NBit / NROM Scalability (III) Scaling below 30nm Separated nitride device1 Use side wall process to fabricate two separated SiN stripes Charges are stored in SiN Separated SiN device only1. Y.K. Lee, et al. (KAIST, Korea), IEEE Electron Device Letters, May 2004(30nm device demonstrated) Charge trapping in separated SiN device