Physical Design Services


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eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.

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  • Title Slide
  • eInfochips has been around for 19 years, and has been cash positive, debt free and Profitable since inception. Today, we are over a thousand professionals operating from 10 design centers and 12 sales offices. Our US HQ is in Sunnyvale while the India HQ is in Ahmedabad. We foresee strong business growth over the next few years. Since the beginning of 2013, we have invested in 2 new design centers in Ahmedabad and Noida, while we have doubled the capacity in Pune and Bangalore. This picture is of our new facility in Ahmedabad, inaugurated in June. It is a fantastic place, with an ‘Experience Zone’ that has on display some of the products we have designed for our clients. I would strongly recommend that you should visit us in Ahmedabad.

    Most technology companies from India have a strong presence in IT / ERP / CRM solutions. On the contrary, we are a pure-play Product Engineering Services company. 100% of our business comes from building and sustaining products – whether that are made of Software, Embedded or Hardware, or a combination of these.

    I am sure you get the difference – For IT Services, the user profile is known. The deployment environment is favorable, and familiar. Users are well trained with the system. Also, if a CRM system crashes, there are 50 people on the premises who are specifically there to fix it.

    On the contrary, when we make a home automation system, the users could be literate/semi-literate or illiterate, young and old.

    When we develop a UAV Software, we have no idea on the conditions it will have to endure. And how many people read the user manual before using a camera?

    Biometric access devices we develop are deployed in military bases over Iraq and Afghanistan. If that system crashes, there isn’t an engineer in a thousand miles who could fix it, while the impact could potentially be catastrophic.

    In short, Product Engineering Services has very stringent quality benchmarks, and we specialize at building critical and complex systems, as we will cover later in the presentation.
  • Physical Design Services

    1. 1. eInfochips Spec to Silicon Services
    2. 2. 2 Product Engineering Services Company Bangalore Chennai Pune Ahmedabad Noida Toronto London BostonChicago Dallas Austin Cedar Rapids Cincinnati Raleigh Sunnyvale 10 Design Centers 12 Sales Offices 1200 Professionals 19 Years Solid Track Record Stable & Secure Cash Positive, Debt-free and Profitable
    3. 3. Semiconductor Journey • 10+ Dedicated Design Center • 5 Design IPs • Intel Strategic Partnership 2002-05 2008 2011 2013 • 8 Dedicated Design Center • 3 Design IPs, 3 VIPs • Synopsys Partnership • A stepping stone in VIP area • Cadence Partnership Launched 7 eVCs Offerings ASIC/FPGA Verification Offerings ASIC/SoC/FPGA Design ASIC/FPGA Verification Offerings Physical Design ASIC/SoC/FPGA Design ASIC/FPGA Verification Offerings Design for Testability Physical Design ASIC/SoC/FPGA Design ASIC/FPGA Verification 3 • Talent ecosystem 250 150 50 400
    4. 4. Turnkey Silicon Offerings Concept - Specification Design - RTL Design - Simulation - IP Integration Architecture – Design Verification - Functional Verification - Verification IP Development Synthesis - Netlist Physical Design - RTL to GDSII - DFT Services - Layout Migration GDSII Silicon Validation - ASIC Prototyping - Chip Bring Up - Silicon Turn-on 4
    5. 5. Tools Expertise ASIC Design •QuestaSim •Modelsim •VCS •Design & DFT Compiler •PT FPGA Design •Synplify-Pro •Xilinx-ISE •Altera-QuartusII •Actel-Libero •ChipScope •SignalTapII •Leonardo Spectrum •PCie Analyzer •Logic Analyzer •O-Scope •CHIPit-PlatinumV4 •HAPS Board •Palladium, EVE Verification •IUS •NC-Sim •Conformal •Questasim •Modelsim •Formality •FinSim, VeriLint •exploreRTL, LEDA •Verix, SureCov •CoverMeter •HDLScore •NextGen MVRC •IUS LP, CLP LEC Implementation •Magma Talus •Blast & Quartz •Synopsys DC •ICC, Astro •PrimeTime, PTSI •TetraMAX •StarRC XT •MG Calibre •SoC Encounter •Celtic, Nanoroute •Virtuoso, Conformal LEC Vertex Spartan Kintex Cyclone Flex Nios A3P Series 5
    6. 6. eInfochips Turnkey Lab Design • 20M Gate Count • 37 Clock Domain; up to 500MHz Verification • 180M Gate Count SoC • 14 VIPs Physical Design • 85+ Tape-outs: 130nm– 16nm • 230M Gate Count Silicon Validation • 15+ Pre-silicon FPGA Prototypes • 11 Evaluation Modules Design • DC Ultra, Design Vision, HDL Physical Design • StarRC, IC Validator & Compiler • PrimeRail, PrimeTime SI Design For Testability • DFTMAX, DFT Compiler • TetraMAX Verification • Formality, VCS-MX • Mature processes evolved over two decades of delivery excellence Comprehensive internal checklists for guaranteed first-pass silicon success • Dedicated Project Management Office for Silicon Design Engineering team 6
    7. 7. Physical Design Services. Services •RTL Synthesis •DFT, ATPG & Fault grading services •Hierarchical Floor planning and Partitioning •Multi-power island designs, power analysis (low power design) •Place & Route •Customized Clock Tree Synthesis •Signal Integrity Analysis •Physical Verification & DFM •Post-Layout ATPG Simulation •Chip / ASIC Layout Migration •ECO Implementation for functional & timing fixes Domain Expertise •Networking & Communication •Wired, Wireless •Multimedia / Consumer Electronics •High End Processors (GPU, APU, Multi CPU ASICs) •Automotive
    8. 8. eInfochips’ Physical Design Differentiators Outcome : 1. 85+% Area Utilization, 95+% High VT Cells on wireless SoC 2. Timing closure on 150 Mn gate count ASIC on rectilinear Floorplan 3. High performance design timing closure with < 1% of LVT cells ensuring power requirements on Networking SoC 4. Low power designs with multiple voltage domains on Tablet SoC  Complete Turnkey Ownership : 85+Silicon Tape-outs across 180 to 16nm  Comprehensive checklist to ensure first time right silicon: Netlist to GDSII in < 3 iterations  Technical Expertise : • Expertise in physical design flow & methodologies using EDA tools from all four major vendors (Synopsys, Magma, Cadence, Mentor Graphics) helps in achieving good results irrespective of tools. • Experience in tape-outs to foundries like TSMC, UMC, GF, Toshiba, TI and CHARTERED • Dedicated Subject Matter Experts (SME) for each stage of Physical design, Different Methodology (Flow), Tools • Advanced Interface expertise: SerDes, MIPI, PCIe3, DDR, High Speed CPUs • Combination of Die Size Reduction and Clock Speed Improvement cost of derivative SoCs  Domain Expertise : Projects across Networking, CE, Telecom, Mobile for Area, Power & Time optimization for domain specific require.  Unique training program includes basic and advanced Physical design practices and how each Physical Design activity impacts Quality, Product schedule, Time to Market and Business.
    9. 9. DFT Expertise and Service Offerings Initial Phases •DFT Evaluation and Assessment •DFT Architecture and Methodology Development •DFT Automation •Design vs Test Time & DFT Trade-offs •ATPG Library Generation Expertise •20+ tapeouts and Silicon turn-on •Signoff with various EDA tools •28nm,40nm, 45nm, 90nm, 130nm technologies •Multiple Clock Domains •On-chip IP DFT Analog blocks •Makefile and Tcl based flow development Implementation •Scan Insertion •Adaptive/Compressed scan logic •Add/Optimize Test Control Logic •ATPG - Vector Generation and GLS •Memory BIST •JTAG Insertion compliant to both IEEE1149.1 and IEEE1149.6 standards •Fault Simulation and Grading •Silicon turn-on •Manufacturing Test Program Debug assistance •Failure Analysis assistance
    10. 10. eInfochips’ DFT Differentiators • Flexible DFT engagement model starts from DFT Architecture to Silicon Turn-on • 20+ successful Silicon tape-outs and Silicon Turn-on • Subject Matter Experts for Scan, MemBIST, JTAG, ATPG, Equivalence check, Silicon Turn-on and failure diagnoses • Comprehensive and well documented checklist to ensure first time right silicon with maximum test coverage • Unique training program includes how DFT activity impacts Profitability, Cost for the Test and Time to Market • Expertise in DFT flow & methodologies using EDA tools from all three major vendors (Synopsys, Cadence and Mentor Graphics) • Experience in tape-outs to foundries like TSMC, UMC, TI & TOSHIBA
    11. 11. Thank you For more information, write us at or visit