Polysilicon MOSFET as a SpinFET base


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This presentation highlights the main points of my senior thesis for Elecctrical Engineering at the University of Utah. The subject of my research was the theory and fabrication of a spinfet, which incorporates the spin of an electron, not just its charge, into the overall function of a mosfet device.

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Polysilicon MOSFET as a SpinFET base

  1. 1. Polysilicon MOSFET as a SpinFET base <ul><li>Current technology uses electron charge </li></ul><ul><li>Spin MOSFET, SpinFET, manipulates charge and spin of electron </li></ul><ul><li>Fabrication of necessary feature sizes currently requires SEM nano-lithography </li></ul><ul><ul><li>Mainstream lithography options available by 2020 </li></ul></ul>
  2. 2. NMOSFET Background <ul><li>Fabrication of polysilicon NMOSFET (NMOS) using a self aligning process </li></ul><ul><li>NMOS is a four contact device. </li></ul><ul><li>MOS capacitor operates in four modes </li></ul><ul><ul><li>Accumulation </li></ul></ul><ul><ul><li>Flat band </li></ul></ul><ul><ul><li>Depletion </li></ul></ul><ul><ul><li>Inversion </li></ul></ul><ul><li>Fabrication accomplished in four processing steps. </li></ul><ul><li>Possible 1um features in University of Utah microfab facility </li></ul><ul><li>ITRS published projections estimate physical gate lengths on the order of 18nm by 2010 . </li></ul>
  3. 3. Processing Steps <ul><li>Four patterning masks used in process: </li></ul><ul><ul><li>Gate oxide </li></ul></ul><ul><ul><li>Polysilicon gates </li></ul></ul><ul><ul><li>Contact vias </li></ul></ul><ul><ul><li>Metal contact pads </li></ul></ul><ul><li>Additional steps required for doping and polysilicon deposition. </li></ul><ul><li>Spin on Glass (SOG). This is applied using a standard spinner and then baked for one hour ramping the temperature from 250C to 400C. </li></ul><ul><li>A metal pad is connected to the polysilicon gate for probing and bonding. </li></ul>
  4. 4. SpinFET Concept <ul><li>Traditional semiconductors make use of the electron charge but not its spin. </li></ul><ul><li>SpinFET devices will utilize both the charge and spin of the electron to create a modified 2D electron system that is spin coupled. </li></ul><ul><li>Poisson’s equation shows the potential at the Si-Si0 2 interface of a traditional MOS capacitor. Four regimes are considered including accumulation, flat band, depletion and inversion. </li></ul><ul><li>In the SpinFET device, the 2D electron system will not be uniform but will have localized potential peaks that confine electrons in the inversion layer to lattice points at the Si-Si0 2 surface. Adjacent electrons will couple due to Coulomb repulsion and take opposite spins. </li></ul>
  5. 5. SpinFET Fabrication Steps <ul><li>Several additional processing steps are required to create a SpinFET device from an NMOSFET device. These steps occur after depositing phosphorus and before applying spin on glass </li></ul><ul><ul><li>Apply PMMA </li></ul></ul><ul><ul><li>Pattern spin lattice using SEM. Lattice features will be on the order of 20-50 nm. </li></ul></ul><ul><ul><li>Develop </li></ul></ul><ul><ul><li>Use reactive ion etching to etch lattice pattern through polysilicon and gate oxide just slightly etching Si surface </li></ul></ul>
  6. 6. Actual Devices <ul><li>Development of the polysilicon process required some refining and further characterizing various process parameters </li></ul><ul><ul><li>Polysilicon etch rates needed adjustment from SOP definitions. </li></ul></ul><ul><ul><li>SOG etch rates were considerably faster than traditional field oxide etch rates. Experiment revealed etch rates of 10nm/sec. </li></ul></ul><ul><ul><li>SEM alignment patterns were changed and new masks made to ensure proper focus of electron beam during patterning. New alignment marks were placed on top of a gate oxide layer to be at the same height as polysilicon gates. </li></ul></ul>
  7. 7. Preliminary Characterization <ul><li>Test devices on the die include </li></ul><ul><ul><li>Polysilicon resistors. Measurements indicate a resistance of 1.2 ohms per square. </li></ul></ul><ul><ul><li>Substrate to poly and poly to metal capacitors to test quality and thickness of oxide layers. Due to the drastically different etch rate for SOG no substrate contact is achieved. </li></ul></ul><ul><li>NMOSFET devices were measured before and after annealing. Standard MOS curves were not achieved. After annealing curves merged and appeared resistive. </li></ul><ul><li>Analysis and discussion… </li></ul>
  8. 8. Conclusions <ul><li>Traditional CMOS fabrication using a polysilicon self aligning gate is mainstream. </li></ul><ul><li>Minor adjustments to the CMOS fabrication process make possible the fabrication of a spin lattice device </li></ul><ul><li>Small feature sizes currently achieved using e-beam lithography are projected to be mainstream by 2010. This makes large scale production of SpinFET technology possible within five years. </li></ul><ul><li>Some of the theoretical predictions for SpinFET devices include decreased power consumption and superconductivity due to a bandgap structure controlled by an applied gate voltage. </li></ul>
  9. 9. Thank You! Questions