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Spdas1 vlsibput Spdas1 vlsibput Presentation Transcript

    • VLSI
    • What is VLSI?
      • “ Very Large Scale Integration”
    • SSI – Small-Scale Integration (0-10 2 )---1960
    • MSI – Medium-Scale Integration (10 2 -10 3 )---1967
    • LSI – Large-Scale Integration (10 3 -10 5 )---1972
    • VLSI – Very Large-Scale Integration (10 5 -10 7 )---1978
    • ULSI – Ultra Large-Scale Integration (>=10 7 )---1989
    • GSI _ Giant Scale Integration (>=10 9 )---2000
    • *Where these are given as no of transistors.
  • Integration Level Trends Obligatory historical Moore’s law plot
  •  
    • Integrated Circuits/MEMs
      • Hierarchy of various technology
      • Semiconductor process
      • Silicon
      • GaAs
      • Unipolar
    Bipolar Unipolar Bipolar ECL TTL NMOS PMOS CMOS
    • Chips
    • Integrated circuits consist of:
      • A small square or rectangular “die”, < 1mm thick
        • Small die: 1.5 mm x 1.5 mm => 2.25 mm 2
        • Large die: 15 mm x 15 mm => 225 mm 2
      • Larger die sizes mean:
        • More logic, memory
        • Less volume
        • Less yield
      • Dies are made from silicon (substrate)
        • Substrate provides mechanical support and electrical common point
  • Advancements over the years
    • © Intel 4004 Processor
    • Introduced in 1971
    • 2300 Transistors
    • 108 KHz Clock
    • © Intel P4 Processor
    • Introduced in 2000
    • 40 Million Transistors
    • 1.5GHz Clock
  • System Design Pyramid
  • • Photo-litho-graphy: lati n: light-stone-writing • Photolithography: an optical means for transferring patterns onto a substrate. • Patterns are first transferred to a photoresist layer . • Typically a wafer is about 8-10 inches in diameter. Individual ICs are placed inside it. Photolithography and Patterning
  • Photoresist is a liquid film that is spread out onto a substrate, exposed with a desired pattern, and developed into a selectively placed layer for subsequent processing. • Photolithography is a binary pattern transfer : there is no gray-scale, color, nor depth to the image.
  •  
  •  
  •  
    • Steps
    • Photo resist Coating (covering)
    • A light sensitive organic polymer (plastic)
    • Mask/ Reticle formation
    • Exposure to light (UV/X-RAY/E-BEAM)
  •  
  •  
  • WHAT IS A PHOTOMASK? Photomasks are high precision plates containing microscopic images of electronic circuits. Photomasks are made from very flat pieces of quartz or glass with a layer of chrome on one side. Etched in the chrome is a portion of an electronic circuit design. This circuit design on the mask is also called geometr y.
  • The Resist The first step is to coat the Si/SiO 2 wafer with a film of a light sensitive material, called a resist. A resist must also be capable of high fidelity recording of the pattern (resolution) and durable enough to survive later process steps Solvent Evaporates
  •  
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  • Photolithography Energy - causes (photo)chemical reactions that modify resist dissolution rate Mask - blocks energy transmission to some areas of the resist Aligner - aligns mask to previously exposed layers of the overall design Resist - records the masked pattern of energy Energy Mask + Aligner Photoresist Wafer
  • Next Generation Lithography In 1996, five technology options were proposed for the 130 nm gate length technology: • X-ray proximity Lithography (XPL) • Extreme Ultraviolet (EUV) • Electron Projection Lithography (EPL) • Ion Projection Lithography (IPL) • Direct-write lithography (EBDW). These options were referred to as the next generation lithography.
  •  
  • MOSFET Design Rules
    • Lambda based design Rule
    • Micron Rule
  • Minimum width and Spacing
    • Layer Value
    • Poly 2L
    • Active 3L
    • N select 3L
    • Metal 3L
  • Stick Diagrams Metal poly ndiff pdiff Can also draw in shades of gray/line style.
    • Wiring Tracks
    • A wiring track is the space required for a wire
      • 4  width, 4  spacing from neighbor = 8  pitch
    • Transistors also consume one wiring track
    • Well spacing
    • Wells must surround transistors by 6 
      • Implies 12  between opposite transistor flavors
      • Leaves room for one wire track
  • Basic Circuit Layout Stick Diagram Stick Diagrams Gnd V DD X X X X V DD Gnd
  • Layout Diagrams Stick Diagrams Gnd V DD X X X X V DD Gnd
    • Example: Inverter
  • MOSFET Arrays and AOI Gates A B C y x y x A B C
  • Parallel Connected MOS Patterning x y A B X X X A B x y
  • Alternate Layout Strategy A B x y X X X X x A B y
  • MOSFET Arrays and AOI Gates NAND2 Layout Vp Gnd Gnd Vp X X X X X
  • NOR2 Layout Vp Gnd Vp Gnd X X X X X
  • Stick Diagrams Power Ground B C Out A
  • Cells, Libraries, and Hierarchical Design
    • Creation of a Cell Library
    Gnd X X X X X X X X V DD X
  • X X X X X X X X X V DD Gnd X
  • Gnd X X X X X X X X X V DD
    • Cell Placement
    • System Hierarchy (MOSFET-Gates-F/Fs-Registers-Networks-Systems)
    • Floorplans and Interconnect Wiring
    • Y= (# of Good Chips/Total No)*100%
    • Y=Yield
    • ‘ Y’ depends on total area=A, and no of defects=D,
    • Y=e *100%
  • Interconnects
    • Place and Route Algorithm.
    • Wiring Delay
    • td=kl 2
    • l=length of inter connect.
    td