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    • 1 2 3 4 5 6 7 8 PCB STACK UP QT8 SYSTEM DIAGRAM 01 DDRII-SODIMM1 DDRII 667/800 MHz LAYER 1 : TOP AMD Lion CPU THERMAL LAYER 2 : IN1 PAGE 7,8 Sabie SENSORA LAYER 3 : IN2 Griffin 14.318MHz A S1G2 Processor PAGE 5 LAYER 4 : VCC DDRII-SODIMM2 DDRII 667/800 MHz 638P (uPGA)/35W LAYER 5 : IN3 PAGE 7,8 PAGE 3,4,5,6 CPU_CLK LAYER 6 : BOT NBGFX_CLK CLOCK GEN NBGPP_CLK ICS9LPRS476AKLFT-->HP SBLINK_CLK SLG8SP626VTR-->HP HT3 RTM880N-795 -->HP PAGE 2 PCI-Express 16X PCI-E HDMI 10 PCI-E WLAN Card x1 PAGE 23 ATI M82-S PAGE 36 Cable VGA X1 X1 X3 NORTH BRIDGE for Discrete Docking RJ-45 Express Mini PCI-E CRT 11 TV-TUNER Card x1 LAN RX781 / RS780MN only CIR/Pwr btn Realtek Card Card PAGE 24 PAGE 36 SPDIF Out PCIE-LAN A12 64 Bit,DDR2*4 7 (NEW CARD) (Wireless LAN/TV Express Card x1 Stereo MIC RTL8102E/8111C 21mm X 21mm, 528pin BGA LVDS M82-SCE A11 PAGE 33B TUNNER) B Headphone Jack (10/100/GagaLAN) Side port PAGE 23 4 USB Port PAGE 31,32 PAGE 33 PAGE 36 PAGE 17,18,19 Cable Docking x1 VOL Cntr PAGE 8,9,10,11, 20,21,22 PAGE 37 PAGE 37 256mb RAM for UMA only RJ45 ALINK X4 PAGE 8 SBSRC_CLK PAGE 31 SYSTEM CHARGER(ISL6251A) USB2.0 PAGE 44 TWO SATA - HDD SATA0,1 150MB 1,8,9 5 2 6 3 USB2.0 Ports Blueflame Webcam Fingerprint Flash Media Touch Screen PAGE 33 SOUTH BRIDGE for UMA only for Discrete SYSTEM POWER ISL6236IRZA-T X3 PAGE 30 PAGE 30 X1 PAGE 30 PAGE 30 RTS5158 only PAGE 38 SB700 A12 SATA - CD-ROM SATA0 150MB PAGE 25 21mm X 21mm, 528pin BGA PCIE BUS JMICRON DDR II SMDDR_VTERM PAGE 33 JMD380 for 1.8V/1.8VSUS(TPS51116REGR) 4.5W(Ext) DiscreteC PAGE 41 E-SATA SATA4 150MB 4.3W(Int) only C Azalia PAGE 30 PAGE 12,13.14.15.16 PAGE 27 VCCP +1.1V AND +1.2V(MAX8717) SMBUS PAGE 39 Accelerometer IDT LIS3LV02DL PAGE 28 LPC 92HD71B7 VGACORE(1.1V~1.2V)Oz8118 MDC CONN PAGE 27 PAGE 42 Keyboard PAGE 34 PAGE 29 Touch Pad PAGE 34 ENE KBC IEEE1394 connect for Memory CardReader Discrete CPU CORE ISL6265A CIR (AUDIO CONN) KB3926 Cx AUDIO only PAGE 40 PAGE 27 Amplifier TPA6017A2 PAGE 26 PAGE 25 SMBUS TABLE Capacitive Sense PAGE 35 PAGE 28 Clock gen/Robson/TV tuner SW PAGE 34 SB--SCL0/SD0 /DDR2/DDR2 thermal/Accelerometer +3VD D Digital MIC AUDIO CONN Audio epress card (Phone/ MIC) Conn Wlan Card +3VS5 PAGE 30 PAGE 27 PAGE 28 FAN SPI PROJECT : QT8 EC --SCL/SD Battery charge/discharge +3VPCU Quanta Computer Inc. PAGE 37 PAGE 35 Size Document Number Rev EC--SCL2/SD2 VGA thermal/system thermal +3V Custom 1A Block Diagram NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 1 of 45 1 2 3 4 5 6 7 8
    • 5 4 3 2 1 +1.2V L49 600 ohms@100Mhz 60 ohm, 0.5A BLM18PG181SN1D(180,1.5A)_6 C523 10U/6.3V_8 C518 0.1U/10V_4 C496 0.1U/10V_4 C527 +1.2V_CLKVDDIO C521 0.1U/10V_4 0.1U/10V_4 C476 0.1U/10V_4 C515 0.1U/10V_4 CLOCKS name NBGFX_CLKP NBGFX_CLKN RX780 RP64 STUFF RS780 RP64 STUFF Clock pin function to NB for VGA reference clock 02 EXT_GFX_CLKP RP66 STUFF RP66 NC to M82-S external reference clock -RX780 only EXT_GFX_CLKN DCR: 0.5 ohm NBGPP_CLKP to NB for RX780 for PCIEX2 interface reference clock onlyD +3V_CLKVDD D 600 ohms@100Mhz NBGPP_CLKN RP70 STUFF RP70 NC RS780 is internal share with AC-LINK clock,RS780 not need 60 ohm, 0.5A +3V L51 +3V_CLKVDD BLM18PG181SN1D(180,1.5A)_6 SBLINK_CLKP to NB for AC-LINK reference clock C541 C468 C473 C512 C522 C508 C500 C474 C471 C469 SBLINK_CLKN RP72 STUFF RP72 STUFF 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 CLK_VGA_27M_SS R653,R656,R612 R653,R656,R612 To M82-S 27Mhz - RX780 only Place very CLK_VGA_27M_NSS STUFF NC +3V_CLKVDD close to C/G L42 BLM18PG181SN1D(180,1.5A)_6 +3V_CLK_VDDA U10A Place within 0.5" R196 *261_4 Del RP for TP on PV of CLKGEN C464 C482 49 56 CPUCLKP RP43 4 3 *0_4P2R_4 CPUCLKP VDDA CPUKG0T_LPRS CPUCLKP 3 10U/6.3V_8 0.1U/10V_4 48 55 CPUCLKN 2 1 CPUCLKN GNDA CPUKG0C_LPRS CPUCLKN 3 +3V_CLK_VDDA 62 VDDREF ATIG0T_LPRS 33 NBGFX_CLKP RP54 4 3 *0_4P2R_4 NBGFX_CLKP NBGFX_CLKP 10 to NB for external Graphics 66 32 NBGFX_CLKN 2 1 NBGFX_CLKN GNDREF ATIG0C_LPRS 31 EXT_GFX_CLKP RP53 4 3 *0_4P2R_4 EXT_GFX_CLKP NBGFX_CLKN 10 reference clock ATIG1T_LPRS EXT_GFX_CLKP 17 C470 69 VDD48 ATIG1C_LPRS 30 EXT_GFX_CLKN 2 1 EXT_GFX_CLKN EXT_GFX_CLKN 17 to M82-S -RX780 only 0.1U/10V_4 29 26 VDDATIG ATIG2T_LPRS T196 54 VDDCPU ATIG2C_LPRS 25 T84 61 VDDHTT 38 40 PCIE_MINI2_CLKP RP48 4 3 *0_4P2R_4 PCIE_MINI2_CLKP VDDSB_SRC SB_SRC0T_LPRS PCIE_MINI2_CLKP 36 17 VDDSRC SB_SRC0C_LPRS 39 PCIE_MINI2_CLKN 2 1 PCIE_MINI2_CLKN PCIE_MINI2_CLKN 36 to TV TUNER CARDC +3V_CLKVDD 44 35 CLK_PCIE_CARD RP55 4 3 *0_4P2R_4 CLK_PCIE_CARD C VDDSATA SB_SRC1T_LPRS CLK_PCIE_CARD 26 3 VDDDOT SB_SRC1C_LPRS 34 CLK_PCIE_CARD# 2 1 CLK_PCIE_CARD# CLK_PCIE_CARD# 26 to PCIE-CARD READER 53 23 NBGPP_CLKN_R Del RP52 for NBGPP CLK VDDCPU_IO SRC0T_LPRS T59 28 22 NBGPP_CLKN_L VDDATIG_IO SRC0C_LPRS T62 37 21 PCIE_NEW_CLKP RP51 4 3 *0_4P2R_4 PCIE_NEW_CLKP VDDSB_SRC_IO SRC1T_LPRS PCIE_NEW_CLKP 33 12 VDDSRC_IO1 SRC1C_LPRS 20 PCIE_NEW_CLKN 2 1 PCIE_NEW_CLKN PCIE_NEW_CLKN 33 to EPRESS CARD +1.2V_CLKVDDIO 18 16 PCIE_MINI1_CLKP RP49 4 3 *0_4P2R_4 PCIE_MINI1_CLKP VDDSRC_IO2 SRC2T_LPRS PCIE_MINI1_CLKP 36 SRC2C_LPRS 15 PCIE_MINI1_CLKN 2 1 PCIE_MINI1_CLKN PCIE_MINI1_CLKN 36 to WLAN 14 SBLINK_CLKP RP47 4 3 *0_4P2R_4 SBLINK_CLKP SRC3T_LPRS SBLINK_CLKP 10 C466 33P/50V_4 CG_XIN 72 GND48 SRC3C_LPRS 13 SBLINK_CLKN 2 1 SBLINK_CLKN SBLINK_CLKN 10 to NB for AC-LINK reference clock 27 10 SBSRC_CLKP RP45 4 3 *0_4P2R_4 SBSRC_CLKP GNDATIG1 SRC4T_LPRS SBSRC_CLKP 12 2 6 GNDDOT SRC4C_LPRS 9 SBSRC_CLKN 2 1 SBSRC_CLKN SBSRC_CLKN 12 to SB Y2 52 8 PCIE_LAN_CLKP RP44 4 3 *0_4P2R_4 PCIE_LAN_CLKP GNDCPU SRC5T_LPRS PCIE_LAN_CLKP 31 14.318MHZ 58 GNDHTT SRC5C_LPRS 7 PCIE_LAN_CLKN 2 1 PCIE_LAN_CLKN PCIE_LAN_CLKN 31 to PCIE-LAN 47 46 1 GNDSATA SRC6T/SATAT_LPRS C465 33P/50V_4 CG_XOUT 36 GNDSB_SRC SRC6C/SATAC_LPRS 45 SI-1 Modified --remove to ROBSON 11 5 CLK_VGA_27M_SS R527 33_4 OSC_SPREAD GNDSRC1 SRC7T_LPRS/27Mhz_SS OSC_SPREAD 18 19 GNDSRC2 SRC7C_LPRS/27Mhz_NS 4 CLK_VGA_27M_NSS R215 75/F_4 EVGA-XTALI 18 SSIN - for M82 - 3.3V level input R490 100/F_4 X_TALIN --for M82 -1.8V level input HTT0T/66M_LPRS 60 CG_XIN 67 59 NBHTREFCLK0P R193 0_4 NBHT_REFCLKP X1 HTT0C/66M_LPRS NBHT_REFCLKP 10 CG_XOUT 68 71 NBHTREFCLK0N R194 0_4 NBHT_REFCLKN X2 48MHz_0 NBHT_REFCLKN 10 70 CLK_48M_CR_L R201 33_4 CLK_48M_CR 48MHz_1 CLK_48M_CR 25 CLK_PD# 57 CLK48MUSB R192 33_4 CLK_48M_USB Ra PD# CLK_48M_USB 13 can remove MOSFET level shift REF0/SEL_HTT66 65 SEL_HT66 R186 158/F_4 SB/clock gen / DDR2 is 3.3V/S0 64 SEL_SATA REF1/SEL_SATA T58 PCLK_SMB 1 63 SEL_27 R184 1 2 90.9/F_4 power level 6,7,13,28,36 PCLK_SMB PDAT_SMB SMBCLK REF2/SEL_27 T167 EXT_NB_OSC 10 6,7,13,28,36 PDAT_SMB 2 SMBDAT 24 CLKREQ0# RbB CLKREQ0# EXT_NWD_CLK_REQ# B CLKREQ1# 51 EXT_NWD_CLK_REQ# 33 50 CLKREQ2# SB_SRC_SLOW# CLKREQ2# CLKREQ3# 14 CHIPSET_PCIE_SLOW_SB# 1 2 41 SB_SRC_SLOW# CLKREQ3# 43 RX780 RS780 D17 *CH501H-40PT L-F 42 CLKREQ4# CLKREQ4# Clock chip has internal serial 1.8V 1.1V terminations when driven lowSB_SRC clocks slow only supported with SLG8SP626VTR for differencial pairs, external resistors Ra 82.5R 158R to reduced setpoint custom CG IC 73 THERMAL GND 77 are 74 eGND73 eGND77 76 reserved for debug purpose. Rb 130R 90.9R eGND74 eGND76 75 eGND75 eGND78 78 +3V RES CHIP 130 1/16W +-1%(0402)L-F -->CS11302FB15 U10B RES CHIP 158 1/16W +-1%(0402) -->CS11582FB00 C952 *10P/50V_4 EXT_NB_OSC R756 *8.2K_4 CLKREQ0# SLG8SP626VTR RES CHIP 90.9 1/16W +-1%(0402) -->CS09092FB15 R757 *8.2K_4 CLKREQ2# +3V_CLKVDD RES CHIP 82.5 1/16W +-1%(0402) -->CS08252FB11 C953 *10P/50V_4 CLK_48M_USB R758 *8.2K_4 CLKREQ3# R759 *8.2K_4 CLKREQ4# ICS ICS9LPR476BKLFT--AJRS4760000 C954 *10P/50V_4 CLK_48M_CR if use clock SLG SLG8SP626VTR--AJ006260000 C955 *10P/50V_4 EVGA-XTALI +3V request pin , need RTL RTM880N-795-- AJ008800000 to pull Hi for C956 *10P/50V_4 OSC_SPREAD default sttting * default R189 R195 EXT_NWD_CLK_REQ# 8.2K_4 R219 *8.2K_4 8.2K_4 66 MHz 3.3V single ended HTT clock CLK_PD# 8.2K_4 R204 1 SEL_27 SI-1 modified -- reserve for EMT SEL_HTT66 SEL_SATA SB_SRC_SLOW# 8.2K_4 R261A 0* 100 MHz differential HTT clock SEL_HT66 A 100 MHz non-spreading differential SRC clock SEL_SATA 1 R203 R202 8.2K_4 0* 100 MHz spreading differential SRC clock *8.2K_4 SEL_27 1* 27MHz non-spreading singled clock PROJECT : QT8 0 100 MHz spreading differential SRC clock Quanta Computer Inc. RS780M/RX780M Size Document Number Rev Custom 1A Clock Generator NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 2 of 45 5 4 3 2 1
    • 5 4 3 2 1 BLM21PG221SN1D(220,100M,2A)_8 CPU_THERMDC R569 0_4 03 W/S= 15 mil/20mil H_THRMDC 5 +2.5V +CPUVDDA CPU_THERMDA R567 0_4 H_THRMDA 5 L36 CPU CLK CPU_LDT_RST# 300_4 R142 +1.8V +1.2V +1.2V_VLDT C416 LS0805-100M-N C392 C368 C363 CPUCLKP CPU_LDT_STOP# 300_4 R140 2 CPUCLKP 10U/6.3V_8 4.7U/6.3V_6 0.22U/6.3V_4 3300P/50V_4 CPUCLKN CPU_PWRGD 300_4 R144 2 CPUCLKN R474 0_8 CPU_LDT_REQ#_CPU 300_4 R563 SI-2 modified -- Keep trace from resisor to CPU within 0.6" confirm AMD R563 R473 0_8 +1.2V_VLDT +CPUVDDA keep trace from caps to CPU within 1.2" U31D need to stuff U31A W/S= 15 mil/20mil +CPUVDDA F8 M11 C739 4.7U/6.3V_6 +1.2V_VLDT +1.2V_VLDT 4.7U/6.3V_6 C840 CPUCLKIN R137 169/F_4 CPUCLKIN# +CPUVDDA VDDA1 KEY1 D1 VLDT_A0 HT LINK VLDT_B0 AE2 F9 VDDA2 KEY2 W18 C744 4.7U/6.3V_6 +1.2V_VLDT D2 AE3 +1.2V_VLDT 0.22U/6.3V_4 C818D C758 0.22U/6.3V_4 +1.2V_VLDT VLDT_A1 VLDT_B1 +1.2V_VLDT 180P/50V_4 C829 CPUCLKP C408 3900P/25V_4 CPUCLKIN CPU_SVC_R D D3 VLDT_A2 VLDT_B2 AE4 A9 CLKIN_H SVC A6 C753 180P/50V_4 +1.2V_VLDT D4 AE5 +1.2V_VLDT CPUCLKN C409 3900P/25V_4 CPUCLKIN# A8 A4 CPU_SVD_R VLDT_A3 VLDT_B3 CLKIN_L SVD HT_NB_CPU_CAD_H0 E3 AD1 HT_CPU_NB_CAD_H0 CPU_LDT_RST# B7 L0_CADIN_H0 L0_CADOUT_H0 10,12 CPU_LDT_RST# RESET_L HT_NB_CPU_CAD_L0 E2 AC1 HT_CPU_NB_CAD_L0 CPU_PWRGD A7 L0_CADIN_L0 L0_CADOUT_L0 12 CPU_PWRGD PWROK HT_NB_CPU_CAD_H1 E1 AC2 HT_CPU_NB_CAD_H1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L# L0_CADIN_H1 L0_CADOUT_H1 10,12 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L HT_NB_CPU_CAD_L1 F1 AC3 HT_CPU_NB_CAD_L1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L# HT_NB_CPU_CAD_H2 L0_CADIN_L1 L0_CADOUT_L1 HT_CPU_NB_CAD_H2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L# G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 MEMHOT_L AA8 HT_NB_CPU_CAD_L2 G2 AA1 HT_CPU_NB_CAD_L2 CPU_SIC AF4 L0_CADIN_L2 L0_CADOUT_L2 5 CPU_SIC SIC HT_NB_CPU_CAD_H3 G1 AA2 HT_CPU_NB_CAD_H3 SideBand Temp sense I2C 5 CPU_SID AF5 HT_NB_CPU_CAD_H[15..0] L0_CADIN_H3 L0_CADOUT_H3 CPU_SID SID HT_NB_CPU_CAD_L3 H1 AA3 HT_CPU_NB_CAD_L3 CPU_ALERT AE6 W7 CPU_THERMDC 8 HT_NB_CPU_CAD_H[15..0] L0_CADIN_L3 L0_CADOUT_L3 5 CPU_ALERT ALERT_L THERMDC HT_NB_CPU_CAD_H4 J1 W2 HT_CPU_NB_CAD_H4 W8 CPU_THERMDA HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CAD_L4 L0_CADIN_H4 L0_CADOUT_H4 HT_CPU_NB_CAD_L4 R128 44.2/F_4 CPU_HTREF0 THERMDA 8 HT_NB_CPU_CAD_L[15..0] K1 L0_CADIN_L4 L0_CADOUT_L4 W3 R6 HT_REF0 HT_NB_CPU_CAD_H5 L3 V1 HT_CPU_NB_CAD_H5 +1.2V_VLDT R135 44.2/F_4 CPU_HTREF1 P6 HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_L5 L0_CADIN_H5 L0_CADOUT_H5 HT_CPU_NB_CAD_L5 place them to CPU within 1.5" HT_REF1 8 HT_NB_CPU_CLK_H[1..0] L2 L0_CADIN_L5 L0_CADOUT_L5 U1 HT_NB_CPU_CAD_H6 L1 U2 HT_CPU_NB_CAD_H6 F6 W9 VDDIO_FB_H HT_NB_CPU_CLK_L[1..0] L0_CADIN_H6 L0_CADOUT_H6 40 CPU_VDD0_RUN_FB_H VDD0_FB_H VDDIO_FB_H VDDIO_FB_H 41 HT_NB_CPU_CAD_L6 M1 U3 HT_CPU_NB_CAD_L6 E6 Y9 VDDIO_FB_L 8 HT_NB_CPU_CLK_L[1..0] L0_CADIN_L6 L0_CADOUT_L6 40 CPU_VDD0_RUN_FB_L VDD0_FB_L VDDIO_FB_L VDDIO_FB_L 41 HT_NB_CPU_CAD_H7 N3 T1 HT_CPU_NB_CAD_H7 HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CAD_L7 L0_CADIN_H7 L0_CADOUT_H7 HT_CPU_NB_CAD_L7 8 HT_NB_CPU_CTL_H[1..0] N2 L0_CADIN_L7 L0_CADOUT_L7 R1 40 CPU_VDD1_RUN_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_RUN_FB_H 40 HT_NB_CPU_CAD_H8 E5 AD4 HT_CPU_NB_CAD_H8 AB6 G6 HT_NB_CPU_CTL_L[1..0] L0_CADIN_H8 L0_CADOUT_H8 40 CPU_VDD1_RUN_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L 40 HT_NB_CPU_CAD_L8 F5 AD3 HT_CPU_NB_CAD_L8 8 HT_NB_CPU_CTL_L[1..0] HT_NB_CPU_CAD_H9 L0_CADIN_L8 L0_CADOUT_L8 HT_CPU_NB_CAD_H9 CPU_DBRDY F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 G10 DBRDY HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_L9 F4 AC5 HT_CPU_NB_CAD_L9 CPU_TMS AA9 E10 CPU_DBREQ# R775 300/F_4 8 HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_H10 L0_CADIN_L9 L0_CADOUT_L9 HT_CPU_NB_CAD_H10 CPU_TCK TMS DBREQ_L G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 AC9 TCK +1.8VSUS HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_L10 H5 AB3 HT_CPU_NB_CAD_L10 CPU_TRST# AD9 AE9 CPU_TDO 8 HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_H11 L0_CADIN_L10 L0_CADOUT_L10 HT_CPU_NB_CAD_H11 CPU_TDI TRST_L TDO H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 AF9 TDI HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_L11 H4 AA5 HT_CPU_NB_CAD_L11 8 HT_CPU_NB_CLK_H[1..0] L0_CADIN_L11 L0_CADOUT_L11 HT_NB_CPU_CAD_H12 K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 HT_CPU_NB_CAD_H12 T7 CPUTEST23 AD7 TEST23 TEST28_H J7 CPUTEST28H T40 SI-2 HT_CPU_NB_CLK_L[1..0] HT_NB_CPU_CAD_L12 HT_CPU_NB_CAD_L12 CPUTEST28L 8 HT_CPU_NB_CLK_L[1..0] K4 L0_CADIN_L12 L0_CADOUT_L12 W5 TEST28_L H8 T43 modified for HT_NB_CPU_CAD_H13 L5 L0_CADIN_H13 L0_CADOUT_H13 V4 HT_CPU_NB_CAD_H13 SI-2 modified for AMD T42 CPUTEST18 H10 TEST18 AMD sightingC HT_CPU_NB_CTL_H[1..0] HT_NB_CPU_CAD_L13 HT_CPU_NB_CAD_L13 CPUTEST19 CPUTEST17 C 8 HT_CPU_NB_CTL_H[1..0] M5 L0_CADIN_L13 L0_CADOUT_L13 V3 sighting update T45 G9 TEST19 TEST17 D7 T48 update HT_NB_CPU_CAD_H14 M3 V5 HT_CPU_NB_CAD_H14 E7 CPUTEST16 HT_CPU_NB_CTL_L[1..0] L0_CADIN_H14 L0_CADOUT_H14 TEST16 T46 HT_NB_CPU_CAD_L14 M4 U5 HT_CPU_NB_CAD_L14 +1.8VSUS R141 510/F_4 CPUTEST25H E9 F7 CPUTEST15 8 HT_CPU_NB_CTL_L[1..0] L0_CADIN_L14 L0_CADOUT_L14 TEST25_H TEST15 T44 HT_NB_CPU_CAD_H15 N5 T4 HT_CPU_NB_CAD_H15 R108 510/F_4 CPUTEST25L E8 C7 CPUTEST14 L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T49 HT_NB_CPU_CAD_L15 P5 T3 HT_CPU_NB_CAD_L15 L0_CADIN_L15 L0_CADOUT_L15 R776 300/F_4 CPUTEST21 AB8 TEST21 TEST7 C3 HT_NB_CPU_CLK_H0 J3 Y1 HT_CPU_NB_CLK_H0 CPUTEST20 AF7 K8 L0_CLKIN_H0 L0_CLKOUT_H0 T116 TEST20 TEST10 HT_NB_CPU_CLK_L0 J2 W1 HT_CPU_NB_CLK_L0 R777 300/F_4 CPUTEST24 AE7 HT_NB_CPU_CLK_H1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_NB_CLK_H1 CPUTEST22 TEST24 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 T118 AE8 TEST22 TEST8 C4 HT_NB_CPU_CLK_L1 K5 Y3 HT_CPU_NB_CLK_L1 +1.8VSUS CPUTEST12 AC8 L0_CLKIN_L1 L0_CLKOUT_L1 T9 TEST12 R455 300_4 CPUTEST27 AF8 HT_NB_CPU_CTL_H0 HT_CPU_NB_CTL_H0 TEST27 CPUTEST29H N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 TEST29_H C9 T47 HT_NB_CPU_CTL_L0 P1 R3 HT_CPU_NB_CTL_L0 R535 0_4 C2 C8 CPUTEST29L L0_CTLIN_L0 L0_CTLOUT_L0 TEST9 TEST29_L T50 HT_NB_CPU_CTL_H1 P3 T5 HT_CPU_NB_CTL_H1 AA6 HT_NB_CPU_CTL_L1 L0_CTLIN_H1 L0_CTLOUT_H1 HT_CPU_NB_CTL_L1 TEST6 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 A3 RSVD1 RSVD10 H18 FOX PZ63826-284R-41F A5 RSVD2 RSVD9 H19 DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7 RSVD3 RSVD8 MLX 47296-4131 B5 RSVD4 RSVD7 D5 C1 RSVD5 RSVD6 C5 DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2) TYC 4-1903401-2 DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN CNTR_VREF C854 0.1U/10V_4 CNTR_VREF 5 +3V Serial VID VFIX MODE VID Override CircuitB R145 *2.2K_4 B SVC SVD Voltage Output +3V R571 20K/F_4 R574 34.8K/F_4 R561 1K/F_4 R562 1K/F_4 +1.8VSUS 0 0 1.4V CNTR_VREF R577 CPU_SVC_R R554 0_4 CPU_SVC 1K/F_4 CPU_SVD_R R553 0_4 CPU_SVD CPU_SVC 40 0 1 1.2V CPU_SVD 40 CPU_PWRGD R147 0_4 CPU_PWRGD_SVID_REG CPU_PWRGD_SVID_REG 40 1 0 1.0V 2 2 R143 Q39 *BSS138_NL/SOT23 0_4 R560 *220_4 CPU_LDT_REQ#_CPU 1 3 CPU_LDT_RST# 1 3 CPU_LDT_RST_HTPA# R559 *220_4 1 1 0.8V CPU_LDT_REQ# 10 Q40 BSS138_NL/SOT23 C926 *0.1U/10V_4 1 R570 0_4 G1 *SHORT_ PAD1 SI-2 remove for power up seq 2 +1.8VSUS R59 10K/F_4 for debug only 2 +1.8VSUS R62 300_4 Q11 CPUTEST20 R798 *300/F_4 MMBT3904 CPUTEST22 R799 *300/F_4 CPU_MEMHOT_L# 3 1 CPU_MEMHOT# CPUTEST12 R800 *300/F_4 CPU_MEMHOT# 7,13 HDT Connector CPUTEST15 CPUTEST14 CPUTEST19 R801 R802 R803 *300/F_4 *300/F_4 *300/F_4 +1.8VSUS CPUTEST18 R804 *300/F_4 1 2 3 4A +1.8VSUS R60 10K/F_4 5 6 SI-2 reserve for AMD recommend A +1.8VSUS R453 10K/F_4 CPU_DBREQ# 7 8 CPU_DBRDY 9 10 +1.8VSUS R454 300_4 CPU_TCK 11 12 2 +1.8VSUS R452 300_4 Q10 CPU_TMS 13 14 2 Q35 MMBT3904 CPU_TDI 15 16 CPU_PROCHOT_L# CPU_THERMTRIP_L# 1 3 CPU_THERMTRIP# 13 CPU_TRST# CPU_TDO 17 18 PROJECT : QT8 Quanta Computer Inc. 1 3 CPU_PROCHOT# 12 19 20 MMBT3904 21 22 C54 *0.1U/10V_4 23 24 CPU_LDT_RST_HTPA# KEY 25 Size Document Number Rev Custom 1A S1G2 HT,CTL I/F 1/3 CN6 *HDT CONN NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 3 of 45 5 4 3 2 1
    • A B C D E PLACE THEM CLOSE TO CPU WITHIN 1" +0.9VSMVTT D10 C10 B10 AD10 U31B VTT1 VTT2 VTT3 MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 W10 AC10 AB10 AA10 +0.9VSMVTT 750 mA +1.8VSUS 6 MEM_MB_DATA[0..63] +0.9VSMVREF 6,41 Processor Memory Interface MEM_MB_DATA0 C11 U31C MEM:DATA G12 MEM_MA_DATA0 MEM_MA_DATA[0..63] 6 04 VTT4 VTT8 R81 R82 Reserved MEM_MB_DATA1 MB_DATA0 MA_DATA0 MEM_MA_DATA1 VTT9 A10 A11 MB_DATA1 MA_DATA1 F12 R459 39.2/F_4 M_ZP AF10 *0_4 MEM_MB_DATA2 A14 H14 MEM_MA_DATA2 39.2/F_4 M_ZN MEMZP MB_DATA2 MA_DATA2 +1.8VSUS R458 AE10 MEMZN VTT_SENSE Y10 CPU_VTT_SENSE CPU_VTT_SENSE 41 2K/F_4 MEM_MB_DATA3 B14 MB_DATA3 MA_DATA3 G14 MEM_MA_DATA3 MEM_MB_DATA4 G11 H11 MEM_MA_DATA4 MEM_MA_RESET# H16 MB_DATA4 MA_DATA4 T41 RSVD_M1 MEMVREF W17 MEMVREF_CPU MEM_MB_DATA5 E11 MB_DATA5 MA_DATA5 H12 MEM_MA_DATA5 MEM_MB_DATA6 D12 C13 MEM_MA_DATA64 MB_DATA6 MA_DATA6 4 6,7 MEM_MA0_ODT0 T19 MA0_ODT0 RSVD_M2 B18 MEM_MB_RESET# T51 MEM_MB_DATA7 A13 MB_DATA7 MA_DATA7 E13 MEM_MA_DATA7 V22 MEM_MB_DATA8 A15 H15 MEM_MA_DATA8 6,7 MEM_MA0_ODT1 MA0_ODT1 MB_DATA8 MA_DATA8 U21 W26 R77 MEM_MB_DATA9 A16 E15 MEM_MA_DATA9 MA1_ODT0 MB0_ODT0 MEM_MB0_ODT0 6,7 MB_DATA9 MA_DATA9 V19 W23 2K/F_4 C197 C177 MEM_MB_DATA10 A19 E17 MEM_MA_DATA10 MA1_ODT1 MB0_ODT1 MEM_MB0_ODT1 6,7 MB_DATA10 MA_DATA10 Y26 0.1U/10V_4 1000P/50V_4 MEM_MB_DATA11 A20 H17 MEM_MA_DATA11 MB1_ODT0 MEM_MB_DATA12 MB_DATA11 MA_DATA11 MEM_MA_DATA12 6,7 MEM_MA0_CS#0 T20 MA0_CS_L0 C14 MB_DATA12 MA_DATA12 E14 U19 V26 MEM_MB_DATA13 D14 F14 MEM_MA_DATA13 6,7 MEM_MA0_CS#1 MA0_CS_L1 MB0_CS_L0 MEM_MB0_CS#0 6,7 MB_DATA13 MA_DATA13 U20 W25 MEM_MB_DATA14 C18 C17 MEM_MA_DATA14 MA1_CS_L0 MB0_CS_L1 MEM_MB0_CS#1 6,7 MB_DATA14 MA_DATA14 V20 U22 MEM_MB_DATA15 D18 G17 MEM_MA_DATA15 MA1_CS_L1 MB1_CS_L0 MEM_MB_DATA16 MB_DATA15 MA_DATA15 MEM_MA_DATA16 D20 MB_DATA16 MA_DATA16 G18 J22 J25 MEM_MB_DATA17 A21 C19 MEM_MA_DATA17 6,7 MEM_MA_CKE0 MA_CKE0 MB_CKE0 MEM_MB_CKE0 6,7 MB_DATA17 MA_DATA17 J20 H26 MEM_MB_DATA18 D24 D22 MEM_MA_DATA18 6,7 MEM_MA_CKE1 MA_CKE1 MB_CKE1 MEM_MB_CKE1 6,7 MB_DATA18 MA_DATA18 MEM_MB_DATA19 C25 E20 MEM_MA_DATA19 MEM_MB_DATA20 MB_DATA19 MA_DATA19 MEM_MA_DATA20 N19 MA_CLK_H5 MB_CLK_H5 P22 B20 MB_DATA20 MA_DATA20 E18 N20 R22 MEM_MB_DATA21 C20 F18 MEM_MA_DATA21 MA_CLK_L5 MB_CLK_L5 MEM_MB_DATA22 MB_DATA21 MA_DATA21 MEM_MA_DATA22 6 MEM_MA_CLK1_P E16 MA_CLK_H1 MB_CLK_H1 A17 MEM_MB_CLK1_P 6 B24 MB_DATA22 MA_DATA22 B22 F16 A18 MEM_MB_DATA23 C24 C23 MEM_MA_DATA23 6 MEM_MA_CLK1_N MA_CLK_L1 MB_CLK_L1 MEM_MB_CLK1_N 6 MB_DATA23 MA_DATA23 Y16 AF18 MEM_MB_DATA24 E23 F20 MEM_MA_DATA24 6 MEM_MA_CLK7_P MA_CLK_H7 MB_CLK_H7 MEM_MB_CLK7_P 6 MB_DATA24 MA_DATA24 AA16 AF17 MEM_MB_DATA25 E24 F22 MEM_MA_DATA25 6 MEM_MA_CLK7_N MA_CLK_L7 MB_CLK_L7 MEM_MB_CLK7_N 6 MB_DATA25 MA_DATA25 P19 R26 MEM_MB_DATA26 G25 H24 MEM_MA_DATA26 MA_CLK_H4 MB_CLK_H4 MEM_MB_DATA27 MB_DATA26 MA_DATA26 MEM_MA_DATA27 P20 MA_CLK_L4 MB_CLK_L4 R25 G26 MB_DATA27 MA_DATA27 J19 MEM_MB_DATA28 C26 E21 MEM_MA_DATA28 6,7 MEM_MA_ADD[0..15] MEM_MB_ADD[0..15] 6,7 MB_DATA28 MA_DATA28 MEM_MA_ADD0 N21 P24 MEM_MB_ADD0 MEM_MB_DATA29 D26 E22 MEM_MA_DATA29 MEM_MA_ADD1 MA_ADD0 MB_ADD0 MEM_MB_ADD1 MEM_MB_DATA30 MB_DATA29 MA_DATA29 MEM_MA_DATA30 M20 MA_ADD1 MB_ADD1 N24 G23 MB_DATA30 MA_DATA30 H20 MEM_MA_ADD2 N22 P26 MEM_MB_ADD2 MEM_MB_DATA31 G24 H22 MEM_MA_DATA31 MEM_MA_ADD3 MA_ADD2 MB_ADD2 MEM_MB_ADD3 MEM_MB_DATA32 MB_DATA31 MA_DATA31 MEM_MA_DATA32 M19 MA_ADD3 MB_ADD3 N23 AA24 MB_DATA32 MA_DATA32 Y24 MEM_MA_ADD4 M22 N26 MEM_MB_ADD4 MEM_MB_DATA33 AA23 AB24 MEM_MA_DATA33 MEM_MA_ADD5 MA_ADD4 MB_ADD4 MEM_MB_ADD5 MEM_MB_DATA34 MB_DATA33 MA_DATA33 MEM_MA_DATA34 L20 MA_ADD5 MB_ADD5 L23 AD24 MB_DATA34 MA_DATA34 AB22 MEM_MA_ADD6 M24 N25 MEM_MB_ADD6 MEM_MB_DATA35 AE24 AA21 MEM_MA_DATA35 MEM_MA_ADD7 MA_ADD6 MB_ADD6 MEM_MB_ADD7 MEM_MB_DATA36 MB_DATA35 MA_DATA35 MEM_MA_DATA363 L21 MA_ADD7 MB_ADD7 L24 AA26 MB_DATA36 MA_DATA36 W22 3 MEM_MA_ADD8 L19 M26 MEM_MB_ADD8 MEM_MB_DATA37 AA25 W21 MEM_MA_DATA37 MEM_MA_ADD9 MA_ADD8 MB_ADD8 MEM_MB_ADD9 MEM_MB_DATA38 MB_DATA37 MA_DATA37 MEM_MA_DATA38 K22 MA_ADD9 MB_ADD9 K26 AD26 MB_DATA38 MA_DATA38 Y22 MEM_MA_ADD10 R21 T26 MEM_MB_ADD10 MEM_MB_DATA39 AE25 AA22 MEM_MA_DATA39 MEM_MA_ADD11 MA_ADD10 MB_ADD10 MEM_MB_ADD11 MEM_MB_DATA40 MB_DATA39 MA_DATA39 MEM_MA_DATA40 L22 MA_ADD11 MB_ADD11 L26 AC22 MB_DATA40 MA_DATA40 Y20 MEM_MA_ADD12 K20 L25 MEM_MB_ADD12 MEM_MB_DATA41 AD22 AA20 MEM_MA_DATA41 MEM_MA_ADD13 MA_ADD12 MB_ADD12 MEM_MB_ADD13 MEM_MB_DATA42 MB_DATA41 MA_DATA41 MEM_MA_DATA42 V24 MA_ADD13 MB_ADD13 W24 AE20 MB_DATA42 MA_DATA42 AA18 MEM_MA_ADD14 K24 J23 MEM_MB_ADD14 MEM_MB_DATA43 AF20 AB18 MEM_MA_DATA43 MEM_MA_ADD15 MA_ADD14 MB_ADD14 MEM_MB_ADD15 MEM_MB_DATA44 MB_DATA43 MA_DATA43 MEM_MA_DATA44 K19 MA_ADD15 MB_ADD15 J24 AF24 MB_DATA44 MA_DATA44 AB21 MEM_MB_DATA45 AF23 AD21 MEM_MA_DATA45 MEM_MB_DATA46 MB_DATA45 MA_DATA45 MEM_MA_DATA46 6,7 MEM_MA_BANK0 R20 MA_BANK0 MB_BANK0 R24 MEM_MB_BANK0 6,7 AC20 MB_DATA46 MA_DATA46 AD19 R23 U26 MEM_MB_DATA47 AD20 Y18 MEM_MA_DATA47 6,7 MEM_MA_BANK1 MA_BANK1 MB_BANK1 MEM_MB_BANK1 6,7 MB_DATA47 MA_DATA47 J21 J26 MEM_MB_DATA48 AD18 AD17 MEM_MA_DATA48 6,7 MEM_MA_BANK2 MA_BANK2 MB_BANK2 MEM_MB_BANK2 6,7 MB_DATA48 MA_DATA48 MEM_MB_DATA49 AE18 W16 MEM_MA_DATA49 MEM_MB_DATA50 MB_DATA49 MA_DATA49 MEM_MA_DATA50 6,7 MEM_MA_RAS# R19 MA_RAS_L MB_RAS_L U25 MEM_MB_RAS# 6,7 AC14 MB_DATA50 MA_DATA50 W14 T22 U24 MEM_MB_DATA51 AD14 Y14 MEM_MA_DATA51 6,7 MEM_MA_CAS# MA_CAS_L MB_CAS_L MEM_MB_CAS# 6,7 MB_DATA51 MA_DATA51 T24 U23 MEM_MB_DATA52 AF19 Y17 MEM_MA_DATA52 6,7 MEM_MA_WE# MA_WE_L MB_WE_L MEM_MB_WE# 6,7 MB_DATA52 MA_DATA52 MEM_MB_DATA53 AC18 AB17 MEM_MA_DATA53 MEM_MB_DATA54 MB_DATA53 MA_DATA53 MEM_MA_DATA54 AF16 MB_DATA54 MA_DATA54 AB15 SOCKET_638_PIN MEM_MB_DATA55 AF15 AD15 MEM_MA_DATA55 MEM_MB_DATA56 MB_DATA55 MA_DATA55 MEM_MA_DATA56 AF13 MB_DATA56 MA_DATA56 AB13 MEM_MB_DATA57 AC12 AD13 MEM_MA_DATA57 MEM_MB_DATA58 MB_DATA57 MA_DATA57 MEM_MA_DATA58 AB11 MB_DATA58 MA_DATA58 Y12 MEM_MB_DATA59 Y11 W11 MEM_MA_DATA59 MEM_MB_DATA60 MB_DATA59 MA_DATA59 MEM_MA_DATA60 AE14 MB_DATA60 MA_DATA60 AB14 MEM_MB_DATA61 AF14 AA14 MEM_MA_DATA61 MEM_MB_DATA62 MB_DATA61 MA_DATA61 MEM_MA_DATA62 AF11 MB_DATA62 MA_DATA62 AB12 MEM_MB_DATA63 AD11 AA12 MEM_MA_DATA63 MB_DATA63 MA_DATA63 6 MEM_MB_DM[0..7] MEM_MA_DM[0..7] 6 MEM_MB_DM0 MEM_MA_DM02 +0.9VSMVTT Place close to socket MEM_MB_DM1 A12 B16 MB_DM0 MA_DM0 E12 C15 MEM_MA_DM1 2 MEM_MB_DM2 MB_DM1 MA_DM1 MEM_MA_DM2 A22 MB_DM2 MA_DM2 E19 MEM_MB_DM3 E25 F24 MEM_MA_DM3 MEM_MB_DM4 MB_DM3 MA_DM3 MEM_MA_DM4 AB26 MB_DM4 MA_DM4 AC24 C112 C399 C99 C398 C213 C369 C364 C201 MEM_MB_DM5 AE22 Y19 MEM_MA_DM5 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 MEM_MB_DM6 MB_DM5 MA_DM5 MEM_MA_DM6 AC16 MB_DM6 MA_DM6 AB16 MEM_MB_DM7 AD12 Y13 MEM_MA_DM7 MB_DM7 MA_DM7 6 MEM_MB_DQS0_P C12 MB_DQS_H0 MA_DQS_H0 G13 MEM_MA_DQS0_P 6 6 MEM_MB_DQS0_N B12 MB_DQS_L0 MA_DQS_L0 H13 MEM_MA_DQS0_N 6 6 MEM_MB_DQS1_P D16 MB_DQS_H1 MA_DQS_H1 G16 MEM_MA_DQS1_P 6 +0.9VSMVTT C16 G15 6 MEM_MB_DQS1_N MB_DQS_L1 MA_DQS_L1 MEM_MA_DQS1_N 6 6 MEM_MB_DQS2_P A24 MB_DQS_H2 MA_DQS_H2 C22 MEM_MA_DQS2_P 6 6 MEM_MB_DQS2_N A23 MB_DQS_L2 MA_DQS_L2 C21 MEM_MA_DQS2_N 6 6 MEM_MB_DQS3_P F26 MB_DQS_H3 MA_DQS_H3 G22 MEM_MA_DQS3_P 6 C401 C202 C400 C185 C183 C189 C390 C396 E26 G21 6 MEM_MB_DQS3_N MB_DQS_L3 MA_DQS_L3 MEM_MA_DQS3_N 6 1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 AC25 AD23 6 MEM_MB_DQS4_P MB_DQS_H4 MA_DQS_H4 MEM_MA_DQS4_P 6 6 MEM_MB_DQS4_N AC26 MB_DQS_L4 MA_DQS_L4 AC23 MEM_MA_DQS4_N 6 6 MEM_MB_DQS5_P AF21 MB_DQS_H5 MA_DQS_H5 AB19 MEM_MA_DQS5_P 6 6 MEM_MB_DQS5_N AF22 MB_DQS_L5 MA_DQS_L5 AB20 MEM_MA_DQS5_N 6 6 MEM_MB_DQS6_P AE16 MB_DQS_H6 MA_DQS_H6 Y15 MEM_MA_DQS6_P 6 6 MEM_MB_DQS6_N AD16 MB_DQS_L6 MA_DQS_L6 W15 MEM_MA_DQS6_N 6 6 MEM_MB_DQS7_P AF12 MB_DQS_H7 MA_DQS_H7 W12 MEM_MA_DQS7_P 6 Close to CPU within 1500 mils 6 MEM_MB_DQS7_N AE12 MB_DQS_L7 MA_DQS_L7 W13 MEM_MA_DQS7_N 6 MEM_MA_CLK7_P MEM_MB_CLK7_P SOCKET_638_PIN C734 C736 1.5P/50V_41 1.5P/50V_4 1 MEM_MA_CLK7_N MEM_MB_CLK7_N MEM_MA_CLK1_P MEM_MB_CLK1_P C367 C366 1.5P/50V_4 1.5P/50V_4 PROJECT : QT8 MEM_MB_CLK1_N MEM_MA_CLK1_N Quanta Computer Inc. Size Document Number Rev Custom 1A S1G2 DDRII MEMORY I/F 2/3 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 4 of 45 A B C D E
    • 5 4 3 2 1 +VCORE0 U31E +VCORE1 AA4 AA11 AA13 AA15 U31F VSS1 VSS2 VSS3 VSS66 VSS67 VSS68 J6 J8 J10 J12 +VCORE0 BOTTOM SIDE DECOUPLING 05 VSS4 VSS69 G4 VDD0_1 VDD1_1 P8 AA17 VSS5 VSS70 J14 H2 VDD0_2 VDD1_2 P10 AA19 VSS6 VSS71 J16 J9 VDD0_3 VDD1_3 R4 AB2 VSS7 VSS72 J18 J11 R7 AB7 K2 C287 C308 C307 C306 C285 C286 C301 VDD0_4 VDD1_4 VSS8 VSS73 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.01U/16V_4 180P/50V_4 J13 VDD0_5 VDD1_5 R9 AB9 VSS9 VSS74 K7D J15 VDD0_6 VDD1_6 R11 AB23 VSS10 VSS75 K9 D K6 VDD0_7 VDD1_7 T2 AB25 VSS11 VSS76 K11 K10 VDD0_8 VDD1_8 T6 AC11 VSS12 VSS77 K13 K12 VDD0_9 VDD1_9 T8 AC13 VSS13 VSS78 K15 K14 T10 AC15 K17 +VCORE1 VDD0_10 VDD1_10 VSS14 VSS79 L4 VDD0_11 VDD1_11 T12 AC17 VSS15 VSS80 L6 L7 VDD0_12 VDD1_12 T14 AC19 VSS16 VSS81 L8 L9 VDD0_13 VDD1_13 U7 AC21 VSS17 VSS82 L10 L11 VDD0_14 VDD1_14 U9 AD6 VSS18 VSS83 L12 L13 U11 AD8 L14 C230 C272 C273 C267 C206 C226 C205 C225 VDD0_15 VDD1_15 VSS19 VSS84 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.01U/16V_4 180P/50V_4 0.01U/16V_4 L15 VDD0_16 VDD1_16 U13 AD25 VSS20 VSS85 L16 M2 VDD0_17 VDD1_17 U15 AE11 VSS21 VSS86 L18 M6 VDD0_18 VDD1_18 V6 AE13 VSS22 VSS87 M7 M8 VDD0_19 VDD1_19 V8 AE15 VSS23 VSS88 M9 M10 VDD0_20 VDD1_20 V10 AE17 VSS24 VSS89 AC6 N7 V12 AE19 M17 +CPUVDDNB +1.8VSUS +CPUVDDNB VDD0_21 VDD1_21 VSS25 VSS90 N9 VDD0_22 VDD1_22 V14 AE21 VSS26 VSS91 N4 N11 VDD0_23 VDD1_23 W4 AE23 VSS27 VSS92 N8 3A VDD1_24 Y2 B4 VSS28 VSS93 N10 K16 VDDNB_1 VDD1_25 AC4 B6 VSS29 VSS94 N16 M16 AD2 +1.8VSUS B8 N18 C264 C231 C279 C248 C284 C309 C247 C214 C315 VDDNB_2 VDD1_26 VSS30 VSS95 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.22U/6.3V_4 180P/50V_4 180P/50V_4 P16 VDDNB_3 B9 VSS31 VSS96 P2 T16 VDDNB_4 VDDIO27 Y25 B11 VSS32 VSS97 P7 +1.8VSUS V16 V25 B13 P9 VDDNB_5 VDDIO26 VSS33 VSS98 2A VDDIO25 V23 B15 VSS34 VSS99 P11 H25 VDDIO1 VDDIO24 V21 B17 VSS35 VSS100 P17 J17 VDDIO2 VDDIO23 V18 B19 VSS36 VSS101 R8 K18 VDDIO3 VDDIO22 U17 B21 VSS37 VSS102 R10 K21 VDDIO4 VDDIO21 T25 B23 VSS38 VSS103 R16 K23 VDDIO5 VDDIO20 T23 B25 VSS39 VSS104 R18C K25 VDDIO6 VDDIO19 T21 D6 VSS40 VSS105 T7 C L17 T18 D8 T9 M18 M21 VDDIO7 VDDIO8 VDDIO18 VDDIO17 R17 P25 D9 D11 VSS41 VSS42 VSS106 VSS107 T11 T13 DECOUPLING BETWEEN PROCESSOR AND DIMMs VDDIO9 VDDIO16 VSS43 VSS108 M23 P23 D13 T15 M25 N17 VDDIO10 VDDIO11 VDDIO15 VDDIO14 P21 P18 D15 D17 VSS44 VSS45 VSS109 VSS110 T17 U4 PLACE CLOSE TO PROCESSOR AS POSSIBLE VDDIO12 VDDIO13 VSS46 VSS111 D19 VSS47 VSS112 U6 D21 U8 +1.8VSUS SOCKET_638_PIN VSS48 VSS113 D23 VSS49 VSS114 U10 D25 VSS50 VSS115 U12 +1.8VSUS E4 U14 VSS51 VSS116 F2 VSS52 VSS117 U16 F11 U18 C750 C802 C236 C749 C803 C240 VSS53 VSS118 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4 3 CNTR_VREF F13 VSS54 VSS119 V2 F15 VSS55 VSS120 V7 R164 R166 R167 F17 V9 390_4 390_4 1K/F_4 VSS56 VSS121 +1.8VSUS F19 VSS57 VSS122 V11 F21 VSS58 VSS123 V13 F23 VSS59 VSS124 V15 2 F25 VSS60 VSS125 V17 Q14 H7 W6 MBCLK2 CPU_SIC VSS61 VSS126 C238 C751 C752 C120 C118 18,35 MBCLK2 3 1 CPU_SIC 3 H9 VSS62 VSS127 Y21 H21 Y23 0.22U/6.3V_4 0.22U/6.3V_4 0.01U/16V_4 0.01U/16V_4 180P/50V_4 VSS63 VSS128 2 *BSS138_NL/SOT23 H23 N6 Q15 VSS64 VSS129 J4 VSS65 18,35 MBDATA2 MBDATA2 3 1 CPU_SID CPU_SID 3 SOCKET_638_PIN 2 *BSS138_NL/SOT23 Q13B B SMBALERT# 3 1 CPU_ALERT CPU_ALERT 3 *BSS138_NL/SOT23 PROCESSOR POWER AND GROUND +3V +3V +VCORE0 +VCORE1 R572 +1.8VSUS EC10 0.01U/16V_4 +3VPCU C69 0.01U/16V_4 200/F_6 Update U36 P/N R170 *0_4 SYS_SHDN# C71 0.01U/16V_4 SYS_SHDN# 38,44 R149 R151 R148 on PV +1.8V EC5 0.01U/16V_4 +3VPCU reserve for C67 0.01U/16V_4 1 10K/F_4 10K/F_4 10K/F_4 power shutdown D34 EC4 0.01U/16V_4 C64 0.01U/16V_4 +1.8V +3V Del R150, R152 C856 ( if can ) *CH500H on PV 0.1U/10V_4 +3VPCU EC7 0.01U/16V_4 +3V 2 U36 +1.8VSUS EC3 0.01U/16V_4 +5V 18,35 MBCLK2 8 1 +5V EC1 *0.01U/16V_4 SCLK VCC H_THRMDA 3 +3V R168 0_4 3920_RST# 3920_RST# 35,44 18,35 MBDATA2 7 2 C855 Q16 EC2 *0.01U/16V_4 +5V EC6 0.01U/16V_4 +3VPCU SDA DXP 2200P/50V_4 3 MMBT3904 D33 6 ALERT# DXN 3 2 2 1 ECPWROK +VGA_CORE EC8 0.01U/16V_4 +1.8V H_THRMDC 3 ECPWROK 16,35 13 PM_THERM# 4 OVERT# GND 5 EC9 0.01U/16V_4 For fix HyperTransport nets 1A MSOP CH501H-40PT A across plane splits SI-2 Modified for H/W thermal shutdown G781P8 SMBALERT# R172 10K/F_4 +3V 3 R805 *10K/F_4 +3VS5 +3VS5 +3V +1.8V PROJECT : QT8 +1.8VSUS R760 *10K/F_4 +1.8VSUS R806 *300_4 PQ60 2 TEMP_FAIL 18 Quanta Computer Inc. 2 Q71 EC13 EC14 EC11 EC12 *MMBT3904 *2N7002E-G ADD VGA TEMP_ FAIL function CPU_THERMTRIP_L# SMBALERT# Size Document Number Rev CPU_THERMTRIP_L# 1 3 M8X is active Hi , M7X acvite Low Custom 1A S1G2 PWR & GND 3/3 1 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 5 of 45 5 4 3 2 1
    • 5 4 3 2 1 07 +1.8VSUS +1.8VSUS 103 104 111 112 117 118 103 104 111 112 117 118 81 82 87 88 95 96 81 82 87 88 95 96 4,7 MEM_MA_ADD[0..15] MEM_MA_DATA[0..63] 4 4,7 MEM_MB_ADD[0..15] MEM_MB_DATA[0..63] 4 CN30 CN31 MEM_MA_ADD0 102 5 MEM_MA_DATA0 MEM_MB_ADD0 102 5 MEM_MB_DATA4 VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 MEM_MA_ADD1 A0 DQ0 MEM_MA_DATA1 MEM_MB_ADD1 A0 DQ0 MEM_MB_DATA5 101 A1 DQ1 7 101 A1 DQ1 7 MEM_MA_ADD2 100 17 MEM_MA_DATA2 MEM_MB_ADD2 100 17 MEM_MB_DATA2 MEM_MA_ADD3 A2 DQ2 MEM_MA_DATA3 MEM_MB_ADD3 A2 DQ2 MEM_MB_DATA3 99 A3 DQ3 19 99 A3 DQ3 19 MEM_MA_ADD4 98 4 MEM_MA_DATA4 MEM_MB_ADD4 98 4 MEM_MB_DATA0 MEM_MA_ADD5 A4 DQ4 MEM_MA_DATA5 MEM_MB_ADD5 A4 DQ4 MEM_MB_DATA1 97 A5 DQ5 6 97 A5 DQ5 6 MEM_MA_ADD6 94 14 MEM_MA_DATA6 MEM_MB_ADD6 94 14 MEM_MB_DATA6 MEM_MA_ADD7 A6 DQ6 MEM_MA_DATA7 MEM_MB_ADD7 A6 DQ6 MEM_MB_DATA7 92 A7 DQ7 16 92 A7 DQ7 16 MEM_MA_ADD8 93 23 MEM_MA_DATA8 MEM_MB_ADD8 93 23 MEM_MB_DATA13D MEM_MA_ADD9 A8 DQ8 MEM_MA_DATA9 MEM_MB_ADD9 A8 DQ8 MEM_MB_DATA12 D 91 A9 DQ9 25 91 A9 DQ9 25 MEM_MA_ADD10 105 35 MEM_MA_DATA10 MEM_MB_ADD10 105 35 MEM_MB_DATA11 MEM_MA_ADD11 A10 DQ10 MEM_MA_DATA11 MEM_MB_ADD11 A10 DQ10 MEM_MB_DATA10 90 A11 DQ11 37 90 A11 DQ11 37 MEM_MA_ADD12 89 20 MEM_MA_DATA12 MEM_MB_ADD12 89 20 MEM_MB_DATA8 MEM_MA_ADD13 A12 DQ12 MEM_MA_DATA13 MEM_MB_ADD13 A12 DQ12 MEM_MB_DATA9 116 A13 DQ13 22 116 A13 DQ13 22 MEM_MA_ADD14 86 36 MEM_MA_DATA14 MEM_MB_ADD14 86 36 MEM_MB_DATA14 MEM_MA_ADD15 A14 DQ14 MEM_MA_DATA15 MEM_MB_ADD15 A14 DQ14 MEM_MB_DATA15 4,7 MEM_MA_BANK[0..2] 84 A15 DQ15 38 4,7 MEM_MB_BANK[0..2] 84 A15 DQ15 38 43 MEM_MA_DATA16 43 MEM_MB_DATA16 MEM_MA_BANK0 107 DQ16 MEM_MA_DATA17 MEM_MB_BANK0 107 DQ16 MEM_MB_DATA17 BA0 DQ17 45 BA0 DQ17 45 MEM_MA_BANK1 106 55 MEM_MA_DATA18 MEM_MB_BANK1 106 55 MEM_MB_DATA18 MEM_MA_BANK2 85 BA1 DQ18 MEM_MA_DATA19 MEM_MB_BANK2 BA1 DQ18 MEM_MB_DATA19 4 MEM_MA_DM[0..7] BA2 DQ19 57 4 MEM_MB_DM[0..7] 85 BA2 DQ19 57 44 MEM_MA_DATA20 44 MEM_MB_DATA20 MEM_MA_DM0 DQ20 MEM_MA_DATA21 MEM_MB_DM0 DQ20 MEM_MB_DATA21 10 DM0 DQ21 46 10 DM0 DQ21 46 MEM_MA_DM1 26 56 MEM_MA_DATA22 MEM_MB_DM1 26 56 MEM_MB_DATA22 MEM_MA_DM2 DM1 DQ22 MEM_MA_DATA23 MEM_MB_DM2 DM1 DQ22 MEM_MB_DATA23 52 DM2 DQ23 58 52 DM2 DQ23 58 MEM_MA_DM3 67 61 MEM_MA_DATA24 MEM_MB_DM3 67 61 MEM_MB_DATA24 MEM_MA_DM4 DM3 DQ24 MEM_MA_DATA25 MEM_MB_DM4 DM3 DQ24 MEM_MB_DATA25 130 DM4 DQ25 63 130 DM4 DQ25 63 MEM_MA_DM5 147 73 MEM_MA_DATA26 MEM_MB_DM5 147 73 MEM_MB_DATA26 MEM_MA_DM6 DM5 DQ26 MEM_MA_DATA27 MEM_MB_DM6 DM5 DQ26 MEM_MB_DATA27 170 DM6 DQ27 75 170 DM6 DQ27 75 MEM_MA_DM7 185 62 MEM_MA_DATA28 MEM_MB_DM7 185 62 MEM_MB_DATA28 DM7 DQ28 MEM_MA_DATA29 DM7 DQ28 MEM_MB_DATA29 DQ29 64 DQ29 64 13 74 MEM_MA_DATA30 13 74 MEM_MB_DATA30 4 MEM_MA_DQS0_P DQS0 DQ30 4 MEM_MB_DQS0_P DQS0 DQ30 31 76 MEM_MA_DATA31 31 76 MEM_MB_DATA31 4 MEM_MA_DQS1_P DQS1 DQ31 4 MEM_MB_DQS1_P DQS1 DQ31 51 123 MEM_MA_DATA36 51 123 MEM_MB_DATA37 4 MEM_MA_DQS2_P DQS2 DQ32 4 MEM_MB_DQS2_P DQS2 DQ32 70 125 MEM_MA_DATA37 70 125 MEM_MB_DATA36 4 MEM_MA_DQS3_P DQS3 DQ33 4 MEM_MB_DQS3_P DQS3 DQ33 131 135 MEM_MA_DATA35 131 135 MEM_MB_DATA34 4 MEM_MA_DQS4_P DQS4 DQ34 4 MEM_MB_DQS4_P DQS4 DQ34 148 137 MEM_MA_DATA39 148 137 MEM_MB_DATA35 4 MEM_MA_DQS5_P DQS5 DQ35 4 MEM_MB_DQS5_P DQS5 DQ35 169 124 MEM_MA_DATA38 169 124 MEM_MB_DATA33 4 MEM_MA_DQS6_P DQS6 DQ36 4 MEM_MB_DQS6_P DQS6 DQ36 188 126 MEM_MA_DATA32 188 126 MEM_MB_DATA32 4 MEM_MA_DQS7_P DQS7 DQ37 4 MEM_MB_DQS7_P DQS7 DQ37 134 MEM_MA_DATA33 134 MEM_MB_DATA38C DQ38 MEM_MA_DATA34 DQ38 MEM_MB_DATA39 C 4 MEM_MA_DQS0_N 11 DQS0 DQ39 136 4 MEM_MB_DQS0_N 11 DQS0 DQ39 136 29 141 MEM_MA_DATA40 29 141 MEM_MB_DATA40 4 MEM_MA_DQS1_N DQS1 DQ40 4 MEM_MB_DQS1_N DQS1 DQ40 49 143 MEM_MA_DATA41 49 143 MEM_MB_DATA45 4 MEM_MA_DQS2_N DQS2 DQ41 4 MEM_MB_DQS2_N DQS2 DQ41 68 151 MEM_MA_DATA46 68 151 MEM_MB_DATA47 4 MEM_MA_DQS3_N DQS3 DQ42 4 MEM_MB_DQS3_N DQS3 DQ42 129 153 MEM_MA_DATA47 129 153 MEM_MB_DATA46 4 MEM_MA_DQS4_N DQS4 DQ43 4 MEM_MB_DQS4_N DQS4 DQ43 146 140 MEM_MA_DATA44 146 140 MEM_MB_DATA44 4 MEM_MA_DQS5_N DQS5 DQ44 4 MEM_MB_DQS5_N DQS5 DQ44 167 142 MEM_MA_DATA45 167 142 MEM_MB_DATA41 4 MEM_MA_DQS6_N DQS6 DQ45 4 MEM_MB_DQS6_N DQS6 DQ45 186 152 MEM_MA_DATA42 186 152 MEM_MB_DATA43 4 MEM_MA_DQS7_N DQS7 DQ46 4 MEM_MB_DQS7_N DQS7 DQ46 154 MEM_MA_DATA43 154 MEM_MB_DATA42 DQ47 MEM_MA_DATA52 DQ47 MEM_MB_DATA52 DQ48 157 DQ48 157 30 159 MEM_MA_DATA49 30 159 MEM_MB_DATA53 4 MEM_MA_CLK1_P CK0 DQ49 4 MEM_MB_CLK1_P CK0 DQ49 32 173 MEM_MA_DATA54 32 173 MEM_MB_DATA50 4 MEM_MA_CLK1_N CK0 DQ50 4 MEM_MB_CLK1_N CK0 DQ50 164 175 MEM_MA_DATA55 164 175 MEM_MB_DATA51 4 MEM_MA_CLK7_P CK1 DQ51 4 MEM_MB_CLK7_P CK1 DQ51 166 158 MEM_MA_DATA53 166 158 MEM_MB_DATA48 4 MEM_MA_CLK7_N CK1 DQ52 4 MEM_MB_CLK7_N CK1 DQ52 160 MEM_MA_DATA48 160 MEM_MB_DATA49 DQ53 MEM_MA_DATA51 DQ53 MEM_MB_DATA54 4,7 MEM_MA_CKE0 79 CKE0 DQ54 174 4,7 MEM_MB_CKE0 79 CKE0 DQ54 174 80 176 MEM_MA_DATA50 4,7 MEM_MB_CKE1 80 176 MEM_MB_DATA55 4,7 MEM_MA_CKE1 CKE1 DQ55 CKE1 DQ55 179 MEM_MA_DATA61 179 MEM_MB_DATA56 DQ56 MEM_MA_DATA60 DQ56 MEM_MB_DATA60 4,7 MEM_MA_RAS# 108 RAS DQ57 181 4,7 MEM_MB_RAS# 108 RAS DQ57 181 113 189 MEM_MA_DATA63 113 189 MEM_MB_DATA58 4,7 MEM_MA_CAS# CAS DQ58 4,7 MEM_MB_CAS# CAS DQ58 109 191 MEM_MA_DATA62 109 191 MEM_MB_DATA59 4,7 MEM_MA_WE# WE DQ59 4,7 MEM_MB_WE# WE DQ59 MEM_MA_DATA56 MEM_MB_DATA61 SO-DIMM 4,7 MEM_MA0_CS#0 110 S0 DQ60 180 4,7 MEM_MB0_CS#0 110 S0 DQ60 180 115 182 MEM_MA_DATA57 115 182 MEM_MB_DATA57 4,7 MEM_MA0_CS#1 S1 DQ61 4,7 MEM_MB0_CS#1 S1 DQ61 (Normal) 192 MEM_MA_DATA58 192 MEM_MB_DATA62 DQ62 DQ62 (REVERSE) 114 194 MEM_MA_DATA59 114 194 MEM_MB_DATA63 4,7 MEM_MA0_ODT0 ODT0 DQ63 4,7 MEM_MB0_ODT0 ODT0 DQ63 4,7 MEM_MA0_ODT1 119 ODT1 4,7 MEM_MB0_ODT1 119 ODT1 50 MEMHOT_SODIMM#_1 R106 0_4 50 MEMHOT_SODIMM#_2 R105 0_4 MEMHOT_SODIMM# NC1 MEMHOT_SODIMM# 7 NC1 SO-DIMM DIM1_SA0 198 69 MEM_MA_RESET#1 DIM2_SA0 198 69 MEM_MB_RESET#2 SA0 NC2 T155 SA0 NC2 T156 DIM1_SA1 200 83 DIM2_SA1 200 83 SA1 NC3 SA1 NC3 NC4 120 NC4 120B PDAT_SMB 195 163 MEM_MA_NC5 PDAT_SMB 195 163 MEM_MB_NC5 B 2,7,13,28,36 PDAT_SMB SDA NC/TEST T115 SDA NC/TEST T114 PCLK_SMB 197 PCLK_SMB 197 2,7,13,28,36 PCLK_SMB SCL SCL +3V 199 VDDspd +3V 199 VDDspd C701 C702+0.9VSMVREF_DIMM 0.1U/10V_4 1 196 +0.9VSMVREF_DIMM 0.1U/10V_4 1 196 VREF VSS56 VREF VSS56 VSS55 193 VSS55 193 2 VSS0 VSS54 190 2 VSS0 VSS54 190 3 187 C848 C406 C397 o3 187 C849 VSS1 VSS53 1000P/50V_4 VSS1 VSS53 8 VSS2 VSS52 184 2.2U/6.3V_6 0.1U/10V_4 8 VSS2 VSS52 184 C391 1000P/50V_4 o 9 VSS3 VSS51 183 9 VSS3 VSS51 183 C370 0.1U/10V_4 12 178 12 178 VSS4 VSS50 VSS4 VSS50 2.2U/6.3V_6 15 VSS5 VSS49 177 15 VSS5 VSS49 177 18 VSS6 VSS48 172 18 VSS6 VSS48 172 21 171 +1.8VSUS 21 171 VSS7 VSS47 VSS7 VSS47 24 VSS8 VSS46 168 24 VSS8 VSS46 168 27 VSS9 VSS45 165 27 VSS9 VSS45 165 28 VSS10 VSS44 162 28 VSS10 VSS44 162 33 161 R138 33 161 VSS11 VSS43 VSS11 VSS43 34 VSS12 VSS42 156 2K/F_4 34 VSS12 VSS42 156 39 155 +0.9VSMVREF_DIMM 39 155 VSS13 VSS41 VSS13 VSS41 40 VSS14 VSS40 150 40 VSS14 VSS40 150 41 VSS15 VSS39 149 41 VSS15 VSS39 149 42 VSS16 VSS38 145 42 VSS16 VSS38 145 47 VSS17 VSS37 144 47 VSS17 VSS37 144 48 139 R139 *0_4 +0.9VSMVREF_DIMM 48 139 4,41 +0.9VSMVREF VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS18 VSS36 VSS18 VSS36 53 138 53 138 GND GND GND GND VSS19 VSS35 VSS19 VSS35 54 VSS20 VSS34 133 54 VSS20 VSS34 133 DDR SO-DIMM SOCKET 1.8V 201 202 59 60 65 66 71 72 77 78 121 122 127 128 132 201 202 59 60 65 66 71 72 77 78 121 122 127 128 132A Only for reserved R130 2K/F_4 H=9.2 A DDR SO-DIMM SOCKET 1.8V H=5.2 DIM2_SA0 DIM2_SA1 R423 R424 10K/F_4 10K/F_4 +3V PROJECT : QT8 R40 R43 10K/F_4 10K/F_4 DIM1_SA0 DIM1_SA1 Quanta Computer Inc. SMbus address A2 SMbus address A0 Size Document Number Rev Custom 1A DDR2 SODIMMS: A/B CHANNEL NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 6 of 45 5 4 3 2 1
    • 5 4 3 2 1 4,6 MEM_MA_ADD[0..15] 4,6 MEM_MA_BANK[0..2] MEM_MA_ADD[0..15] MEM_MA_BANK[0..2] 4,6 MEM_MB_ADD[0..15] 4,6 MEM_MB_BANK[0..2] MEM_MB_ADD[0..15] MEM_MB_BANK[0..2] 08 +0.9VSMVTT +0.9VSMVTT MEM_MA_CKE0 RP40 4 3 47_4P2R_4 MEM_MB_CKE0 RP36 4 3 47_4P2R_4 4,6 MEM_MA_CKE0 4,6 MEM_MB_CKE0 MEM_MA_BANK2 2 1 C176 0.1U/10V_4 +1.8VSUS MEM_MB_BANK2 2 1 C193 0.1U/10V_4 +1.8VSUS MEM_MA_ADD12 RP35 4 3 47_4P2R_4 MEM_MB_ADD12 RP32 2 1 47_4P2R_4D D MEM_MA_ADD9 2 1 C256 0.1U/10V_4 MEM_MB_ADD9 4 3 C245 0.1U/10V_4 MEM_MA_ADD8 RP28 2 1 47_4P2R_4 MEM_MB_ADD8 RP27 4 3 47_4P2R_4 MEM_MA_ADD5 4 3 C223 0.1U/10V_4 +1.8VSUS MEM_MB_ADD5 2 1 C154 0.1U/10V_4 +1.8VSUS MEM_MA_ADD3 RP26 2 1 47_4P2R_4 MEM_MB_ADD3 RP25 4 3 47_4P2R_4 MEM_MA_ADD1 4 3 C104 0.1U/10V_4 MEM_MB_ADD1 2 1 C100 0.1U/10V_4 MEM_MA_ADD10 RP20 4 3 47_4P2R_4 MEM_MB_ADD10 RP18 4 3 47_4P2R_4 MEM_MA_BANK0 2 1 C217 0.1U/10V_4 +1.8VSUS MEM_MB_BANK0 2 1 C137 0.1U/10V_4 +1.8VSUS MEM_MA_WE# RP16 4 3 47_4P2R_4 MEM_MB_WE# RP15 4 3 47_4P2R_4 4,6 MEM_MA_WE# 4,6 MEM_MB_WE# MEM_MA_CAS# 2 1 C96 0.1U/10V_4 MEM_MB_CAS# 2 1 C94 0.1U/10V_4 4,6 MEM_MA_CAS# 4,6 MEM_MB_CAS# MEM_MA0_ODT1 RP10 4 3 47_4P2R_4 MEM_MB0_ODT1 RP9 4 3 47_4P2R_4 4,6 MEM_MA0_ODT1 4,6 MEM_MB0_ODT1 MEM_MA0_CS#1 2 1 C152 0.1U/10V_4 +1.8VSUS MEM_MB0_CS#1 2 1 C190 0.1U/10V_4 +1.8VSUS 4,6 MEM_MA0_CS#1 4,6 MEM_MB0_CS#1 MEM_MA_ADD15 RP39 4 3 47_4P2R_4 MEM_MB_CKE1 RP38 2 1 47_4P2R_4 4,6 MEM_MB_CKE1 MEM_MA_CKE1 2 1 C271 0.1U/10V_4 MEM_MB_ADD15 4 3 C93 0.1U/10V_4 4,6 MEM_MA_CKE1 MEM_MA_ADD7 RP33 4 3 47_4P2R_4 MEM_MB_ADD7 RP34 4 3 47_4P2R_4 C160 0.1U/10V_4 +1.8VSUS MEM_MA_ADD14 2 1 C162 0.1U/10V_4 +1.8VSUS MEM_MB_ADD14 2 1 MEM_MA_ADD6 RP29 4 3 47_4P2R_4 C254 0.1U/10V_4 MEM_MA_ADD11 2 1 C101 0.1U/10V_4 MEM_MB_ADD6 RP30 4 3 47_4P2R_4 MEM_MB_ADD11 2 1 C173 0.1U/10V_4 +1.8VSUS C208 0.1U/10V_4 +1.8VSUS MEM_MA_ADD2 RP24 4 3 47_4P2R_4 MEM_MB_ADD2 RP22 4 3 47_4P2R_4 C255 0.1U/10V_4 MEM_MA_ADD4 2 1 C102 0.1U/10V_4 MEM_MB_ADD4 2 1 C126 0.1U/10V_4 +1.8VSUS MEM_MA_BANK1 RP21 2 1 47_4P2R_4 MEM_MB_BANK1 RP19 4 3 47_4P2R_4 MEM_MA_ADD0 4 3 C107 0.1U/10V_4 +1.8VSUS MEM_MB_ADD0 2 1 C253 0.1U/10V_4 4,6 MEM_MA0_CS#0 MEM_MA0_CS#0 RP14 4 3 47_4P2R_4 C270 0.1U/10V_4 4,6 MEM_MB0_CS#0 MEM_MB0_CS#0 RP13 4 3 47_4P2R_4 4,6 MEM_MA_RAS# MEM_MA_RAS# 2 1 4,6 MEM_MB_RAS# MEM_MB_RAS# 2 1 C178 0.1U/10V_4 +1.8VSUS C146 0.1U/10V_4 +1.8VSUSC MEM_MA_ADD13 RP12 4 3 47_4P2R_4 MEM_MB0_ODT0 RP11 2 1 47_4P2R_4 C105 0.1U/10V_4 C 4,6 MEM_MB0_ODT0 MEM_MA0_ODT0 2 1 C269 0.1U/10V_4 MEM_MB_ADD13 4 3 4,6 MEM_MA0_ODT0 PLACE CLOSE TO PROCESSOR PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH WITHIN 1.5 INCH +1.8VSUS +1.8VSUS C239 C121 C241 C242 C117 C235 C122 C119 C237 C115 C116 C745 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 PLACE CLOSE TO SOCKET( PER EMI/EMC) PLACE CLOSE TO SOCKET( PER EMI/EMC)B B +3VS5 SI-2 modified --SB internal pull HI to 3vs5 +3V R417 *10K/F_4 R421 CPU_MEMHOT# 3,13 *10K/F_4 3 Close DDR2 socket +3V U25 R416 *33_4 2 3 7 8 C706 0.1U/10V_4 Q32 A0 +VS *2N7002E-G +3V 6 A1 5 1 A2 MEMHOT_SODIMM# O.S 3 2 PDAT_SMB 1 Q33 2,6,13,28,36 PDAT_SMB SDA PCLK_SMB 2 4 *2N7002E-G 2,6,13,28,36 PCLK_SMB SCL GND 1 *DS75U+T&R Address:92hA R422 10K/F_4 MEMHOT_SODIMM# A +3V MEMHOT_SODIMM# 6 PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev Custom 1A DDR2 SODIMMS TERMINATIONS NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 7 of 45 5 4 3 2 1
    • 5 4 3 2 1 U32A HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H2 HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H3 Y25 Y24 V22 V23 V25 V24 U24 HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N PART 1 OF 6 HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N D24 D25 E24 E25 F24 F25 F23 HT_NB_CPU_CAD_H0 HT_NB_CPU_CAD_L0 HT_NB_CPU_CAD_H1 HT_NB_CPU_CAD_L1 HT_NB_CPU_CAD_H2 HT_NB_CPU_CAD_L2 HT_NB_CPU_CAD_H3 HT_CPU_NB_CAD_H[15..0] HT_CPU_NB_CAD_L[15..0] HT_CPU_NB_CLK_H[1..0] HT_CPU_NB_CAD_H[15..0] HT_CPU_NB_CAD_L[15..0] HT_CPU_NB_CLK_H[1..0] 3 3 3 08 HT_CPU_NB_CAD_L3 HT_RXCAD3P HT_TXCAD3P HT_NB_CPU_CAD_L3 HT_CPU_NB_CLK_L[1..0] U25 HT_RXCAD3N HT_TXCAD3N F22 HT_CPU_NB_CLK_L[1..0] 3 HT_CPU_NB_CAD_H4 T25 H23 HT_NB_CPU_CAD_H4 HT_CPU_NB_CAD_L4 HT_RXCAD4P HT_TXCAD4P HT_NB_CPU_CAD_L4 HT_CPU_NB_CTL_H[1..0] T24 HT_RXCAD4N HT_TXCAD4N H22 HT_CPU_NB_CTL_H[1..0] 3 HYPER TRANSPORT CPU I/F HT_CPU_NB_CAD_H5 P22 J25 HT_NB_CPU_CAD_H5 HT_CPU_NB_CAD_L5 HT_RXCAD5P HT_TXCAD5P HT_NB_CPU_CAD_L5 HT_CPU_NB_CTL_L[1..0] P23 HT_RXCAD5N HT_TXCAD5N J24 HT_CPU_NB_CTL_L[1..0] 3 HT_CPU_NB_CAD_H6 P25 K24 HT_NB_CPU_CAD_H6D HT_CPU_NB_CAD_L6 HT_RXCAD6P HT_TXCAD6P HT_NB_CPU_CAD_L6 HT_NB_CPU_CAD_H[15..0] D P24 HT_RXCAD6N HT_TXCAD6N K25 HT_NB_CPU_CAD_H[15..0] 3 HT_CPU_NB_CAD_H7 N24 K23 HT_NB_CPU_CAD_H7 HT_CPU_NB_CAD_L7 HT_RXCAD7P HT_TXCAD7P HT_NB_CPU_CAD_L7 HT_NB_CPU_CAD_L[15..0] N25 HT_RXCAD7N HT_TXCAD7N K22 HT_NB_CPU_CAD_L[15..0] 3 HT_CPU_NB_CAD_H8 AC24 F21 HT_NB_CPU_CAD_H8 HT_NB_CPU_CLK_H[1..0] HT_CPU_NB_CAD_L8 HT_RXCAD8P HT_TXCAD8P HT_NB_CPU_CAD_L8 HT_NB_CPU_CLK_H[1..0] 3 AC25 HT_RXCAD8N HT_TXCAD8N G21 HT_CPU_NB_CAD_H9 AB25 G20 HT_NB_CPU_CAD_H9 HT_NB_CPU_CLK_L[1..0] HT_CPU_NB_CAD_L9 HT_RXCAD9P HT_TXCAD9P HT_NB_CPU_CAD_L9 HT_NB_CPU_CLK_L[1..0] 3 AB24 HT_RXCAD9N HT_TXCAD9N H21 HT_CPU_NB_CAD_H10 AA24 J20 HT_NB_CPU_CAD_H10 HT_NB_CPU_CTL_H[1..0] HT_CPU_NB_CAD_L10 HT_RXCAD10P HT_TXCAD10P HT_NB_CPU_CAD_L10 HT_NB_CPU_CTL_H[1..0] 3 AA25 HT_RXCAD10N HT_TXCAD10N J21 HT_CPU_NB_CAD_H11 Y22 J18 HT_NB_CPU_CAD_H11 HT_NB_CPU_CTL_L[1..0] HT_CPU_NB_CAD_L11 HT_RXCAD11P HT_TXCAD11P HT_NB_CPU_CAD_L11 HT_NB_CPU_CTL_L[1..0] 3 Y23 HT_RXCAD11N HT_TXCAD11N K17 HT_CPU_NB_CAD_H12 W21 L19 HT_NB_CPU_CAD_H12 HT_CPU_NB_CAD_L12 HT_RXCAD12P HT_TXCAD12P HT_NB_CPU_CAD_L12 W20 HT_RXCAD12N HT_TXCAD12N J19 HT_CPU_NB_CAD_H13 V21 M19 HT_NB_CPU_CAD_H13 HT_CPU_NB_CAD_L13 HT_RXCAD13P HT_TXCAD13P HT_NB_CPU_CAD_L13 V20 HT_RXCAD13N HT_TXCAD13N L18 HT_CPU_NB_CAD_H14 U20 HT_RXCAD14P HT_TXCAD14P M21 HT_NB_CPU_CAD_H14 signals RS780 RX780 HT_CPU_NB_CAD_L14 U21 P21 HT_NB_CPU_CAD_L14 HT_CPU_NB_CAD_H15 HT_RXCAD14N HT_TXCAD14N HT_NB_CPU_CAD_H15 U19 HT_RXCAD15P HT_TXCAD15P P18 HT_CPU_NB_CAD_L15 U18 HT_RXCAD15N HT_TXCAD15N M18 HT_NB_CPU_CAD_L15 HT_TXCALP RES CHIP 1.21K 1/16W +-1%(0402) R641 R641 P/N : CS21212FB18 HT_CPU_NB_CLK_H0 T22 HT_RXCLK0P HT_TXCLK0P H24 HT_NB_CPU_CLK_H0 SI-2 modified 301 ohm 1% 1.21k ohm 1% HT_CPU_NB_CLK_L0 T23 HT_RXCLK0N HT_TXCLK0N H25 HT_NB_CPU_CLK_L0 -- follow AMD HT_TXCALN HT_CPU_NB_CLK_H1 AB23 L21 HT_NB_CPU_CLK_H1 HT_CPU_NB_CLK_L1 HT_RXCLK1P HT_TXCLK1P HT_NB_CPU_CLK_L1 check list to AA22 HT_RXCLK1N HT_TXCLK1N L20 change part HT_RXCALP RES CHIP 301 1/16W +-1%(0402) SI-2 modified HT_CPU_NB_CTL_H0 M22 HT_RXCTL0P HT_TXCTL0P M24 HT_NB_CPU_CTL_H0 number 300 ohm R655 R655 P/N : CS13012FB14 -- follow AMD HT_CPU_NB_CTL_L0 M23 M25 HT_NB_CPU_CTL_L0 to 301 ohm 301 ohm 1% 1.21k ohm 1% HT_RXCTL0N HT_TXCTL0N check list to HT_CPU_NB_CTL_H1 R21 HT_RXCTL1P HT_TXCTL1P P19 HT_NB_CPU_CTL_H1 HT_RXCALNC HT_CPU_NB_CTL_L1 R20 R18 HT_NB_CPU_CTL_L1 C change part HT_RXCTL1N HT_TXCTL1N R655 R641 number 300 ohm R533 301/F_4 HT_RXCALP C23 HT_RXCALP HT_TXCALP B24 HT_TXCALP R534 301/F_4 to 301 ohm HT_RXCALN A24 B25 HT_TXCALN HT_RXCALN HT_TXCALN RS780(RX780) U27 SPM_BA0 L2 BA0 DQ15 B9 SPM_DQ15 This block is for UMA RS780 only , RX780 can SPM_BA1 L3 B1 SPM_DQ14 SPM_A12 BA1 DQ14 DQ13 D9 SPM_DQ9 SPM_DQ12 remove all component R2 A12 DQ12 D1 SPM_A11 P7 D3 SPM_DQ8 SPM_A10 A11 DQ11 SPM_DQ10 M2 A10/AP DQ10 D7 SPM_A9 P3 C2 SPM_DQ13 +1.8V SPM_A8 A9 DQ9 SPM_DQ11 P8 A8 DQ8 C8 SPM_A7 SPM_DQ5 +1.8V_MEM_VDDQ SPM_A6 P2 A7 DQ7 F9 SPM_DQ3 U32D 40mils wdith or more N7 A6 DQ6 F1 SPM_A5 N3 H9 SPM_DQ4 PAR 4 OF 6 R487 *0_6 SPM_A4 A5 DQ5 SPM_DQ1 SPM_A0 SPM_DQ0 N8 A4 DQ4 H1 AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18 SPM_A3 N2 H3 SPM_DQ0 SPM_A1 AE16 AA20 SPM_DQ1 SPM_A2 A3 DQ3 SPM_DQ7 SPM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) SPM_DQ2 C70 C738 C76 M7 A2 DQ2 H7 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19 SPM_A1 M3 G2 SPM_DQ2 SPM_A3 AE15 Y19 SPM_DQ3 *1U/10V_4 *10U/6.3V_8 *10U/6.3V_8 SPM_A0 A1 DQ1 SPM_DQ6 SPM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) SPM_DQ4 M8 A0 DQ0 G8 AA12 MEM_A4(NC) MEM_DQ4(NC) V17 SPM_A5 AB16 AA17 SPM_DQ5 SPM_A6 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) SPM_DQ6 AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15 SPM_CLKN K8 A9 +1.8V_MEM_VDDQ SPM_A7 AD14 Y15 SPM_DQ7 R56 *100_4 SPM_CLKP CK VDDQ1 SPM_A8 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) SPM_DQ8B J8 CK VDDQ2 C1 AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20 B C3 SPM_A9 AD15 AD19 SPM_DQ9 SBD_MEM/DVO_I/F Within 200mils SPM_CKE VDDQ3 SPM_A10 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) SPM_DQ10 K2 CKE VDDQ4 C7 AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22 C9 SPM_A11 AE13 AC18 SPM_DQ11 C87 C77 C74 VDDQ5 T24 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) E9 SPM_A12 AC14 AB20 SPM_DQ12 *0.1U/10V_4 *0.1U/10V_4 *1U/10V_4 VDDQ6 SPM_A13 MEM_A12(NC) MEM_DQ12(NC) SPM_DQ13 VDDQ7 G1 Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22 SPM_CS# L8 G3 AC22 SPM_DQ14 CS VDDQ8 SPM_BA0 MEM_DQ14/DVO_D10(NC) SPM_DQ15 VDDQ9 G7 AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21 SPM_WE# K3 G9 SPM_BA1 AE17 WE VDDQ10 SPM_BA2 MEM_BA1(NC) SPM_DQS0P AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17 SPM_RAS# K7 A1 W18 SPM_DQS0N RAS VDD1 L76 SPM_RAS# MEM_DQS0N/DVO_IDCKN(NC) SPM_DQS1P VDD2 E1 W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20 SPM_CAS# L7 CAS VDD3 J9 SPM_CAS# Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21 SPM_DQS1N IOPLLVDD18 - memory PLL M9 SPM_WE# AD18 not applicable to RX780 SPM_DM0 VDD4 *BLM18PG181SN1D(180,1.5A)_6 SPM_CS# MEM_WEb(NC) SPM_DM0 F3 LDM VDD5 R1 AB13 MEM_CSb(NC) MEM_DM0(NC) W17 SPM_DM1 B3 SPM_CKE AB18 AE19 SPM_DM1 UDM MEM_VDDQ_VDDL SPM_ODT MEM_CKE(NC) MEM_DM1/DVO_D8(NC) VDDL J1 V14 MEM_ODT(NC) J7 AE23 +1.8_IOPLLVDD18_NB Del L77, L78 SPM_ODT VSSDL SPM_CLKP IOPLLVDD18(NC) +1.1V_IOPLLVDD K9 ODT V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 SPM_CLKN W14 MEM_CKN(NC) for TP on PV +1.8V_MEM_VDDQ C757 AD23 C762 C763 IOPLLVSS(NC) SPM_DQS0P F7 LDQS *1U/10V_4 R502 *40.2/F_4 SPM_COMPP AE12 MEM_COMPP(NC) *2.2U/6.3V_6 IOPLLVDD- memory PLL SPM_DQS0N E8 A7 R501 *40.2/F_4 SPM_COMPN AD12 AE18 SPM_VREF1 *2.2U/6.3V_6 not applicable to RX780 LDQS VSSQ1 MEM_COMPN(NC) MEM_VREF(NC) VSSQ2 B2 +1.8V_MEM_VDDQ B8 RS780(RX780) VSSQ3 VSSQ4 D2 SPM_DQS1P B7 D8 R498 *1K_4 R497 *1K_4 C95 R63 SPM_DQS1N UDQS VSSQ5 A8 UDQS VSSQ6 E7 *0.1U/10V_4 *1K_4 F2 VSSQ7 VSSQ8 F8A SPM_VREF J2 H2 C775 *0.1U/10V_4 C774 *0.1U/10V_4 +1.8V_MEM_VDDQ A VREF VSSQ9 VSSQ10 H8 A2 NC#A2 C89 R61 E2 A3 *0.1U/10V_4 *1K_4 SPM_BA2 NC#E2 VSS1 L1 NC#L1 VSS2 E3 R3 J3 PROJECT : QT8 NC#R3 VSS3 R7 NC#R7 VSS4 N1 Quanta Computer Inc. R8 NC#R8 VSS5 P9 *HYB18T512161B2F-25 Size Document Number Rev Custom 1A RS740/RS780-HT LINK I/F 1/5 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 8 of 45 5 4 3 2 1
    • 5 4 3 2 1 PEG_RX15 PEG_RX#15 PEG_RX14 PEG_RX#14 PEG_RX13 PEG_RX#13 D4 C4 A3 B3 C2 U32B GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P PART 2 OF 6 GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P A5 B5 A4 B4 C3 C_PEG_TX15 C_PEG_TX#15 C_PEG_TX14 C_PEG_TX#14 C_PEG_TX13 C_PEG_TX#13 C360 C359 C362 C361 C343 C354 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 PEG_TX15 PEG_TX#15 PEG_TX14 PEG_TX#14 PEG_TX13 PEG_TX#13 17 PEG_RX#[15:0] 17 PEG_RX[15:0] PEG_RX#[15:0] PEG_RX[15:0] Close to North Bridge PEG_TX#[15:0] PEG_TX[15:0] PEG_TX#[15:0] 17 PEG_TX[15:0] 17 9 C1 GFX_RX2N GFX_TX2N B2 PEG_RX12 E5 D1 C_PEG_TX12 C351 0.1U/10V_4 PEG_TX12 PEG_RX#12 GFX_RX3P GFX_TX3P C_PEG_TX#12 C350 0.1U/10V_4 PEG_TX#12 F5 GFX_RX3N GFX_TX3N D2 PEG_RX11 G5 E2 C_PEG_TX11 C814 0.1U/10V_4 PEG_TX11 PEG_RX#11 GFX_RX4P GFX_TX4P C_PEG_TX#11 C815 0.1U/10V_4 PEG_TX#11 G6 GFX_RX4N GFX_TX4N E1 PEG_RX10 H5 F4 C_PEG_TX10 C810 0.1U/10V_4 PEG_TX10 PEG_RX#10 GFX_RX5P GFX_TX5P C_PEG_TX#10 C809 0.1U/10V_4 PEG_TX#10 H6 GFX_RX5N GFX_TX5N F3D PEG_RX9 J6 F1 C_PEG_TX9 C811 0.1U/10V_4 PEG_TX9 C_PEG_TX15 D GFX_RX6P GFX_TX6P C_PEG_TX15 23 PEG_RX#9 J5 F2 C_PEG_TX#9 C813 0.1U/10V_4 PEG_TX#9 C_PEG_TX#15 GFX_RX6N GFX_TX6N C_PEG_TX#15 23 PEG_RX8 J7 H4 C_PEG_TX8 C806 0.1U/10V_4 PEG_TX8 PEG_RX#8 GFX_RX7P GFX_TX7P C_PEG_TX#8 C805 0.1U/10V_4 PEG_TX#8 C_PEG_TX14 J8 H3 PCIE I/F GFX GFX_RX7N GFX_TX7N C_PEG_TX14 23 PEG_RX7 L5 H1 C_PEG_TX7 C804 0.1U/10V_4 PEG_TX7 C_PEG_TX#14 GFX_RX8P GFX_TX8P C_PEG_TX#14 23 PEG_RX#7 L6 H2 C_PEG_TX#7 C800 0.1U/10V_4 PEG_TX#7 PEG_RX6 GFX_RX8N GFX_TX8N C_PEG_TX6 C798 0.1U/10V_4 PEG_TX6 C_PEG_TX13 M8 GFX_RX9P GFX_TX9P J2 C_PEG_TX13 23 PEG_RX#6 L8 J1 C_PEG_TX#6 C801 0.1U/10V_4 PEG_TX#6 C_PEG_TX#13 GFX_RX9N GFX_TX9N C_PEG_TX#13 23 PEG_RX5 P7 K4 C_PEG_TX5 C791 0.1U/10V_4 PEG_TX5 PEG_RX#5 GFX_RX10P GFX_TX10P C_PEG_TX#5 C795 0.1U/10V_4 PEG_TX#5 C_PEG_TX12 M7 GFX_RX10N GFX_TX10N K3 C_PEG_TX12 23 PEG_RX4 P5 K1 C_PEG_TX4 C792 0.1U/10V_4 PEG_TX4 C_PEG_TX#12 GFX_RX11P GFX_TX11P C_PEG_TX#12 23 PEG_RX#4 M5 K2 C_PEG_TX#4 C796 0.1U/10V_4 PEG_TX#4 PEG_RX3 GFX_RX11N GFX_TX11N C_PEG_TX3 C788 0.1U/10V_4 PEG_TX3 R8 M4 PEG_RX#3 P8 GFX_RX12P GFX_RX12N GFX_TX12P GFX_TX12N M3 C_PEG_TX#3 C785 0.1U/10V_4 PEG_TX#3 To HDMI CONN PEG_RX2 R6 M1 C_PEG_TX2 C787 0.1U/10V_4 PEG_TX2 PEG_RX#2 GFX_RX13P GFX_TX13P C_PEG_TX#2 C784 0.1U/10V_4 PEG_TX#2 R5 GFX_RX13N GFX_TX13N M2 PEG_RX1 P4 N2 C_PEG_TX1 C778 0.1U/10V_4 PEG_TX1 PEG_RX#1 GFX_RX14P GFX_TX14P C_PEG_TX#1 C783 0.1U/10V_4 PEG_TX#1 P3 GFX_RX14N GFX_TX14N N1 PEG_RX0 T4 P1 C_PEG_TX0 C771 0.1U/10V_4 PEG_TX0 PEG_RX#0 GFX_RX15P GFX_TX15P C_PEG_TX#0 C777 0.1U/10V_4 PEG_TX#0 T3 GFX_RX15N GFX_TX15N P2 PCIE_RXP0 AE3 AC1 PCIE_TXP0_C C158 0.1U/10V_4 33 PCIE_RXP0 GPP_RX0P GPP_TX0P PCIE_TXP0 33 33 PCIE_RXN0 PCIE_RXN0 AD4 GPP_RX0N GPP_TX0N AC2 PCIE_TXN0_C C159 0.1U/10V_4 PCIE_TXN0 33 TO EPRESS CARD PCIE_RXP1 AE2 AB4 PCIE_TXP1_C C131 0.1U/10V_4 36 PCIE_RXP1 GPP_RX1P GPP_TX1P PCIE_TXP1 36 36 PCIE_RXN1 PCIE_RXN1 AD3 GPP_RX1N GPP_TX1N AB3 PCIE_TXN1_C C130 0.1U/10V_4 PCIE_TXN1 36 TO WLAN PCIE_RXP6_LAN AD1 AA2 PCIE_TXP6_C C149 0.1U/10V_4 31 PCIE_RXP6_LAN GPP_RX2P GPP_TX2P PCIE_TXP6_LAN 31 31 PCIE_RXN6_LAN PCIE_RXN6_LAN AD2 GPP_RX2N PCIE I/F GPP GPP_TX2N AA1 PCIE_TXN6_C C148 0.1U/10V_4 PCIE_TXN6_LAN 31 TO PCIE-LAN PCIE_RXP3 V5 Y1 PCIE_TXP3_C C772 0.1U/10V_4 36 PCIE_RXP3 GPP_RX3P GPP_TX3P PCIE_TXP3 36 36 PCIE_RXN3 PCIE_RXN3 W6 GPP_RX3N GPP_TX3N Y2 PCIE_TXN3_C C773 0.1U/10V_4 PCIE_TXN3 36 TO TV TUNNER T223 PCIE_RXP4 U5 Y4 PCIE_TXP4_CC GPP_RX4P GPP_TX4P T224 C T225 PCIE_RXN4 U6 Y3 PCIE_TXN4_C GPP_RX4N GPP_TX4N T226 PCIE_RXP5 U8 V1 PCIE_TXP5_C C139 0.1U/10V_4 26 PCIE_RXP5 GPP_RX5P GPP_TX5P PCIE_TXP5 26 26 PCIE_RXN5 PCIE_RXN5 U7 GPP_RX5N GPP_TX5N V2 PCIE_TXN5_C C140 0.1U/10V_4 PCIE_TXN5 26 TO PCIE CARD READER AA8 AD7 A_TX0P_C C766 0.1U/10V_4 PCIE_NB_SB_TX0P 12 12 PCIE_SB_NB_RX0P SB_RX0P SB_TX0P Y8 AE7 A_TX0N_C C767 0.1U/10V_4 PCIE_NB_SB_TX0N 12 12 PCIE_SB_NB_RX0N SB_RX0N SB_TX0N AA7 AE6 A_TX1P_C C765 0.1U/10V_4 PCIE_NB_SB_TX1P 12 12 PCIE_SB_NB_RX1P SB_RX1P SB_TX1P Y7 AD6 A_TX1N_C C764 0.1U/10V_4 PCIE_NB_SB_TX1N 12 12 PCIE_SB_NB_RX1N SB_RX1N SB_TX1N AA5 PCIE I/F SB AB6 A_TX2P_C C150 0.1U/10V_4 PCIE_NB_SB_TX2P 12 12 PCIE_SB_NB_RX2P SB_RX2P SB_TX2P AA6 AC6 A_TX2N_C C151 0.1U/10V_4 PCIE_NB_SB_TX2N 12 12 PCIE_SB_NB_RX2N SB_RX2N SB_TX2N W5 AD5 A_TX3P_C C754 0.1U/10V_4 PCIE_NB_SB_TX3P 12 12 PCIE_SB_NB_RX3P SB_RX3P SB_TX3P Y5 AE5 A_TX3N_C C755 0.1U/10V_4 PCIE_NB_SB_TX3N 12 12 PCIE_SB_NB_RX3N SB_RX3N SB_TX3N AC8 NB_PCIECALRP R491 1.27K/F_4 PCE_CALRP(PCE_BCALRP) NB_PCIECALRN R489 2K/F_4 PCE_CALRN(PCE_BCALRN) AB8 +1.1V RS780(RX780) RX780/RS740/RS780 difference table (PCIE LINK) RS780 Display Port Support (muxed on GFX) RS740 RX780/RS780 GFX_TX0,TX1,TX2 and TX3 NB_PCIECALRP 562R (GND) 1.27K (GND) DP0 AUX0 and HPD0 GPP4 NC GPP4 GFX_TX4,TX5,TX6 and TX7 DP1B GPP5 NC GPP5 AUX1 and HPD1 BA A PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev Custom 1A RS740/RS780-PCIE I/F 2/5 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 9 of 45 5 4 3 2 1
    • 5 4 3 2 1 U32C RX780: Powered from the 1.8-V and driven by SB600 LDT_RST#, SB700 LDT_RST# or A_RST#. RS780: Powered from the 3.3-V and driven by SB600 LDT_RST#, rail or rail or +3V_AVDD_NB +1.8V_AVDDDI_NB +1.8V_AVDDQ_NB F12 E12 F14 G15 H15 H14 AVDD1(NC) AVDD2(NC) AVDDDI(NC) AVSSDI(NC) AVDDQ(NC) AVSSQ(NC) PART 3 OF 6 TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC) TXOUT_L2N(DBG_GPIO0) A22 B22 A21 B21 B20 A20 LA_DATAP0 LA_DATAN0 LA_DATAP1 LA_DATAN1 LA_DATAP2 LA_DATAN2 LA_DATAP3 LA_DATAP0 LA_DATAN0 LA_DATAP1 LA_DATAN1 LA_DATAP2 LA_DATAN2 23 23 23 23 23 23 10 SB700 LDT_RST# or A_RST#. TXOUT_L3P(NC) A19 T159 S-CD1 E17 B19 LA_DATAN3 CRT/TVOUT C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) T157 R109 for UAM use 140 ohm F17 Y(DFT_GPIO2) LB_DATAP0 RX780 F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 LB_DATAP0 23 R157 *0_4 NB_RST#_IN A18 LB_DATAN0 3,12 CPU_LDT_RST# TXOUT_U0N(NC) LB_DATAN0 23 18,24 CRT_R R446 *0_4 CRT_R_1 G18 A17 LB_DATAP1 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) LB_DATAP1 23 RS780 R109 *150/F_4 G17 B17 LB_DATAN1 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) LB_DATAN1 23 R160 0_4 18,24 CRT_G R445 *0_4 CRT_G_1 E18 D20 LB_DATAP2 12 NB_PLTRST# GREEN(DFT_GPIO1) TXOUT_U2P(NC) LB_DATAP2 23 R110 *150/F_4 F18 D21 LB_DATAN2 GREENb(NC) TXOUT_U2N(NC) LB_DATAN2 23D North Bridge RESET 18,24 CRT_B R444 *0_4 CRT_B_1 E19 D18 LB_DATAP3 D BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) T163 R111 *150/F_4 F19 D19 LB_DATAN3 BLUEb(NC) TXOUT_U3N(NC) T160 R549 *0_4 HSYNC_INT A11 B16 LA_CLK 18,19,24 HSYNC_COM DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) LA_CLK 23 R540 *0_4 VSYNC_INT B11 A16 LA_CLK# 18,19,24 VSYNC_COM DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) LA_CLK# 23 R133 *0_4 DDCDATA_INT E8 D16 LB_CLK 18,24 DDCDATA DAC_SDA(PCE_TCALRN) TXCLK_UP(PCIE_RESET_GPIO4) LB_CLK 23 R134 *0_4 DDCCLK_INT F8 D17 LB_CLK# 18,24 DDCCLK DAC_SCL(PCE_RCALRN) TXCLK_UN(PCIE_RESET_GPIO1) LB_CLK# 23 R119 *715/F_6 DAC_RSET_NB G14 DAC_RSET(PWM_GPIO1) +1.8V_VDDLTP18_NB VDDLTP18(NC) A13 +1.1V_PLLVDD A12 B13 +1.8V_PLLVDD18 PLLVDD(NC) VSSLTP18(NC) D14 LVTM PLLVDD18(NC) +1.8V_VDDLT_18_NB B12 A15 PLL PWR PLLVSS(NC) VDDLT18_1(NC) VDDLT18_2(NC) B15 +1.8V_VDDA18HTPLL H17 A14 +3V_VDLT33_NB VDDA18HTPLL VDDLT33_1(NC) VDDLT33_2(NC) B14 +1.8V_VDDA18PCIEPLL D7 VDDA18PCIEPLL1 E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14 VSSLT2(VSS) D15 NB_RST#_IN D8 C16 NB_PWRGD_IN SYSRESETb VSSLT3(VSS) 16 NB_PWRGD_IN A10 POWERGOOD VSSLT4(VSS) C18 NB_LDT_STOP# C10 C20 PM NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS) C12 ALLOW_LDTSTOP VSSLT6(VSS) E20 VSSLT7(VSS) C22 NBHT_REFCLKP C25 2 NBHT_REFCLKP HT_REFCLKP 2 NBHT_REFCLKN NBHT_REFCLKN C24 HT_REFCLKN I RS780 only R117 0_4 NB_REFCLK_P E11 2 EXT_NB_OSC REFCLK_P/OSCIN(OSCIN) CLOCKs NB_REFCLK_N F11 I E9 R132 *0_4 DISP_ON REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) DISP_ON 19,23 +1.1V F7 R126 *0_4 LVDS_BLON LVDS_BLON(PCE_RCALRP) LVDS_BLON 18,23 R125 RS780 RS780 R120 NBGFX_CLKP T2 G12 R118 *0_4 DPST_PWM GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) DPST_PWM 19,23 4.7K_4 4.7K_4 NBGFX_CLKN T1 I/O GFX_REFCLKN 2 NBGFX_CLKP NBGPP_CLKP U1 2 NBGFX_CLKN GPP_REFCLKP Del NBGPP CLK NBGPP_CLKN U2 I/O R121 *1.27K/F_4 T168 GPP_REFCLKNC T169 For RX780 only C SBLINK_CLKP V4 R127 *1.27K/F_4 2 SBLINK_CLKP GPPSB_REFCLKP(SB_REFCLKP) SBLINK_CLKN V3 2 SBLINK_CLKN GPPSB_REFCLKN(SB_REFCLKN) +3V R536 4.7K_4 HDTV_DET 18,23 EDIDDATA R547 *0_4 NB_I2C_DATA A9 I2C_DATA R545 UMA only R546 *0_4 NB_I2C_CLK TMDS_HPD0 *0_4 RS780 only R539 4.7K_4 NB_I2C_DATA 18,23 EDIDCLK R537 *0_4 HDTV_DET B9 B8 I2C_CLK MIS. TMDS_HPD(NC) D9 D10 TMDS_HPD1 TMDS_HPD 18,23 23 HDMI_DDC_DATA DDC_DATA/AUX0N(NC) HPD(NC) T162 R544 *0_4 RS740_DFT_GPIO0 A8 23 HDMI_DDC_CLK DDC_CLK/AUX0P(NC) R538 4.7K_4 NB_I2C_CLK RS740_DFT_GPIO1 B7 D12 SUS_STAT#_NB R131 0_4 T161 AUX1P(NC) TVCLKIN(PWM_GPIO5) SUS_STAT# 13 T158 A7 AUX1N(NC) AE8 R_NB_THRMDA THERMALDIODE_P T136 R27 0_4 STRP_DATA B10 AD8 R_NB_THRMDC 39 DYN_PWR_EN STRP_DATA THERMALDIODE_N T135 G11 RSVD TESTMODE D13 TEST_EN selects Loading of straps from RS780_AUX_CAL C8 R541 T164 AUX_CAL(NC) EPROM 1.82K/F_4 1 : use default vaule , default RS780(RX780) 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected BLM18PG181SN1D(180,1.5A)_6 RX780 --RS780_AUX_CAL RX780 RX780 -->NC / RS780 --- ADD +1.1V_PLLVDD +1.1V RS780 -- SUS_ATAT +3V L35 +3V_AVDD_NB L82 RS780_AUX_CAL R543 3K_4 BLM18PG181SN1D(180,1.5A)_6 PLLVDD - Graphics PLL +1.8V not applicable to AVDD-DAC Analog C842 RX780 BLM18PG181SN1D(180,1.5A)_6 not applicable to RX780 C340 2.2U/6.3V_6 +1.8V_VDDLTP18_NB 2.2U/6.3V_6 L83 C841 VDDLTP18 - LVDS or DVI/HDMI PLL 2.2U/6.3V_6 not applicable to RX780 +1.8V Enables Debug Bus acessB through memory T/O pads and GPIO. RS780 +1.8V B BLM21PG221SN1D(220,100M,2A)_8 0 : Enable RS780 , Default VSYNC_COM R124 3K_4 L33 +1.8V_PLLVDD18 R107 0_6 +1.8V_AVDDDI_NB AVDDI-DAC Digital +1.8V_VDDLT_18_NB +3V 1 : Disable RS780 BLM18PG181SN1D(180,1.5A)_6 not applicable to RX780 L85 (RS780 use VSYNC#) VDDLT18 - LVDS or C321 DVI/HDMI digital C405 C333 2.2U/6.3V_6 C846 C838 10U/6.3V_8 not applicable to 2.2U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 RX780 BLM18PG181SN1D(180,1.5A)_6 AVDDQ-DAC Bandgap Reference PLLVDD18 - Graphics PLL +1.8V_AVDDQ_NB not applicable to RX780 not applicable to RX780 L34 Indicates if memory Side port RS780 is available or not C349 HSYNC_COM R129 3K_4 +3V 2.2U/6.3V_6 0: available RS780 , Default 1: Not available RS780 R136 *3K_4 ( RS780 use HSYNC#) R566 *0_6 RX780 +1.8V +VDDG_NB +1.8V VDDA18PCIEPLL -PCIE PLL +1.8V +VDDG_NB R565 0_6 For extrnal EEPROM Debug only 20mils width RS780/RX780 L32 +1.8V_VDDA18PCIEPLL RS780 RS780 +3V Q37 R556 RS780 2 STRP_DATA R548 10K/F_4 +VDDG_NB BLM18PG181SN1D(180,1.5A)_6 BSS138_NL/SOT23 4.7K_4 C358 1 3 NB_LDT_STOP# L84 3,12 CPU_LDT_STOP# R558 *10K/F_4 2.2U/6.3V_6 +3V +3V_VDLT33_NB *BLM21PG221SN1D(220,100M,2A)_8 C844 R555 *0_4 VDDA18HTPLL -HT LINK PLL RX780 *2.2U/6.3V_6A A 20mils width L31 +1.8V_VDDA18HTPLL +VDDG_NB Enables Debug Bus acess RX780 +1.8V RS780 VDDLT33 - LVDS or DVI/HDMI ANALOG through memory T/O pads and GPIO. BLM18PG181SN1D(180,1.5A)_6 RS780 RS740 only R557 1 : Enable RX780 , Default S-CD1 R810 *3K_4 C356 Q38 4.7K_4 2 0 : Disable RX780 2.2U/6.3V_6 BSS138_NL/SOT23 Reserved only 3 CPU_LDT_REQ# R568 0_4 1 3 NB_ALLOW_LDTSTOP PROJECT : QT8 Quanta Computer Inc. R564 *0_4 Size Document Number Rev 12 ALLOW_LDTSTOP Custom RS740/RS780-SYSTEM I/F 3/5 1A RX780 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 10 of 45 5 4 3 2 1
    • 5 4 3 2 1 11 AE14 AC3 AC4 M11 AA4 AB5 AB1 AB7 AE1 AE4 AB2 D11 E14 E15 K14 L15 J15 J12 W1 W2 W4 W7 W8 M6 G1 G2 G4 G8 D3 D5 H7 R7 N4 R1 R2 R4 U4 A2 B1 E4 P6 V7 V8 V6 Y6 L1 L2 L4 L7 RX780/RS780 POWER DIFFERENCE TABLE J4 U32F VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40 VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 PIN NAME RX780 RS780 PIN NAME RX780 RS780 VDDHT +1.1V +1.1V IOPLLVDD NC +1.1V VDDHTRX +1.1V +1.1V AVDD NC +3.3V PART 6/6D D GROUND VDDHTTX +1.2V +1.2V AVDDDI NC +1.8V VDDA18PCIE +1.8V +1.8V AVDDQ NC +1.8V VDDG18 +1.8V +1.8V PLLVDD NC +1.1V VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27 VDD18_MEM NC +1.8V PLLVDD18 NC +1.8V VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VDDPCIE +1.1V +1.1V VDDA18PCIEPLL +1.8V +1.8V VDDC +1.1V +1.1V VDDA18HTPLL +1.8V +1.8V A25 D23 E22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19 W22 W24 W25 Y21 AD25 L12 M14 N13 P12 P15 R11 R14 T12 U14 U11 U15 V12 W11 W15 AC12 AA14 Y18 AB11 AB15 AB17 AB19 AE20 AB21 K11 VDD_MEM NC +1.8V/1.5V VDDLTP18 NC +1.8V VDDG33 NC +3.3V VDDLT18 NC +1.8V IOPLLVDD18 NC +1.8V VDDLT33 NC NC +1.1V VDDHT - HTC LINK digital +1.1V 2A for RS780M U32E VDDPCIE - PCIE-E Main power C I/O for 0.6A L72 +1.1V_VDDHT +1.1V_VDD_PCIE 0.7A R542 0_8 J17 VDDHT_1 VDDPCIE_1 A6 +1.1V RX780/RS780 BLM21PG221SN1D(220,100M,2A)_8 K16 PART 5/6 B6 VDDHT_2 VDDPCIE_2 L16 VDDHT_3 VDDPCIE_3 C6 C770 C274 C313 C280 M16 D6 C275 C337 C318 C328 C845 4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHT_4 VDDPCIE_4 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 4.7U/6.3V_6 P16 VDDHT_5 VDDPCIE_5 E6 VDDHTRX - HT R16 VDDHT_6 VDDPCIE_6 F6 LINK RX I/O for T16 VDDHT_7 VDDPCIE_7 G7 RX780/RS780 0.45A L81 +1.1V_VDDHTRX VDDPCIE_8 H8 H18 VDDHTRX_1 VDDPCIE_9 J9 BLM21PG221SN1D(220,100M,2A)_8 G19 K9 VDDHTRX_2 VDDPCIE_10 F20 VDDHTRX_3 VDDPCIE_11 M9 C847 C323 C843 C839 E21 L9 4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHTRX_4 VDDPCIE_12 D22 VDDHTRX_5 VDDPCIE_13 P9 B23 VDDHTRX_6 VDDPCIE_14 R9 A23 VDDHTRX_7 VDDPCIE_15 T9 L12 0.5A +1.2V 2A for RS780M+SB700 +1.2V_VDDHTTX VDDPCIE_16 V9 +1.2V AE25 VDDHTTX_1 VDDPCIE_17 U9 BLM21PG221SN1D(220,100M,2A)_8 AD24 VDDHTTX_2 7A VDDC - Core Logic power AC23 VDDHTTX_3 VDDC_1 K12 +1.1V_DYN +1.35V L13 C124 C195 C194 C249 C199 AB22 J14 *BLM21PG221SN1D(220,100M,2A)_8 4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHTTX_4 VDDC_2 AA21 VDDHTTX_5 VDDC_3 U16 +1.35V for VDDHTTX - HT Y20 VDDHTTX_6 VDDC_4 J11 C251 C292 C297 C303 C59 A1-1 chip LINK TX I/O for W19 K15 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8 POWER VDDHTTX_7 VDDC_5 bug , A1-2 RX780/RS780 V18 VDDHTTX_8 VDDC_6 M12 U17 L14 can remove T17 VDDHTTX_9 VDDC_7 L11 VDDHTTX_10 VDDC_8 R17 VDDHTTX_11 VDDC_9 M13 P17 M15B +1.8V 1A for RS780M+SB700 M17 VDDHTTX_12 VDDHTTX_13 VDDC_10 VDDC_11 N12 B L22 600mA +1.8V_VDDA18PCIE VDDC_12 N14 C281 C278 C250 C60 +1.8V J10 VDDA18PCIE_1 VDDC_13 P11 P10 P13 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8 BLM21PG221SN1D(220,100M,2A)_8 VDDA18PCIE_2 VDDC_14 K10 VDDA18PCIE_3 VDDC_15 P14 VDDA18PCIE - C188 C175 C258 C209 C302 C234 M10 VDDA18PCIE_4 VDDC_16 R12 PCIE TX stage 4.7U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 L10 R15 VDDA18PCIE_5 VDDC_17 I/O for W9 VDDA18PCIE_6 VDDC_18 T11 RX780/RS780 H9 VDDA18PCIE_7 VDDC_19 T15 VDD_MEM For UMA RS780 only T10 U12 R10 VDDA18PCIE_8 VDDC_20 T14 Not applicable to RX780 VDDA18PCIE_9 VDDC_21 Y9 VDDA18PCIE_10 VDDC_22 J16 memory I/O transform AA9 VDDA18PCIE_11 +1.8V_VDD_MEM 1.8V(0.15A) L23 AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 +1.8V 0.005A AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11 VDD18 - RS780 I/O +1.8V R122 0_6 AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11 C192 C179 C172 C216 C153 BLM21PG221SN1D(220,100M,2A)_8 transform U10 AD10 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 4.7U/6.3V_6 C317 VDDA18PCIE_15 VDD_MEM4(NC) VDD_MEM5(NC) AB10 1U/10V_4 +1.8V_VDDG18_NB F9 AC10 VDDG18_1(VDD18_1) VDD_MEM6(NC) RS780 G9 VDDG18_2(VDD18_2) +3V_VDDG33 R123 0_6 3.3V(0.03A) R499 0_6 0.005A +1.8V_VDD18_MEM AE11 VDD18_MEM1(NC) VDDG33_1(NC) H11 +3V +1.8V AD11 VDD18_MEM2(NC) VDDG33_2(NC) H12 C336 C329 VDD33 - 3.3V I/O VDD18_MEM For UMA RS780 only C769 RS780(RX780) 0.1U/10V_4 0.1U/10V_4 Not applicable to RX780 1U/10V_4 Not applicable to RX780 memory I/O transformA A PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev Custom 1A RS740/RS780-POWER5/5 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 11 of 45 5 4 3 2 1
    • 5 4 3 2 1 10 17 NB_PLTRST# PCIE_RST# R250 R252 R312 33_4 33_4 33_4 Del R639, R640, R641, R642 on PV 12 26 CARD_PLTRST# 31 LAN_PLTRST# R251 33_4 U37A R241 33_4 33 EPRESS_PLTRST# R660 33_4 A_RST#_SB N2 SB700 P4 36 MINI_PLTRST# A_RST# PCICLK0 T108 Part 1 of 5 P3 PCI CLKS PCICLK1 T214 9 PCIE_SB_NB_RX0P C869 0.1U/10V_4 A_RX0P_C V23 P1 PCI_CLK2_R PCI_CLK_TPM 16 C868 0.1U/10V_4 A_RX0N_C PCIE_TX0P PCICLK2 PCI_CLK3_RD 9 PCIE_SB_NB_RX0N V22 PCIE_TX0N PCICLK3 P2 PCI_CLK3 16 D PLACE THESE 9 PCIE_SB_NB_RX1P C865 0.1U/10V_4 A_RX1P_C V24 T4 PCI_CLK4_R PCI_CLK4 16 C864 0.1U/10V_4 A_RX1N_C PCIE_TX1P PCICLK4 PCI_CLK5_R 9 PCIE_SB_NB_RX1N V25 PCIE_TX1N PCICLK5/GPIO41 T3 PCI_CLK5 16 PCIE AC 9 PCIE_SB_NB_RX2P C871 0.1U/10V_4 A_RX2P_C U25 PCIE_TX2P To RS780 C870 0.1U/10V_4 A_RX2N_C U24 COUPLING CAPS 9 PCIE_SB_NB_RX2N C867 0.1U/10V_4 A_RX3P_C PCIE_TX2N 9 PCIE_SB_NB_RX3P T23 PCIE_TX3P CLOSE TO U600 9 PCIE_SB_NB_RX3N C866 0.1U/10V_4 A_RX3N_C T22 PCIE_TX3N PCIRST# N1 PCIRST#_L R643 33_4 PCIRST# PCIRST# 35 PCI EXPRESS INTERFACE PCIE_NB_SB_TX0P U22 9 PCIE_NB_SB_TX0P PCIE_RX0P PCIE_NB_SB_TX0N U21 U2 9 PCIE_NB_SB_TX0N PCIE_RX0N AD0 PCIE_NB_SB_TX1P U19 P7 9 PCIE_NB_SB_TX1P PCIE_RX1P AD1 PCIE_NB_SB_TX1N V19 V4 9 PCIE_NB_SB_TX1N PCIE_RX1N AD2 PCIE_NB_SB_TX2P R20 T1 +3V 9 PCIE_NB_SB_TX2P PCIE_RX2P AD3 PCIE_NB_SB_TX2N R21 V3 9 PCIE_NB_SB_TX2N PCIE_RX2N AD4 PCIE_NB_SB_TX3P R18 U1 9 PCIE_NB_SB_TX3P PCIE_RX3P AD5 PCIE_NB_SB_TX3N R17 V1 PE_GPIO1 R294 8.2K_4 9 PCIE_NB_SB_TX3N PCIE_RX3N AD6 AD7 V2 R581 562/F_4 PCIE_CALRP_SB T25 T2 R299 *8.2K_4 R587 2.05K/F_4 PCIE_CALRN_SB PCIE_CALRP AD8 +1.2V_PCIE_VDDR T24 PCIE_CALRN AD9 W1 AD10 T9 +1.2V L44 BLM18PG181SN1D(180,1.5A)_6 +1.2V_PCIE_PVDD P24 R6 SB_GPIO65 R274 *100K/F_4 PCIE_PVDD AD11 40mA AD12 R7 PCIE_PVDD-- PCIE PLL POWER P25 PCIE_PVSS AD13 R5 C485 C503 U8 10U/6.3V_8 1U/10V_4 AD14 R809 8.2K_4 AD15 U5 +3V AD16 Y7 AD17 W8 AD18 V9 AD19 Y8 AD20 AA8C AD21 Y4 C AD22 Y3 Y2 AD23 AD23 AD23 16 AA2 AD24 AD24 AD24 16 AB4 AD25 change D21, D20 type for PV AD25 AD25 16 SBSRC_CLKP N25 AA1 AD26 2 SBSRC_CLKP PCIE_RCLKP/NB_LNK_CLKP AD26 AD26 16 SBSRC_CLKN N24 AB3 AD27 2 SBSRC_CLKN PCIE_RCLKN/NB_LNK_CLKN AD27 AD27 16 AB2 AD28 AD28 AD28 16 K23 AC1 PCI INTERFACE NB_DISP_CLKP AD29 K22 NB_DISP_CLKN AD30 AC2 AD1 D21 AD31 M24 NB_HT_CLKP CBE0# W2 SI-2 mofified for satify -- RB500V-40 +AVBAT M25 NB_HT_CLKN 100MHZ CBE1# U7 remove R560 , add R796 ,R797 +3VPCU CBE2# AA7 All the PCI bus has P17 M18 CPU_HT_CLKP CBE3# Y1 AA6 build-in Pull-UP/Down 20MILR796 499/F_4 +3VRTC_1 R797 10_4 +3VRTC CPU_HT_CLKN FRAME# DEVSEL# W5 resistors RTC_X1 D20 M23 AA5 20MIL 20MIL +VCCRTC_2 SLT_GFX_CLKP IRDY# RB500V-40 Y8 M22 SLT_GFX_CLKN TRDY# Y5 U6 C906 PAR C907 3 2 J19 GPP_CLK0P STOP# W6 1U/10V_4 J18 GPP_CLK0N PERR# W4 V7 SERR# SERR# 35 1U/10V_4 20MIL SERR# R298 L20 GPP_CLK1P REQ0# AC3 4 1 RTC_X2 L19 GPP_CLK1N REQ1# AD4 SI-2 Modified-- for power leakage issue R632 AB7 Del R783 for 0_4 CLOCK GENERATOR REQ2# R187 0_4 32.768KHZ M19 GPP_CLK2P REQ3#/GPIO70 AE6 RF_OFF# 36 TP on PV M20 GPP_CLK2N REQ4#/GPIO71 AB6 D3E GPIO# 26 *20M_6 R626 20M_6 AD2 +BAT GNT0# SI-2 Modified-- Add GPIO pin for control D3E wake up ( need low 1msB N22 P22 GPP_CLK3P GNT1# AE4 AD5 for Jmicron request) 20MIL B C900 C899 GPP_CLK3N GNT2# PE_GPIO1 GNT3#/GPIO72 AC6 18P/50V_4 18P/50V_4 L18 AE5 R631 0_4 LCD_BK 23 25M_48M_66M_OSC GNT4#/GPIO73 1 AD6 CLKRUN#_R R629 0_4 CLKRUN# CLKRUN# 35 V5 BT1 LOCK# T94 R257 0_4 J21 25M_X1 INTE# BAT_CONN AD3 T213 2 INTE#/GPIO33 INTF# INTF#/GPIO34 AC4 T110 R589 change to 10 ohm on PV AE2 INTG# INTG#/GPIO35 T217 T74 J20 AE3 INTH# 25M_X2 INTH#/GPIO36 INTH# 28 LPC_CLK0 16 LPC_CLK1 16 If CPU have pull Hi ,this LPCCLK0 G22 LPC_CLK0 R243 22_4 PCLK_LPC_DEBUG 36 pin should be not need E22 LPC_CLK1 R589 10_4 LPCCLK1 PCLK_LPC_KB3920 35 RTC_X1 A3 H24 LAD0 RTC XTAL X1 LAD0 LAD0 35,36 LAD1 H23 LAD1 LAD1 35,36 SI-2 +1.8V R232 *10K/F_4 J25 LAD2 C940 modified LAD2 LAD2 35,36 PV-1 J24 LAD3 LPC RTC_X2 LAD3 LFRAME# LAD3 35,36 5.6P/50V_6 C939 -- for EMI Modified B3 X2 LFRAME# H25 LFRAME# 35,36 suggestion H22 LDRQ0#_SB 22P/50V_4 -- change LDRQ0# LDRQ1#_SB T61 LDRQ1#/GNT5#/GPIO68 AB8 T90 to pull hi AD7 SB_GPIO65 BMREQ#/REQ5#/GPIO65 T107 to 3VS5 +3VS5 R588 10K/F_4 SERIRQ V15 SERIRQ SERIRQ 35 for power SI-1 Modified - for EMI ALLOW_LDTSTOP F23 leakage 10 ALLOW_LDTSTOP CPU_PROCHOT# ALLOW_LDTSTP RTC_CLK 3 CPU_PROCHOT# F24 PROCHOT# RTCCLK C3 RTC_CLK 16 issue 3 CPU_PWRGD CPU_PWRGD F22 C2 INTRUDER_ALERT# R782 *1M/F_4 +AVBAT RTC LDT_PG INTRUDER_ALERT# CPU 3,10 CPU_LDT_STOP# CPU_LDT_STOP# G25 LDT_STP# VBAT B2 +AVBAT +AVBAT SI-2 Modified--reserve 3,10 CPU_LDT_RST# CPU_LDT_RST# G24 LDT_RST# INTRUDER_ALERT# Left not connected (SouthbridgeA 20MIL 1 G3 has 50-kohm internal pull-up to VBAT). A SB700 *SHORT_ PAD1 C902 IC CTRL(528P) SB700 A11(218S7EALA11FG) 0.1U/10V_4 P/N : AJALA110T00 2 PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev Custom 1A SB700-PCIE/PCI/CPU/LPC 1/4 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 12 of 45 5 4 3 2 1
    • 5 4 3 2 1 +3VSUS R297 R240 NC only ,Cant be install *2.2K_4 *2.2K_4 SB_TEST0 SB_TEST1 NEWCARD_DETECT E1 U37D SB700 Part 4 of 5 13 33 NEWCARD_DETECT PCI_PME#/GEVENT4# RI# E2 C8 CLK_48M_USB T211 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC CLK_48M_USB 2 R287 *2.2K_4 SB_TEST2 SLP_S2 H7 CLK_48M_USB T99 SLP_S2/GPM9# R271 *0_4 SUSB# F5 G8 USB_RCOMP_SB R267 11.8K/F_6 USB MISC 35 SUSB# SLP_S3# USB_RCOMP R191 *0_4 SUSC# G1 35 SUSC# SLP_S5# ACPI / WAKE UP EVENTS R233 *0_4 DNBSWON# H2 +3VSUS 35 DNBSWON# PWR_BTN# SB_PWRGD_IN H1D 16 SB_PWRGD_IN PWR_GOOD D SUS_STAT# K3 C554 10 SUS_STAT# SUS_STAT# R289 *10K/F_4 SWI# SB_TEST2 H5 E6 USB_FSD13P *2.2P/50V_4 TEST2 USB_FSD13P T101 SI-2 modified add D3E function SB_TEST1 H4 TEST1 USB_FSD13N E7 USB_FSD13N T199 SB_TEST0 H3 TEST0 USB 1.1 GATEA20 Y15 F7 USB_FDS12P +3V SCL0/SDATA0 35 GATEA20 GA20IN/GEVENT0# USB_FSD12P T91 is 3V tolerance Clock gen/Robson/TV 35 RCIN# RCIN# W15 KBRST#/GEVENT1# USB_FSD12N E8 USB_FSD12N T93 AMD datasheet define it tuner SCI# K4 35 SCI# LPC_PME#/GEVENT3# KBSMI# K24 H11 R245 2.2K_4 PCLK_SMB /DDR2/DDR2 35 KBSMI# GEVENT5# LPC_SMI#/EXTEVNT1# USB_HSD11P USBP11+ 36 thermal/Accelerometer T109 F1 S3_STATE/GEVENT5# USB_HSD11N J10 USBP11- 36 TV Min-Card SYS_RST# J2 SYS_RESET#/GPM7# R253 2.2K_4 PDAT_SMB 31,33,36 PCIE_WAKE# PCIE_WAKE# H6 WAKE#/GEVENT8# USB_HSD10P E11 USBP10+ 36 for EMI & del R268 R211 *0_4 SWI# F2 F11 WLAN Min-Card 35 SWI# R786 0_4 SB_THERMTRIP# J6 BLINK/GPM6# USB_HSD10N USBP10- 36 change 2.2P 3 CPU_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2# WD_PWRGD W14 A11 16 WD_PWRGD NB_PWRGD USB_HSD9P USBP9+ 30 +3VS5 USB_HSD9N B11 USBP9- 30 USB Connector SCL1/SDATA1 is 3V/S5 tolerance 35 RSMRST# R284 *0_4 RSMRST# D3 RSMRST# AMD datasheet define it SI-2 modified -- Change lan USB_HSD8P C10 USBP8+ 30 disable control from SB to EC SB USB_HSD8N D10 USBP8- 30 USB Connector R648 *2.2K_4 SB_SMBCLK1 R649 *2.2K_4 SB_SMBDATA1 reserve T63 AE18 SATA_IS0#/GPIO10 USB_HSD7P G11 USBP7+ 33 SATA_IS1 AD18 H12 NEW CARD T194 CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USBP7- 33 R217 *0_4 LAN_DISABLE#_SB AA19 31,35 LAN_DISABLE# SMARTVOLT/SATA_IS2#/GPIO4 remove pull hi W17 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P E12 USBP6+ 30 ( chip internal SB_NWD_CLK_REQ# V17 E14 FINGERPRINT T222 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N USBP6- 30 have pull hi ) W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 R302 *0_4 ACZ_SPKR W21 C12 USB 2.0 27,28 ACZ_SPKR SPKR/GPIO2 USB_HSD5P USBP5+ 30 PCLK_SMB AA18 D12 BLUETOOTH 2,6,7,28,36 PCLK_SMB SCL0/GPOC0# USB_HSD5N USBP5- 30 PDAT_SMB W18 +3VS5 2,6,7,28,36 PDAT_SMB SDA0/GPOC1# SCL2/SDATA2 is 3V/S5 tolerance SB_SMBCLK1 K1 SCL1/GPOC2# USB_HSD4P B12 USBP4+ 37C AMD datasheet define it SB_SMBDATA1 K2 A12 Docking C GPIO SDA1/GPOC3# USB_HSD4N USBP4- 37 T69 AA20 DDC1_SCL/GPIO9 R222 *2.2K_4 SB_SCLK2 Y18 G12 T75 DDC1_SDA/GPIO8 USB_HSD3P USBP3+ R227 *2.2K_4 SB_SDATA2 PM_BATLOW# C1 G14 USB card reader or Touch screen 35 PM_BATLOW# LLB#/GPIO66 USB_HSD3N USBP3- SES_INT Y19 T72 SHUTDOWN#/GPIO5 26 D3E_SCI# G5 DDR3_RST#/GEVENT7# USB_HSD2P H14 USBP2+ 30 +3V H15 Carama USB USB_HSD2N USBP2- 30 D3E_SCI# from Gevent5# change to Gevent7# on PV USB_HSD1P A13 USBP1+ 30 R276 4.7K_4 SUS_STAT# SI-2 modified Del D35 USB_HSD1N B13 USBP1- 30 E-SATA and USB Connector G4 USB_HSD0P B14 USBP0+ 30 2 1 SYS_RST# CPU_MEMHOT#_IN B9 A14 USB Connector 3,7 CPU_MEMHOT# USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USBP0- 30 R275 *0_4 SMBALERT#_1 B8 5 PM_THERM# USB_OC5#/IR_TX0/GPM5# R279 *10K/F_4 A8 A18 USB OC *SHORT_ PAD1 +3VS5 USB_OC4#/IR_RX0/GPM4# IMC_GPIO8 SB_JTAG_TDO A9 B18 SB_JTAG_TCK USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 E5 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 F21 +3VS5 SB_JTAG_TDI F8 D21 SB_SCLK2 SB_JTAG_RST# USB_OC1#/GPM1# SCL2/IMC_GPIO11 SB_SDATA2 E4 USB_OC0#/GPM0# SDA2/IMC_GPIO12 F19 R763 2.2K_4 DNBSWON# E20 SB_SCLK3 SCL3_LV/IMC_GPIO13 T64 ACZ_BCLK M1 E21 SB_SDATA3 AZ_BITCLK SDA3_LV/IMC_GPIO14 T70 ACZ_SDOUT M2 E19 ACZ_SDIN0_R AZ_SDOUT IMC_PWM1/IMC_GPIO15 SB_GPIO16 J7 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 D19 SB_GPIO16 16 ACZ_SDIN1_R SB_GPIO17 SPI/LPC define HD AUDIO J8 E18 To Azalia T98 T209 L8 M3 AZ_SDIN1/GPIO43 AZ_SDIN2/GPIO44 IMC_PWM3/IMC_GPO17 G20 SB_GPIO17 16 ACZ_SDOUT R644 33_4 ACZ_SYNC AZ_SDIN3/GPIO46 IMC_GPIO18 ACZ_SDOUT_AUDIO 27 L6 AZ_SYNC IMC_GPIO19 G21 ACZ_RST# M4 D25 16 ACZ_RST# AZ_RST# IMC_GPIO20 INTEGRATED uC C908 *10P/50V_4 L5 D24 AZ_DOCK_RST#/GPM8# IMC_GPIO21B HD audio IMC_GPIO22 C25 B interface is IMC_GPIO23 C24 ACZ_SYNC R290 33_4 B25 ACZ_SYNC_AUDIO 27 3.3S5 voltage IMC_GPIO24 IMC_GPIO25 C23 C569 *10P/50V_4 IMC_GPIO26 B24 IMC_GPIO27 B23 ACZ_BCLK R646 33_4 A23 BIT_CLK_AUDIO 27 IMC_GPIO28 IMC_GPIO29 C22 C910 10P/50V_4 A22 IMC_GPIO30 +3VS5 IMC_GPIO31 B22 IMC_GPIO32 B21 ACZ_RST# R296 33_4 A21 +3V ACZ_RST#_AUDIO 27 IMC_GPIO33 H19 IMC_GPIO0 IMC_GPIO34 D20 INTEGRATED uC +3VS5 H20 C20 R764 IMC_GPIO1 IMC_GPIO35 2 ACZ_SDIN0_R R295 0_4 ACZ_SDIN0 27 H21 A20 2K/04 R592 22K_4 HDD_AUX_RST# SPI_CS2#/IMC_GPIO2 IMC_GPIO36 F25 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37 B20 B19 3 1 PCLK_SMB IMC_GPIO38 33,36 SCLK_WLAN SI-2 Modified --for D22 IMC_GPIO4 IMC_GPIO39 A19 EMI suggestion E24 D18 Q66 To Modem Board E25 D23 IMC_GPIO5 IMC_GPIO6 IMC_GPIO40 IMC_GPIO41 C18 +3VS5 2N7002EPT ACZ_SDOUT R645 33_4 IMC_GPIO7 +3V ACZ_SDOUT_AUDIO_MDC 29 C909 *10P/50V_4 R765 2 2K/04 SB700 ACZ_SYNC R292 33_4 3 1 PDAT_SMB ACZ_SYNC_AUDIO_MDC 29 +3VSUS 33,36 SDATA_WLAN C577 *10P/50V_4 CN16 C462 SI-2 Modified -- discrete remove RP56A 10P/50V_4 A 2N7002EPT Q67 ACZ_BCLK R647 33_4 1 SB_JTAG_TCK BIT_CLK_AUDIO_MDC 29 2 CLOSE TO SB SB_JTAG_TDO C911 10P/50V_4 3 SB_JTAG_TDI USBP3- SB JTAG 4 SB_TEST1 USBP3+ 2 1 USBP6_CR- 25 PROJECT : QT8 5 4 3 USBP6_CR+ 25 RP50 *0_4P2R_4 6 Quanta Computer Inc. ACZ_RST# R293 33_4 SB_JTAG_RST# UMA ACZ_RST#_AUDIO_MDC 29 7 8 ACZ_SDIN1_R R286 0_4 *S/W JTAG DEBUG Size Document Number Rev ACZ_SDIN1 29 Custom 1A SB700-ACPI/GPIO/USB 2/4 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 13 of 45 5 4 3 2 1
    • 5 4 3 2 1 SATA PORT 0,1,2,3 can support AHCI mode PLACE SATA AC COUPLING CAPS CLOSE TO SB600 C559 0.01U/16V_4 SATA_TXP0_C AD9 U37B SB700 AA24 14 33 SATA_TXP0 SATA_TX0P IDE_IORDY T231 C558 0.01U/16V_4 SATA_TXN0_C Part 2 of 5 SATA1 33 SATA_TXN0 AE9 SATA_TX0N IDE_IRQ AA25 Y22 T232 IDE_A0 T233 C563 0.01U/16V_4 SATA_RXN0_C AB10 AB23 33 SATA_RXN0 SATA_RX0N IDE_A1 T234 C562 0.01U/16V_4 SATA_RXP0_C AC10 Y23 33 SATA_RXP0 SATA_RX0P IDE_A2 T235 IDE_DACK# AB24 T236 C544 0.01U/16V_4 SATA_TXP1_CD SATA ODD 33 SATA_TXP4 C543 0.01U/16V_4 SATA_TXN1_C AE10 AD10 SATA_TX1P IDE_DRQ AD25 AC25 T237 D 33 SATA_TXN4 SATA_TX1N IDE_IOR# T238 IDE_IOW# AC24 T239 C535 0.01U/16V_4 SATA_RXN1_C AD11 Y25 33 SATA_RXN4 SATA_RX1N IDE_CS1# T240 C529 0.01U/16V_4 SATA_RXP1_C AE11 Y24 IF THERE IS NO IDE, TEST 33 SATA_RXP4 SATA_RX1P IDE_CS3# T241 R613 4.99/F_4 SATA_TXP2_C AB12 AD24 POINTS FOR DEBUG BUS 30 SATA_TXP2 SATA_TX2P IDE_D0/GPIO15 T242 30 SATA_TXN2 R615 4.99/F_4 SATA_TXN2_C AC12 SATA_TX2N IDE_D1/GPIO16 AD23 T243 IS MANDATORY ATA 66/100/133 E-SATA SATA_RXN2_C AE12 IDE_D2/GPIO17 AE22 AC22 T244 30 SATA_RXN2 SATA_RX2N IDE_D3/GPIO18 T245 SATA_RXP2_C AD12 AD21 30 SATA_RXP2 SATA_RX2P IDE_D4/GPIO19 T246 IDE_D5/GPIO20 AE20 T247 SATA_TXP3_C AD13 AB20 T197 T248 SERIAL ATA SATA_TXN3_C SATA_TX3P IDE_D6/GPIO21 T198 AE13 SATA_TX3N IDE_D7/GPIO22 AD19 T249 IDE_D8/GPIO23 AE19 T250 SATA_RXN3_C AB14 AC20 T88 SATA_RX3N IDE_D9/GPIO24 T251 SATA_RXP3_C AC14 AD20 T85 SATA_RX3P IDE_D10/GPIO25 T252 IDE_D11/GPIO26 AE21 T253 SATA_TXP4_C AE14 AB22 T227 SATA_TX4P IDE_D12/GPIO27 T254 SATA_TXN4_C AD14 AD22 T228 SATA_TX4N IDE_D13/GPIO28 T255 IDE_D14/GPIO29 AE23 T256 SATA_RXN4_C AD15 AC23 T229 SATA_RX4N IDE_D15/GPIO30 T257 SATA PORT 4,5 are T230 SATA_RXP4_C AE15 SATA_RX4P only support IDE SATA_TXP5_C AB16 T89 SATA_TX5P mode T87 SATA_TXN5_C AC16 SATA_TX5N SPI_DI/GPIO12 G6 T100 SATA_RXN5_C AE16 D2 T86 SATA_RX5N SPI_DO/GPIO11 T219 SATA_RXP5_C AD16 D1 T82 SATA_RX5P SPI_CLK/GPIO47 T218 R361 F4 SPI ROM SPI_HOLD#/GPIO31 T111C R264 1K/F_4 SATA_RBIAS_PN V12 F3 C SATA_CAL SPI_CS#/GPIO32 T220 SATA_X1 Y12 U15 R265 0_4 SATA_X1 LAN_RST#/GPIO13 BT_OFF# 30 J1 ROM_RST# ROM_RST#/GPIO14 T215 PLACE SATA_CAL SATA_X2 AA12 SATA_X2 SB_FANOUT0 M8 RES VERY CLOSE SB_SATA_LED# W11 FANOUT0/GPIO3 M5 SB_FANOUT1 T96 SATA_ACT#/GPIO67 FANOUT1/GPIO48 T97 TO BALL OF SB700 PLVDD_SATA-- FANOUT2/GPIO49 M7 CHIPSET_PCIE_SLOW_SB# 2 SI-2 modified -- SB SATA PLL +3V R382 10K/F_4 internal pull Hi to 3VS5 NOTE: AA11 P5 SB_FANTACH0 SATA PWR POWER +1.2V_PLLVDD_SATA PLLVDD_SATA FANIN0/GPIO50 SB_FANTACH1 T104 , modified to same power FANIN1/GPIO51 P8 T92 R361 IS 1K 1% FOR 25MHz +3V_XTLVDD_SATA W12 R8 PORT_80_PWR_DWN rail with SB XTLVDD_SATA FANIN2/GPIO52 T95 XTAL, 4.99K 1% FOR 100MHz XTLVDD_SATA-- SATA C6 TEMP_COMM TEMP_COMM T208 INTERNAL CLOCK crystal power TEMPIN0/GPIO61 B6 TEMPIN0 T202 +3VS5 R221 10K/F_4 BOARD_ID0 R229 *10K/F_4 A6 TEMPIN1 TEMPIN1/GPIO62 T203 HW MONITOR A5 MB_THRMDA_SB TEMPIN2/GPIO63 T207 C534 B5 R247 *10K/F_4 BOARD_ID1 R248 *10K/F_4 TEMPIN3/TALERT#/GPIO64 T259 SATA_X1 Del R220 for TP on PV VIN0/GPIO53 A4 ACCLED_EN 29 27P/50V_4 B4 R216 0_4 R225 *10K/F_4 BOARD_ID2 R228 *10K/F_4 VIN1/GPIO54 BT_COMBO_EN# 36 2 Y4 C4 R262 VIN2/GPIO55 BOARD_ID0 VIN3/GPIO56 D4 Del WAN off# 25MHZ 10M_6 D5 BOARD_ID1 and R597 on R230 *10K/F_4 BOARD_ID3 R242 *10K/F_4 VIN4/GPIO57 BOARD_ID2 D6 PV 1 C517 VIN5/GPIO58 BOARD_ID3 VIN6/GPIO59 A7 SATA_X2 B7 BOARD_ID4 R596 *10K/F_4 BOARD_ID4 R600 *10K/F_4 VIN7/GPIO60 27P/50V_4 +3VS5B 5mA SI-2 modified -- for fix +3V power leakage in S5 mode B F6 +3V_VDD_HWM L52 0_6 AVDD SB700 AVSS G7 C571 C572 AVDD--H/W monitor +3V *0.1U/10V_4 *2.2U/6.3V_6 Analog power ID4 ID3 ID2 ID1 ID0 C655 +1.2V ( 1.2V @ 60mA) +1.2V_PLLVDD_SATA 0.1U/10V_4 77mA X X X 0 0 UMA U20 L47 5 TC7SH08FU BLM18PG181SN1D(180,1.5A)_6 2 SB_SATA_LED# 29 SATA_LED# 4 C524 C550 X X X 0 1 discrete 1 1U/10V_4 0.1U/10V_4 3 X X X X X +3V 1mA ( 3.3V @ 1.2mA) +3V_XTLVDD_SATA X X X X X SI-2 modified for SATA LED fail issue L46 BLM18PG181SN1D(180,1.5A)_6 C539 1U/10V_4A A Place near ball PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev Custom 1A SB700-ACPI/GPIO/USB 2/4 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 14 of 45 5 4 3 2 1
    • 5 4 3 2 1 PLACE ALL THE DECOUPLING CAPS ON For SB700 issue(6/22) A1-1 chip bug 23 THIS SHEET CLOSE TO SB AS POSSIBLE. Del R285 for TP on PV R590 use A1-2 chip can remove VDD-- S/B CORE power 2 1 *0_8 +1.2V_S5 U37C +1.2V_VCC_SB_R VDDQ--3.3V I/O power 0.8A SB700 604mA R198 +3V L9 VDDQ_1 VDD_1 L15 2 1 0_8 +1.2V U37E M9 VDDQ_2 Part 3 of 5 VDD_2 M12 1 T15 VDDQ_3 VDD_3 M14 SB700 1 1 1 1 1 1 1 1 1 1 1 1 C576 U9 N13 A2 CORE S0 C557 C560 C573 C565 C547 C553 C574 VDDQ_4 VDD_4 C533 C545 C538 C532 C467 VSS_1 U16 P12 A25 PCI/GPIO I/O 100U/6.3V_3528 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 VDDQ_5 VDD_5 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 VSS_2 2 U17 P14 B1 2 2 2 2 2 2 2 2 2 2 2 2D VDDQ_6 VDD_6 VSS_3 D V8 VDDQ_7 VDD_7 R11 VSS_4 D7 W7 VDDQ_8 VDD_8 R15 T10 AVSS_SATA_1 VSS_5 F20 Y6 VDDQ_9 VDD_9 T16 U10 AVSS_SATA_2 VSS_6 G19 AA4 VDDQ_10 U11 AVSS_SATA_3 VSS_7 H8 AB5 VDDQ_11 U12 AVSS_SATA_4 VSS_8 K9 1.8V : FLASH MEMORY MODE(DEFAULT) AB21 VDDQ_12 CKVDD_1.2V-- Internal V11 AVSS_SATA_5 VSS_9 K11 3.3V: IDE MODE +VDD33_18 +1.2V_CKVDD clock Generator I/O V14 AVSS_SATA_6 VSS_10 K16 power W9 AVSS_SATA_7 VSS_11 L4 VDD33_18--3.3V IDE I/O power Y9 AVSS_SATA_8 VSS_12 L7 1.8V flash memory I/O power 0.45A 286mA Y11 AVSS_SATA_9 VSS_13 L10 +3V R226 2 1 0_8 Y20 L21 L43 +1.2V Y14 L11 VDD33_18_1 CKVDD_1.2V_1 AVSS_SATA_10 VSS_14 AA21 L22 Y17 L12 IDE/FLSH I/O CLKGEN I/O R751 2 VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_11 VSS_15 +1.8V 1 *0_8 AA22 VDD33_18_3 CKVDD_1.2V_3 L24 BLM18PG181SN1D(180,1.5A)_6 AA9 AVSS_SATA_12 VSS_16 L14 1 1 1 1 1 1 1 1 1 AE25 VDD33_18_4 CKVDD_1.2V_4 L25 AB9 AVSS_SATA_13 VSS_17 L16 C486 C501 C487 C497 C488 C505 C489 C475 C478 AB11 M6 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 2.2U/6.3V_6 AVSS_SATA_14 VSS_18 AB13 M10 2 2 2 2 2 2 2 2 2 2.2U/6.3V_6 0.1U/50V_6 0.1U/50V_6 AVSS_SATA_15 VSS_19 AB15 AVSS_SATA_16 VSS_20 M11 AB17 AVSS_SATA_17 VSS_21 M13 AC8 AVSS_SATA_18 VSS_22 M15 AD8 AVSS_SATA_19 VSS_23 N4 AE8 N12 +1.2V_PCIE_VDDR POWER AVSS_SATA_20 VSS_24 VSS_25 N14 VSS_26 P6 PCIE_VDDR--PCIE I/O power 844mA VSS_27 P9 +1.2V L89 P18 PCIE_VDDR_1 S5_3.3--3.3v standby power VSS_28 P10 P19 +3VALW_R A15 P11 BLM18PG181SN1D(180,1.5A)_6 PCIE_VDDR_2 R604 0_6 AVSS_USB_1 VSS_29 A-LINK I/O P20 PCIE_VDDR_3 0.01A B15 AVSS_USB_2 VSS_30 P13 1 1 1 1 1 1 P21 PCIE_VDDR_4 S5_3.3V_1 A17 2 1 +3VS5 C14 AVSS_USB_3 VSS_31 P15 C477 C502 C484 C504 C492 C483 R22 A24 D8 R1 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 PCIE_VDDR_5 S5_3.3V_2 Change to 0603 AVSS_USB_4 VSS_32C R24 B17 D9 R2 C 2 2 2 2 2 2 PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_5 VSS_33 1 1 1 3.3V_S5 I/O R25 PCIE_VDDR_7 S5_3.3V_4 J4 D11 AVSS_USB_6 VSS_34 R4 J5 C875 C570 C876 D13 R9 S5_3.3V_5 AVSS_USB_7 VSS_35 GROUND L1 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8 D14 R10 2 2 2 S5_3.3V_6 AVSS_USB_8 VSS_36 S5_3.3V_7 L2 D15 AVSS_USB_9 VSS_37 R12 +1.2V_AVDD_SATA E15 R14 AVSS_USB_10 VSS_38 AVDD_SATA--SATA phy power 0.2A F12 AVSS_USB_11 VSS_39 T11 +1.2V L92 AA14 AVDD_SATA_1 S5_1.2V--1.2V standby power F14 AVSS_USB_12 VSS_40 T12 AB18 AVDD_SATA_4 G9 AVSS_USB_13 VSS_41 T14 BLM18PG181SN1D(180,1.5A)_6 AA15 0.22A H9 U4 SATA I/O AVDD_SATA_2 AVSS_USB_14 VSS_42 1 1 1 1 1 AA17 G2 +1.2V_S5 H17 U14 CORE S5 C888 C880 C884 C883 C881 AVDD_SATA_3 S5_1.2V_1 AVSS_USB_15 VSS_43 AC18 AVDD_SATA_5 S5_1.2V_2 G4 J9 AVSS_USB_16 VSS_44 V6 1 1 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 AD17 Del R661 J11 Y21 2 2 2 2 2 AVDD_SATA_6 C903 C901 AVSS_USB_17 VSS_45 AE17 AVDD_SATA_7 J12 AVSS_USB_18 VSS_46 AB1 0.2A 0.1U/10V_4 0.1U/10V_4 for TP on J14 AB19 2 2 AVSS_USB_19 VSS_47 USB_PHY_1.2V_1 A10 +1.2V_USB_PHY_R PV J15 AVSS_USB_20 VSS_48 AB25 USB_PHY_1.2V_2 B10 K10 AVSS_USB_21 VSS_49 AE1 K12 AVSS_USB_22 VSS_50 AE24 K14 AVSS_USB_23 +3V_AVDD_USB K15 AVSS_USB_24 AVDDTX--USB Phy PCIE_CK_VSS_9 P23 For support USB wakeup-->3V_S5 Analog I/O power V5_VREF--PCI 5V TOLERANCE PCIE_CK_VSS_10 R16 L91 0.2A +5V_VREF 4mA R621 PCIE_CK_VSS_11 R19 +3VS5 A16 AVDDTX_0 V5_VREF AE7 1 2 1K/F_4 +5V PCIE_CK_VSS_12 T17 B16 AVDDTX_1 PCIE_CK_VSS_13 U18 BLM18PG181SN1D(180,1.5A)_6 C16 J16 +3V_AVDDCK 7mA H18 U20 AVDDTX_2 AVDDCK_3.3V PCIE_CK_VSS_1 PCIE_CK_VSS_14 1 1 1 1 D16 AVDDTX_3 1 2 +3V J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18 1 C889 C882 C878 C886 D17 PLL K17 +1.2V_AVDDCK 44mA D36 J22 V20 10U/6.3V_8 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 AVDDTX_4 AVDDCK_1.2V C898 CH501H-40PT PCIE_CK_VSS_3 PCIE_CK_VSS_16 E17 K25 V21 2 2 2 2 AVDDTX_5 PCIE_CK_VSS_4 PCIE_CK_VSS_17 USB I/O F15 E9 +3V_AVDDC 1U/10V_4 M16 W19 2B AVDDRX_0 AVDDC PCIE_CK_VSS_5 PCIE_CK_VSS_18 B F17 AVDDRX_1 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22 F18 AVDDRX_2 16mA M21 PCIE_CK_VSS_7 PCIE_CK_VSS_20 W24 G15 AVDDRX_3 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25 G17 AVDDRX_4 G18 AVDDRX_5 F9 AVSSC AVSSCK L17 Part 5 of 5 1 1 1 1 1 1 1 SB700 SB700 C528 C537 C885 C511 C510 C879 C536 1U/10V_4 1U/10V_4 1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 2 2 2 2 2 2 2 +3VS5 +3V_AVDDC +1.2V_S5 +1.2V_USB_PHY_R AVDDC--USB Analog PLL power L50 R616 0_6 USB_PHY_1.2V--USB Phy BLM18PG181SN1D(180,1.5A)_6 2 1 digital power 1 1 C546 C540 1 1 1 0.1U/10V_4 10U/6.3V_8 2 2 C890 C891 C892 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8 2 2 2A +1.2V A +1.2V_AVDDCK +3V +3V_AVDDCK AVDDCK_1.2--USB Phy AVDDCK_3.3--Analog digital power system PLL power L45 L48 BLM18PG181SN1D(180,1.5A)_6 BLM18PG181SN1D(180,1.5A)_6 PROJECT : QT8 1 1 C509 C516 2.2U/6.3V_6 2.2U/6.3V_6 Quanta Computer Inc. 2 2 Size Document Number Rev Custom 1A SB700-PWR/DECOUPLING 4/4 NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 15 of 45 5 4 3 2 1
    • 5 4 3 2 1 OVERLAP COMMON PADS WHERE POSSIBLE FOR DUAL-OP RESISTORS. 16 It must ready refore RSMRST# REQUIRED STRAPS +3VS5 1D +3V +3V +3VS5 SI-2 Modified D -R599 change from R599 2.2K_4 10kohm to 2.2kohm for fix system can 2 1 1 1 intermal have pull not boot Hi 10K , confirm AMD R655 R656 R300 10K/F_4 10K/F_4 *10K/F_4 ward this pull Hi 13 SB_GPIO17 not need 13 SB_GPIO16 2 2 2 12 PCI_CLK_TPM 12 PCI_CLK4 12 LPC_CLK0 12 RTC_CLK 1 1 12 PCI_CLK3 12 PCI_CLK5 12 LPC_CLK1 13 ACZ_RST# GPIO16 R598 R255 *2.2K_4 2.2K_4 GPIO17 2 2 1 1 1 1 1 1 1 R659 10K/F_4 R291 R658 R654 R657 R231 R595 10K/F_4 TYPE GPIO16 GPIO17 2 10K/F_4 *10K/F_4 *10K/F_4 10K/F_4 10K/F_4 2 2 2 2 2 2 FWH L : 2.2K L : 2.2K pull down pull down PCI_CLK_TPM PCI_CLK3 PCI_CLK4 PCI_CLK5 LPC_CLK0 LPC_CLK1 RTC_CLK AZ_RST# LPC NC L : 2.2KC pull down C PULL BOOTFAIL USE RESERVED RESERVED IMC CLKGEN INTERNAL ENABLE PCI HIGH TIMER DEBUG ENABLED ENABLED RTC ROM BOOT L : 2.2K ENABLED STRAPS SPI NC pull down DEFAULT EXT. RTC PULL BOOTFAIL IGNORE IMC CLKGEN (PD on X1, DISABLE PCI LOW TIMER DEBUG DISABLED DISABLED apply ROM BOOT RSVD NC NC DISABLED STRAPS 32KHz to DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK) NB_PWRGD_IN: RS780/RX780 = 1.8V; RS740 = 3.3V DEBUG STRAPS Do NOT share it with SB_PWRGD when use Internal Clk Gen (Need SB PLL initialize firstly) SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23] SI-2 modified -- confirm AMD R563 need to stuff +3VS5 R282 10K/F_4 R278 0_4 SB_PWRGD_IN SB_PWRGD_IN 13 SI-2 modified -- remove +3V pull Hi resistor . C564 *2.2U/6.3V_6 +1.8V 12 AD28 +1.8VB 12 AD27 B 12 AD26 12 AD25 U14 R269 12 AD24 1 5 C549 *0.1U/10V_4 10K/F_4 D18 CH501H-40PT NC VCC RX780,RS780 12 AD23 40 VRM_PWRGD 1 2 2 A 1 1 1 1 1 1 3 4 R273 *33_4 NB_PWRGD_IN GND Y NB_PWRGD_IN 10 R651 R636 R652 R638 R637 R653 *2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 Use 2.2K PD. D19 CH501H-40PT *NL17SZ17DFT2G 1 2 SOT-353 5,35 ECPWROK 2 2 2 2 2 2 R266 *10K/F_4 +1.8V NB/SB POWER GOOD CIRCUIT 0_4 R272 WD_PWRGD 13 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED PULL LONG PLL BCLK PLL PCIE STRAPS HIGH RESET DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM AL17SZ17000 IC(5P) NL17SZ17DFT2G(SOT-353) SOT-353 LOW SHORT PCI PLL ACPI PLL PCIE STRAPSA RESET BCLK ALUC1G17000 IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5) SOT23-5 A PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev Custom 1A SB700-STRAPS NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 16 of 45 5 4 3 2 1
    • 5 4 3 2 1 IC CTRL(632P) 216-0707001-00(BGA) VGA P/N : AJ070700T00 17 PART 1 OF 6 2.5Gb/s bit rate POWER PEG_TX0 AC30 AA28 C_PEG_RXP0 C163 0.1U/10V_4 +PCIE_VDDR=1.2V 9 PEG_TX0 PCIE_RX0P PCIE_TX0P PEG_RX0 9 PEG_TX#0 AC31 AA27 C_PEG_RXN0 C156 0.1U/10V_4D 9 PEG_TX#0 PCIE_RX0N PCIE_TX0N PEG_RX#0 9 +VDD_MEM1.8V=1.8V D +VGA_CORE=1.0~1.1V - M62S,M71S 9 PEG_TX1 PEG_TX1 AC29 PCIE_RX1P P PCIE_TX1P AA25 C_PEG_RXP1 C167 0.1U/10V_4 PEG_RX1 9 0.95~1.1V - M72S PEG_TX#1 AB29 AA24 C_PEG_RXN1 C170 0.1U/10V_4 9 PEG_TX#1 PCIE_RX1N C PCIE_TX1N PEG_RX#1 9 I PEG_TX2 AB31 Y28 C_PEG_RXP2 C180 0.1U/10V_4 9 PEG_TX2 PEG_TX#2 AB30 PCIE_RX2P - PCIE_TX2P Y27 C_PEG_RXN2 C196 0.1U/10V_4 PEG_RX2 9 9 PEG_TX#2 PCIE_RX2N PCIE_TX2N PEG_RX#2 9 E PEG_TX3 AA31 X Y25 C_PEG_RXP3 C164 0.1U/10V_4 9 PEG_TX3 PCIE_RX3P PCIE_TX3P PEG_RX3 9 9 PEG_TX#3 PEG_TX#3 AA30 PCIE_RX3N P PCIE_TX3N Y24 C_PEG_RXN3 C157 0.1U/10V_4 PEG_RX#3 9 R 9 PEG_TX4 PEG_TX4 W30 PCIE_RX4P E PCIE_TX4P V28 C_PEG_RXP4 C218 0.1U/10V_4 PEG_RX4 9 PEG_TX#4 C_PEG_RXN4 C204 0.1U/10V_4 9 PEG_TX#4 W31 PCIE_RX4N S PCIE_TX4N V27 PEG_RX#4 9 S PEG_TX5 W29 V25 C_PEG_RXP5 C203 0.1U/10V_4 9 PEG_TX5 PCIE_RX5P PCIE_TX5P PEG_RX5 9 PEG_TX#5 V29 V24 C_PEG_RXN5 C187 0.1U/10V_4 9 PEG_TX#5 PEG_RX#5 9 PCIE_RX5N I PCIE_TX5N PEG_TX6 N C_PEG_RXP6 C220 0.1U/10V_4 9 PEG_TX6 V31 T28 PEG_RX6 9 9 PEG_TX#6 PEG_TX#6 V30 PCIE_RX6P T PCIE_TX6P T27 C_PEG_RXN6 C224 0.1U/10V_4 PEG_RX#6 9 PCIE_RX6N PCIE_TX6N E 9 PEG_TX7 PEG_TX7 U31 R T25 C_PEG_RXP7 C243 0.1U/10V_4 PEG_RX7 9 PCIE_RX7P PCIE_TX7P 9 PEG_TX#7 PEG_TX#7 U30 PCIE_RX7N F PCIE_TX7N T24 C_PEG_RXN7 C252 0.1U/10V_4 PEG_RX#7 9C A C 9 PEG_TX8 PEG_TX8 PEG_TX#8 P30 PCIE_RX8P C PCIE_TX8P P28 C_PEG_RXP8 C_PEG_RXN8 C276 0.1U/10V_4 PEG_RX8 9 P31 P27 C268 0.1U/10V_4 9 PEG_TX#8 PCIE_RX8N E PCIE_TX8N PEG_RX#8 9 PEG_TX9 P29 P25 C_PEG_RXP9 C259 0.1U/10V_4 9 PEG_TX9 PCIE_RX9P PCIE_TX9P PEG_RX9 9 PEG_TX#9 N29 P24 C_PEG_RXN9 C246 0.1U/10V_4 9 PEG_TX#9 PCIE_RX9N PCIE_TX9N PEG_RX#9 9 PEG_TX10 N31 M28 C_PEG_RXP10 C289 0.1U/10V_4 9 PEG_TX10 PCIE_RX10P PCIE_TX10P PEG_RX10 9 PEG_TX#10 N30 M27 C_PEG_RXN10 C277 0.1U/10V_4 9 PEG_TX#10 PCIE_RX10N PCIE_TX10N PEG_RX#10 9 PEG_TX11 M31 M25 C_PEG_RXP11 C290 0.1U/10V_4 9 PEG_TX11 PCIE_RX11P PCIE_TX11P PEG_RX11 9 PEG_TX#11 M30 M24 C_PEG_RXN11 C296 0.1U/10V_4 9 PEG_TX#11 PCIE_RX11N PCIE_TX11N PEG_RX#11 9 PEG_TX12 K30 L28 C_PEG_RXP12 C288 0.1U/10V_4 9 PEG_TX12 PCIE_RX12P PCIE_TX12P PEG_RX12 9 PEG_TX#12 K31 L27 C_PEG_RXN12 C295 0.1U/10V_4 9 PEG_TX#12 PCIE_RX12N PCIE_TX12N PEG_RX#12 9 PEG_TX13 K29 L25 C_PEG_RXP13 C330 0.1U/10V_4 9 PEG_TX13 PCIE_RX13P PCIE_TX13P PEG_RX13 9 PEG_TX#13 J29 L24 C_PEG_RXN13 C324 0.1U/10V_4 9 PEG_TX#13 PCIE_RX13N PCIE_TX13N PEG_RX#13 9 PEG_TX14 J31 J28 C_PEG_RXP14 C325 0.1U/10V_4 9 PEG_TX14 PCIE_RX14P PCIE_TX14P PEG_RX14 9 PEG_TX#14 J30 J27 C_PEG_RXN14 C331 0.1U/10V_4 9 PEG_TX#14 PCIE_RX14N PCIE_TX14N PEG_RX#14 9 PEG_TX15 H31 G28 C_PEG_RXP15 C304 0.1U/10V_4B 9 PEG_TX15 PCIE_RX15P PCIE_TX15P PEG_RX15 9 B PEG_TX#15 H30 G27 C_PEG_RXN15 C316 0.1U/10V_4 9 PEG_TX#15 PCIE_RX15N PCIE_TX15N PEG_RX#15 9 Clock Calibration EXT_GFX_CLKP AD29 2 EXT_GFX_CLKP PCIE_REFCLKP EXT_GFX_CLKN AD30 AF25 M72_PCIE_CALRN R74 2K/F_4 +1.1V_PCIE_VDDC 2 EXT_GFX_CLKN PCIE_REFCLKN PCIE_CALRN 100MHz (+/-300ppm) input frequency, SM BUS PCIE_CALRP AE25 M72_PCIE_CALRP R70 1.27K/F_4 0-0.7V single-ended swing AC28 NC_SMBCLK AC27 NC_SMBDATA 1.27K for M82-S NC_1 AE23 R71 0_4 AG25 AH30 12 PCIE_RST# PERSTB NC_2 M72-S/M82-S U29A VGA Core BPP VGA Core VDDC +1.8V PCIE_VDDRA A +1.8V PCIE_PVDD +1.8V VDDR1 PROJECT : QT8 Quanta Computer Inc. 3.3V_Delay VDDR3 Size Document Number Rev 20ms 20ms Custom M7X/M8X_PCIE_Interface 1A NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 17 of 45 5 4 3 2 1
    • 5 4 3 2 1 U29B R100 R522 1K/F_4 10K/F_4 GPIO_24_JMODE ROMCS# NA- M62S,M71S PD 1K- M72S AJ4 AJ5 AL5 AK5 TXCM_DPA0P TXCP_DPA0N TX0M_DPA1P TX0P_DPA1N PART 2 OF 6 INTEGRATED TXCM_DPB0P TMDS/DP PORT TXCP_DPB0N TX0M_DPB1P TX0P_DPB1N AK9 AL9 AJ9 AJ10 TXC_HDMI_L- TXC_HDMI_L+ TX0_HDMI_L- TX0_HDMI_L+ Remove 180R SHUNT RESISTOR for M82-S from AMD Jackson TXC_HDMI_L- 23 TXC_HDMI_L+ 23 TX0_HDMI_L- 23 TX0_HDMI_L+ 23 18 AL6 TX1M_DPA2P TX1M_DPB2P AL10 TX1_HDMI_L- confirm TX1_HDMI_L- 23 GPIO22(ROMCS#) AK6 AK10 TX1_HDMI_L+ TX1P_DPA2N TX1P_DPB2N TX1_HDMI_L+ 23 PD without external VBIOS ROM AK8 AL11 TX2_HDMI_L- TX2M_DPA3P TX2M_DPB3P TX2_HDMI_L- 23 AL8 AK11 TX2_HDMI_L+ TX2P_DPA3N TX2P_DPB3N TX2_HDMI_L+ 23 NA - M64/M62, M71 R87 10K/F_4 BBEN AL7 +1.8V_TPVDD DPA_PVDD / DPB_PVDD BBEN- M66 DPA_PVDD +1.8V_TPVDD BBEN(10K PD)- M76 AD9 DVALID DPA_PVSS AK7 DP/TMDS PLL Power (Link A) PSYNC DPB_PVDD DP/TMDS PLL Power (Link B)D AE7 AE11 DPB_PVDD D 19 PSYNC PSYNC_NEW DPB_PVDD AF11 1.8 V ± 3% R95 10K/F_4 TEMP_FAIL DPB_PVSS NA- M62S,M71S PU to 3.3V- M72S AK4 DVPCNTL_MVP_0 DPA_VDDR_1 AJ12 DPA_B_VDDR DPA_B_VDDR DPA_VDDR / DPB_VDDR AL3 DVPCNTL_MVP_1 DPA_VDDR_2 AJ13 DP/TMDS Transmitter Power (Link A) DPA_B_VDDR DP/TMDS Transmitter Power (Link B) V2 AK13 DPA_B_VDDR V1 DVPCNTL_0 DPB_VDDR_1 AL13 1.1 V ± 3% DVPCNTL_1 DPB_VDDR_2 MEM_ID[3:0] Vendor Type Vendor P/N W3 DVPCNTL_2 DPB_VSSR_5 AL12 0000 Qimonda (Infineon) 16*16 HYB18T256161BF-25 W1 DVPCLK DPB_VSSR_4 AK12 ENABLE HD AUDIO ( M8X-M ) 0001 Qimonda (Infineon) 32*16-500MHZ HYB18T512161B2F-20 DPB_VSSR_3 AJ11 0010 Hynix 16*16 HY5PS561621AFP-25 Y1 DVPDATA_0 DPB_VSSR_2 AH9 0011 Hynix 32*16-500MHZ H5PS5162FFR-20L Y2 DVPDATA_1 DPB_VSSR_1 AH11 R488 *0_4 VIP_3 VIP_3 19 0100 Samsung 16*16 K4N56163QG-ZC25 Y3 DVPDATA_2 0101 Samsung 32*16-500MHZ K4N51163QG-HC20 AA2 DVPDATA_3 DPA_VSSR_5 AJ8 0110 Reserved AA3 DVPDATA_4 DPA_VSSR_4 AF7 M82-S 0_4 0111 Reserved AB1 DVPDATA_5 DPA_VSSR_3 AG7 R476 1000 Reserved AB2 DVPDATA_6 DPA_VSSR_2 AJ7 DPA_VSSR_2 1001 Reserved AB3 DVPDATA_7 DPA_VSSR_1 AH7 1010 Reserved AC1 DVPDATA_8 150 OHM 1011 Reserved AC3 DVPDATA_9 DP_CALR AG11 TMDS_HPD TMDS_HPD 10,23 1100 Reserved AD1 DVPDATA_10 1101 Reserved AD2 DVPDATA_11 EXT TMDS HPD1 AA8 TMDS_HPD R65 *100K/F_4 1110 Reserved AD3 DVPDATA_12 DVO L_CRT_R R463 150/F_4 1111 Reserved AF3 DVPDATA_13 R AL28 L_CRT_R R449 0_4 CRT_R 10,24 Del R481, R482, R483, AG3 AK28 AH3 DVPDATA_14 DVPDATA_15 RB L_CRT_G R462 150/F_4 R68, R464, R486 for TP AG1 AL27 L_CRT_G R448 0_4 AH2 DVPDATA_16 G AK27 CRT_G 10,24 on PV +VDDR4 DVPDATA_17 GB PWRCNTL1 PWRCNTL0 V-CORE Memory ID AH1 DVPDATA_18 L_CRT_B R461 150/F_4 AJ3 AL26 L_CRT_B R447 0_4 R495 DVPDATA_19 B CRT_B 10,24 10K/F_4 MEM_ID0 AJ1 AK26 R496 *10K/F_4 MEM_ID1 DVPDATA_20 DAC1 / CRT BB AJ2 DVPDATA_21 H 0 0 1.1V R493 R492 *10K/F_4 *10K/F_4 MEM_ID2 MEM_ID3 AK2 AK3 DVPDATA_22 DVPDATA_23 HSYNC VSYNC AK29 AK30 HSYNC_COM 10,19,24 VSYNC_COM 10,19,24C AJ28 R484 499/F_4 C RSET M 0 1 1.0V 19 19 GPIO0 GPIO1 GPIO0 GPIO1 Y4 V3 GPIO_0 GPIO_1 AVDD AL29 +1.8V_A2VDD_Q +1.8V_A2VDD_Q AVDD GPIO2 V4 C111 DAC1 Analog Power T151 GPIO_2 GPIO3 V5 GENERAL AH28 T18 GPIO_3 AVSSQ Dedicated power for DAC1. M 1 0 1.0V 19 T152 GPIO5 GPIO4 GPIO5 U3 U2 GPIO_4 GPIO_5 PURPOSE I/O VDD1DI AJ27 +VDDD1 +VDDD1 0.1U/10V_4 1.8 V ± 5% T4 C127 GPIO_6 10,23 LVDS_BLON R93 0_4 EXT_LVDS_BLON T5 GPIO_7_BLON VSS1DI AJ26 VDD1DI +1.8V_A2VDD_Q L 1 1 0.9V 19 19 GPIO8 GPIO9 GPIO8 GPIO9 T7 T8 GPIO_8_ROMSO GPIO_9_ROMSI R2 AL17 0.1U/10V_4 DAC1 Digital Power. 1.8 V ± 5% 1.8V(65mA) GPIO10 R1 AK17 T153 GPIO_10_ROMSCK R2B 19 GPIO11 GPIO11 R2 +1.8V_A2VDD_Q L16 GPIO_11 +1.8V 19 GPIO12 GPIO12 R3 GPIO_12 G2 AL15 A2VDD BBEN BBP 19 GPIO13 T154 GPIO13 HDMI_HP2 P1 P3 GPIO_13 GPIO_14_HPD2 G2B AK15 DAC2 Analog Power. 3.3 V ± 5% C129 C168 BLM18PG181SN1D(180,1.5A)_6 C98 42 GFX_CORE_CNTRL0 R526 0_4 N1 AL14 10U/6.3V_8 GPIO_15_PWRCNTL0 DAC2 (TV/CRT2) B2 2 OSC_SPREAD OSC_SPREAD N2 GPIO_16_SSIN B2B AK14 A2VDDQ 0.1U/10V_4 1U/10V_4 L 0 V-CORE T37 HPD3 VGA_ALERT P4 P7 GPIO_17_THERMAL_INT GPIO_18_HPD3 C AJ17 Del R470, R478, DAC2 Band Gap (clean) power supply. 1.8 V ± 5% 5 TEMP_FAIL TEMP_FAIL P8 R450, R472, R471, R99 0_4 PWRCNTL_1 GPIO_19_CTFB 42 GFX_CORE_CNTRL1 P5 GPIO_20_PWRCNTL1 Y AJ15 R469, R451 for TP on VDD2DI DPB_PVDD H 1 +1.8V 20 BBEN BBEN ROMCS# V7 N3 GPIO_21_BB_EN GPIO_22_ROMCSB COMP AJ14 PV DAC2 Digital Power. 1.8V(20mA) R91 10K/F_4 GPIO_23_CLKREQb Y5 DPB_PVDD L24 +3V GPIO_24_JMODE GPIO_23_CLKREQB DAC2_VSY 1.8 V ± 5% C165 C182 +1.8V M4 GPIO_24_JMODE V2SYNC AE16 T13 DPLL_PVDD BLM18PG181SN1D(180,1.5A)_6 1.8V(40mA) T36 M5 GPIO_25_TDI H2SYNC AF16 DAC2_HSY BLM18PG181SN1D(180,1.5A)_6 Phase Lock Loop +1.8V M7 T10 0.1U/10V_4 1000P/50V_4 C145 T34 GPIO_26_TCK L17 M8 AH14 10U/6.3V_8 Power T35 GPIO_27_TMS A2VDD +3V_DELAY T38 L8 Dedicated analog C114 C147 GPIO_28_TDO AH16 +1.8V_A2VDD_Q C136 Del L25 for A2VDDQ +1.8V_A2VDD_Q power pin for 10U/6.3V_8 0.1U/10V_4 Y8 GEN_A 0.1U/10V_4 TP on PV +VDDD1 display PLLs. +1.8V 1.8V+R6043(249R)=1.8V/3=0.6V Y7 GEN_B A2VSSQ AG16 1.8 V ± 3% V8 GEN_C GENERICC AH6 AF18 +VDDD1 T123 GEN_D_HPD4 VDD2DI R75 499/F_4 AG6 GEN_E C171 VSS2DI AE18B BLM18PG181SN1D(180,1.5A)_6 1.8V(40mA) R76 249/F_4 +0.6V_M72_VREFG AC11 B VREFG PCIE_PVDD +1.8V R2SET AG14 R69 715/F_4 0.1U/10V_4 PCI-E PLL power. L71 +1.8V_DPLL_PVDD AH12 1.8 V ± 5% C743 C747 C746 DPLL_PVSS DPLL_PVDD AG12 DPLL_PVSS SCL AA5 EDIDCLK 10,23 AA4 Del R84, R85, +VDDD1 10U/6.3V_8 1U/10V_4 0.1U/10V_4 +1.8V_VPCIE_PVDD AH31 SDA EDIDDATA 10,23 PCIE_PVDD R466, R467 1.8V(100mA) SERIAL AJ29 BUSES DDC1DATA DDCDATA 10,24 for TP on PV BLM18PG181SN1D(180,1.5A)_6 VDDC(345mA) AH29 +VDDD1 L15 DDC1CLK DDCCLK 10,24 +1.8V +VGA_CORE +VGACORE_MPVDD A9 PLL & R511 *4.7K_4 +3V_DELAY L79 MPVSS MPVDD XTAL VTHM_DAT BLM18PG181SN1D(180,1.5A)_6 B9 MPVSS DDC2DATA AC5 MPVDD C822 C823 DDC2CLK AC4 VTHM_CLK C110 C135 C97 Memory Phase Lock Loop Power 10U/6.3V_8 C824 +1.1V_DPLL_VDDC AE12 R510 *4.7K_4 +3V_DELAY 10U/6.3V_8 1U/10V_4 0.1U/10V_4 DPLL_VDDC 0.1U/10V_4 1U/10V_4 Same as VDDC DDC3DATA_DP3_AUXN AF4 T12 2 EVGA-XTALI EVGA-XTALI AJ31 XTALIN DDC3CLK_DP3_AUXP AH4 T11 DDC 3V tolerance --DDC1,DDC2,SDA/SCL EVGA-XTALO AJ30 AF9 BLM18PG181SN1D(180,1.5A)_6 XTALOUT DDC4DATA_DP4_AUXN HDMI_SDA 23 DDC 5V tolerance 1.1V(100mA) AG9 HDMI_SCL 23 L18 DDC4CLK_DP4_AUXP --DDC3,DDC4 +1.8V_TPVDD 1.8V(20mA) +1.1V TS_FDO AE14 C106 C169 C161 1K/F_4 R67 AH26 TEST +1.8V_TPVDD L20 +1.8V 10U/6.3V_8 1U/10V_4 0.1U/10V_4 TESTEN THERMAL VGATHRM+ C113 C108 DPLUS AE5 AD12 AE4 VGATHRM- BLM18PG181SN1D(180,1.5A)_6 PLLTEST DMINUS 0.1U/10V_4 1000P/50V_4 C134 DPLL_VDDC 10U/6.3V_8 Phase Lock Loop Power M72-S/M82-S Dedicated digital power pin for display PLLs. DPA_B_VDDR 1.1 V ± 5% Thermal Sensor 5,35 MBCLK2 R524 0_4 1.1V(S100,D200mA) 5,35 MBDATA2 R525 0_4 781-1_3V R509 200/F_6 +3V_DELAY DPA_B_VDDR L70 +1.1V U30 C790 0.1U/10V_4 BLM18PG181SN1D(180,1.5A)_6 C741 *22P/50V_4 EVGA-XTALI VTHM_CLK R518 *0_4 MBCLK2 8 1 C740 C742 C737 SMCLK VCC VGATHRM+ 10U/6.3V_8 1 VTHM_DAT R519 *0_4 MBDATA2 7 2 0.1U/10V_4 1000P/50V_4 SMDATA DXPA CL=20PF *27MHZ Y7 R468 *10M_6 For Int Clk 27Mhz +3V_DELAY R516 10K/F_4 VGA_ALERT 6 -ALT DXN 3 C793 2200P/50V_4 w/s 10 / 10 A 2 5 4 VGATHRM- C735 EVGA-XTALO GND -OVT *22P/50V_4 G781-1P8@EV -VGATHRM +3V_DELAY I2C ADDRESS: 9AH R513 10K/F_4 PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev Custom 1A M7X/M8X_Main NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 18 of 45 5 4 3 2 1
    • 5 4 3 2 1 1.8V -(300mA) L14 BLM18PG181SN1D(180,1.5A)_6 +LVDDR_1-2 U29F 19 +1.8V U29E C109 C123 PART 6 OF 6 R83 10K/F_4 Part 5 of 6 C103 1U/10V_4 1U/10V_4 0.1U/10V_4 AF20 AA7 0_4 R89 LVDDR_1 VARY_BL DPST_PWM 10,23 VSS_33 B25 AG20 LVDDR_2 AA26 J8 Control AC6 0_4 R80 PCIE_VSS_1 VSS_34 DIGON DISP_ON 10,23 AA29 PCIE_VSS_2 VSS_35 B5 1.8V(100mA) AC26 D11 L19 BLM18PG181SN1D(180,1.5A)_6 +1.8V_LVDDC AJ18 LVDS channel PCIE_VSS_3 VSS_36 +1.8V LVDDC_1 AD31 PCIE_VSS_4 VSS_37 C17 AH20 LVDDC_2 TXCLK_UP AD21 EXT_TXUCLKOUT+ 23 AE29 PCIE_VSS_5 VSS_38 C22 TXCLK_UN AE21 EXT_TXUCLKOUT- 23 AE30 C27 C133 C125 C144 AJ24 PCIE_VSS_6 VSS_39 TXOUT_U0P EXT_TXUOUT0+ 23 AE31 D29 1U/10V_4 1U/10V_4 1U/10V_4 AJ23 PCIE_VSS_7 VSS_40 TXOUT_U0N EXT_TXUOUT0- 23D F28 PCIE_VSS_8 VSS_41 C3 AF23 LVSSR_1 TXOUT_U1P AK24 EXT_TXUOUT1+ 23 D G26 PCIE_VSS_9 VSS_42 C6 AF21 LVSSR_2 TXOUT_U1N AL24 EXT_TXUOUT1- 23 G29 PCIE_VSS_10 VSS_43 D3 AL18 LVSSR_3 TXOUT_U2P AG21 EXT_TXUOUT2+ 23 PCI-Express GND G30 PCIE_VSS_11 VSS_44 D28 LVDDR AJ22 LVSSR_4 TXOUT_U2N AH21 EXT_TXUOUT2- 23 G31 PCIE_VSS_12 VSS_45 F29 LVDS Output Driver Analog Power Supply AJ25 LVSSR_5 TXOUT_U3P AG23 H29 PCIE_VSS_13 VSS_46 D4 1.8 V ± 3% AK18 LVSSR_6 TXOUT_U3N AH23 J25 PCIE_VSS_14 VSS_47 F11 AK23 LVSSR_7 J26 PCIE_VSS_15 VSS_48 F12 AK25 LVSSR_8 TXCLK_LP AL19 EXT_TXLCLKOUT+ 23 L26 PCIE_VSS_16 VSS_49 F14 LVDDC AJ21 LVSSR_9 TXCLK_LN AK19 EXT_TXLCLKOUT- 23 L29 PCIE_VSS_17 VSS_50 F16 LVDS Output Driver Digital Power Supply AL23 LVSSR_10 TXOUT_L0P AJ20 EXT_TXLOUT0+ 23 L30 PCIE_VSS_18 VSS_51 F18 1.8 V ± 3% AL25 LVSSR_11 TXOUT_L0N AJ19 EXT_TXLOUT0- 23 L31 PCIE_VSS_19 VSS_52 F20 TXOUT_L1P AK20 EXT_TXLOUT1+ 23 M26 PCIE_VSS_20 VSS_53 F21 TXOUT_L1N AL20 EXT_TXLOUT1- 23 M29 F23 LPVDD +1.8V_TPVDD AK21 PCIE_VSS_21 VSS_54 TXOUT_L2P EXT_TXLOUT2+ 23 P26 PCIE_VSS_22 VSS_55 F25 Analog Power for 1.8V(40mA) TXOUT_L2N AL21 EXT_TXLOUT2- 23 R29 PCIE_VSS_23 VSS_56 F7 transmitter PLL. It should AG18 LPVDD TXOUT_L3P AK22 R30 F9 AH18 AL22 R31 PCIE_VSS_24 VSS_57 G3 be a power for the PLL C155 LPVSS TXOUT_L3N PCIE_VSS_25 VSS_58 T26 PCIE_VSS_26 VSS_59 G6 block of the macro. C143 C132 U29 H23 1.8 V ± 3% 100P/50V_4 1U/10V_4 0.1U/10V_4 PCIE_VSS_27 VSS_60 M72-S/M82-S V26 PCIE_VSS_28 VSS_61 J3 Y26 PCIE_VSS_29 VSS_62 J4 Y29 PCIE_VSS_30 VSS_63 J6 Y30 K1 +3V_DELAY PCIE_VSS_31 VSS_64 Y31 PCIE_VSS_32 VSS_65 L12 VSS_66 L15 VSS_67 L18 L21 GPIO0 R92 *10K/F_4 VSS_68 VSS_69 L6 CONFIGURATION STRAPS 18 GPIO0 A13 M11 18 GPIO1 GPIO1 R514 *10K/F_4 VSS_1 VSS_70C A2 VSS_2 VSS_71 M14 C C18 M17 18 GPIO5 GPIO5 R517 *10K/F_4 VSS_3 VSS_72 A24 VSS_4 VSS_73 M20 A30 M6 PIN DESCRIPTION OF DEFAULT SETTINGS M82-S 18 VIP_3 VIP_3 R475 *10K/F_4 VSS_5 VSS_74 AA1 VSS_6 VSS_75 P12 AA11 P15 18 GPIO8 GPIO8 R94 10K/F_4 VSS_7 VSS_76 AA14 VSS_8 VSS_77 P18 GPIO0 PCIE FULL TX OUTPUT SWING 0 R465 10K/F_4 AA17 VSS_9 VSS_78 P21 10,18,24 HSYNC_COM AA20 VSS_10 VSS_79 P6 AA6 AC21 GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0 10,18,24 VSYNC_COM R485 *10K/F_4 VSS_11 VSS_80 AC2 VSS_12 VSS_81 R14 AC7 R17 18 PSYNC R79 *10K/F_4 VSS_13 VSS_82 AE3 VSS_15 VSS_83 R20 GPIO5 Allows eitherPCIe 2.5GT/s or 5GT/s operation REV AL4 VSS_16 VSS_84 T6 AD14 VSS_17 VSS_85 U1 AF12 VSS_18 VSS_86 U12 VIP3 ENABLE HD AUDIO ( M8X-M ) 1 AF14 VSS_19 VSS_87 U15 AD16 VSS_20 VSS_88 U18 AD18 VSS_21 VSS_89 U21 GPIO8 ENABLE HD AUDIO ( M82-S ) 1 AE6 VSS_22 VSS_90 AE20 AG2 VSS_23 VSS_91 V14 AE9 VSS_24 VSS_92 V17 HSYNC ENABLED HDMI 1 AH25 VSS_25 VSS_93 V20 AK1 VSS_26 VSS_94 P2 AK31 VSS_27 VSS_95 V6 AJ6 VSS_28 VSS_96 W2 AL2 VSS_29 VSS_97 Y12 AL30 Y15 B1 VSS_30 VSS_31 VSS_98 VSS_99 Y18 Memory Aperture size SI-1 Modified -- follow AMDB C13 VSS_32 VSS_100 Y21 reference schematic change for B VSS_101 Y6 reduce leakage to VDDR3 BUS M9 VSS_102 GPIO9 GPIO13 GPIO12 GPIO11 CORE GND BIOSROM ROMIDCFG2 ROMIDCFG1 ROMIDCFG0 M72-S/M82-S 0 128M 0 0 0 0 256M 0 0 1 0 64M 0 1 0 +3V_DELAY 0 32M 0 1 1 GPIO9 R90 *10K/F_4 18 GPIO9 0 512M 1 0 0 18 GPIO13 GPIO13 R523 *10K/F_4 GPIO12 R521 *10K/F_4 0 1G 1 0 1 18 GPIO12 GPIO11 R520 10K/F_4 18 GPIO11 0 2G 1 1 0A 0 4G 1 1 1 A It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0. PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev Custom 1A M7X/M8X_GND / LVDS/ Straps NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 19 of 45 5 4 3 2 1
    • 5 4 3 2 1 20 PCIE_VDDR--PCI-E I/O power. 1.8 V ± 5% U29D VDDR1-- I/O power for the memory interface on M82 1.8 V ± 5% +1.8V_PCIE_VDDRD D PART 4 OF 6 1.8V(400mA) 1.8V(1.1A) A15 AF30 +1.8V_PCIE_VDDR L74 +1.8V VDDR1_1 PCIE_VDDR_1 +1.8V A22 VDDR1_2 PCIE_VDDR_2 AF31 A28 AF29 C759 BLM18PG181SN1D(180,1.5A)_6 C820 C438 C339 C312 VDDR1_3 PCIE_VDDR_3 C760 C761 A4 VDDR1_4 PCIE_VDDR_4 AF27 C263 C300 C305 A8 AF28 *0.1U/10V_4 1U/10V_4 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 VDDR1_5 PCIE_VDDR_5 +1.1V 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 B8 AG29 VDDR1_6 PCIE_VDDR_6 C9 VDDR1_7 PCIE_VDDR_7 AG30 +1.1V_PCIE_VDDC Memory I/O D1 VDDR1_8 PCIE_VDDR_8 AG31 1.1V(1.0A) H1 VDDR1_9 H11 AA23 +1.1V_PCIE_VDDC L21 VDDR1_10 PCIE_VDDC_1 BLM18PG181SN1D(180,1.5A)_6 H12 VDDR1_11 PCIE_VDDC_2 AC24 H14 AC25 C244 C219 C138 VDDR1_12 PCIE_VDDC_3 C311 C326 C298 C327 H16 VDDR1_13 PCIE_VDDC_4 AE26 C186 C207 PCIE_VDDC--PCI-E H18 AE27 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 Digital Power PCI-Express 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDR1_14 PCIE_VDDC_5 H20 VDDR1_15 PCIE_VDDC_6 AE28 Supply (Either 1.0 VDD_CT -- Level H21 L23 translation between B31 VDDR1_16 PCIE_VDDC_7 M23 V or 1.1 V) 1.0 V +1.8V_VDD_CT VDDR1_17 PCIE_VDDC_8 core and I/O, 1.8V(110mA) M1 VDDR1_18 PCIE_VDDC_9 P23 -5% to 1.1 V +5% T23 excluding memory L28 BLM18PG181SN1D(180,1.5A)_6 +1.8V_VDD_CT AA9 PCIE_VDDC_10 V23 +1.8V VDD_CT_1 PCIE_VDDC_11 receivers.1.8 V ± 5% Y9 VDD_CT_2 PCIE_VDDC_12 Y23 VDDC+VDDCI C314 C257 V9 +VGA_CORE VDD_CT_3 0.95~1.1V(15A peak )( Ripple < 87.2mV) C291 T9 VDD_CT_4 VDDC--Dedicated core 10U/6.3V_8 1000P/50V_4 J11 L11 power, provides power Q34 VDD_CT_5 VDDC_1 P-MOS,2.6A Gated 3.3V 0.1U/10V_4 J20 VDD_CT_6 VDDC_2 L14 to the internal AO3409 +3V_DELAY C222 C232 C73 50mA by J21 VDD_CT_7 VDDC_3 L17 logic. 0.9 V - 1.2 V L9 L20 C227 C215 VDDC +3V_DELAY VDD_CT_8 VDDC_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 (± 5%)C +3V 1 3 VDDC_5 M12 C M72-S/M82-S M15 VDDC_6 VDD_R3 --IO power for C174 C191 I/O Internal AC18 VDDR3_1 VDDC_7 M18 3.3 V pins (e.g. C184 AC16 M21 2 R443 1U/10V_4 1U/10V_4 0.1U/10V_4 VDDR3_2 VDDC_8 GPIO’s). 3.3 V ± 5% AC14 VDDR3_3 VDDC_9 AC20 100K/F_4 +VDDR4 AC12 P14 VDDR3_4 VDDC_10 C210 C262 C261 C86 VDDC_11 P17 +1.8V L94 BLM18PG181SN1D(180,1.5A)_6 C937 AF1 AF2 VDDR4_1 P VDDC_12 P20 R12 1U/10V_4 1U/10V_4 1U/10V_4 C266 1U/10V_4 10U/6.3V_8 VDDR4_2 VDDC_13 SI-1 Modified -- follow AMD C935 C936 O R15 Core reference schematic change *10U/6.3V_8 1U/10V_4 0.1U/10V_4 VDDC_14 AE1 R18 D8 CH501H-40PT AE2 VDDR5_1 VDDR5_2 W VDDC_15 VDDC_16 R21 1 2 AD20 1.8/3.3V 150mA +VDDR5 E VDDC_17 VDDC_18 U14 L95 C233 C198 C228 C9127,35,39,42,43,44 MAINON +1.8V C780 C779 M2 R VDDC_19 U17 U20 C200 R42 68.1K_4 BLM18PG181SN1D(180,1.5A)_6 C938 C781 RSVD_1 VDDC_20 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 M3 V12 10U/6.3V_8 *10U/6.3V_8 1U/10V_4 1U/10V_4 0.1U/10V_4 RSVD_2 VDDC_21 L4 RSVD_3 VDDC_22 V15 Q8 AD11 V18 RSVD_4 VDDC_23 3 2N7002E V21 D9 VDDC_24 VDDC_25 Y11 L30 BLM18PG181SN1D(180,1.5A)_6 +1.8V_VDDRH_1 A10 Y14 +1.8V VDDRH_1 VDDC_26 1 2 2 C347 A19 Y17 C181 C265 C211 C9023,35,38,39,41,42 HWPG VDDRH_2 VDDC_27 Clock I/O Memory C346 Y20 C229 *CH501H-40PT L-F 10U/6.3V_8 0.1U/10V_4 VDDC_28 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 AA12 10U/6.3V_8 VDDC_29 B10 VSSRH_1 VDDC_30 AA15 B19 AA18 1 L80 BLM18PG181SN1D(180,1.5A)_6 +1.8V_VDDRH_2 VSSRH_2 VDDC_31 +1.8V VDDC_32 AA21 R45 *75K/F_4 C58 P9 VDDC_33B C826 C825 BBN -0.75V 100mA B 10U/6.3V_8 V11 BBN_1 Back Bias 0.1U/10V_4 0.1U/10V_4 U11 J12 +VDDCI L27 +VBBP BBN_2 VDDCI_1 +VGA_CORE J14 BLM18PG181SN1D(180,1.5A)_6 VDDCI_2 1.5/1.8V 120mA VDDCI_3 J16 C294 C282 C293 R11 BBP_1 VDDCI_4 J18 C283 VDDCI--Isolated (clean) P11 0.1U/10V_4 0.1U/10V_4 1U/10V_4 10U/6.3V_8 core power for the l/O C212 BBP_2 C260 logic. Voltage level 1U/10V_4 0.1U/10V_4 should match that of VDDC. POWER Same as VDDC VDD_R4 -- Power for DVPDATA_[23:12] - external TMDS or GPIO; corresponds to +VBBP DVOA_MSB_VMODE register bit; 1 - 3.3 V(default); *BLM18PG181SN1D(180,1.5A)_6 BBP -- Connect to VBBP back bias regulator / generator. 0 - 1.8 V; 1.8 V ± 5% or 3.3 V ± 5% If back bias is not used, connect directly to VDDC. +VGA_CORE L93 SI-1 modified -- ADD power play function Back Bias Enabled: VDD_R5 -- Power for DVP control pins Q61 (GPIO_21_BB_EN = 3.3 V): (DVPCNTL_[0-2] and DVPCLK) and 2N7002E 1.5 V or 1.8 V Q62 DVPDATA_[11:0] - external TMDS or GPIO; ME2303T1 corresponds to DVOA_LSB_VMODE register bit; 3 1 3 1 +1.8V Back Bias Disabled: +VGA_CORE 1 - 3.3 V(default); 0 - 1.8 V; 1.8 V (GPIO_21_BB_EN = 0 V): ± 5% or 3.3 V ± 5% VDDC 2 2 R752 100K/F_4 VDDRH_1 & VDDRH_2 --Dedicated power 1 2 +5VA pins for memory clock pads for each A 3 channel. Should have the same voltage level as VDDR1. 2 Q63 18 BBEN 2N7002E PROJECT : QT8 Quanta Computer Inc. 1 Size Document Number Rev Custom 1A M7X/M8X_Power_and_NC NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 20 of 45 5 4 3 2 1
    • 5 4 3 2 1 22 ODTA0 ODTA0 ODTA1 MDA0 MDA1 E29 U29C DQ_0 Part 3 of 6 MA_0 B14 MAA0 MAA1 21 22 ODTA1 E30 DQ_1 MA_1 A14 MDA2 E31 B13 MAA2 RASA0# MDA3 DQ_2 MA_2 MAA3 22 RASA0# D31 DQ_3 MA_3 E14 RASA1# MDA4 MAA4D 22 RASA1# MDA5 C29 B29 DQ_4 MEMORY MA_4 B17 A17 MAA5 D CASA0# MDA6 DQ_5 MA_5 MAA6 22 CASA0# CASA1# MDA7 B30 A29 DQ_6 INTERFACE MA_6 C15 G16 MAA7 22 CASA1# DQ_7 MA_7 MDA8 E26 E16 MAA8 WEA0# MDA9 DQ_8 MA_8 MAA9 22 WEA0# D26 DQ_9 MA_9 C14 22 WEA1# WEA1# MDA10 E25 A12 MAA10 MDA11 DQ_10 MA_10 MAA11 D25 DQ_11 MA_11 B12 22 CSA0#_0 CSA0#_0 MDA12 G23 C12 A_BA0 MDA13 DQ_12 MA_BA0 A_BA1 G21 DQ_13 MA_BA1 D14 MDA14 E21 B15 MAA12 CSA1#_0 MDA15 DQ_14 MA_A12 A_BA2 22 CSA1#_0 D21 DQ_15 MA_BA2 G14 A_BA2 22 MDA16 C28 MDA17 DQ_16 DQMA#0 B28 DQ_17 DQMb_0 D30 22 CKEA0 CKEA0 MDA18 B27 DQ_18 DQMb_1 G25 DQMA#1 SI-1 modified -- 22 CKEA1 CKEA1 MDA19 A27 C26 DQMA#2 for support MDA20 DQ_19 DQMb_2 DQMA#3 C25 DQ_20 DQMb_3 C21 1Gbit VRAM ( 64M 22 CLKA0 CLKA0 MDA21 A25 C5 DQMA#4 22 CLKA0# CLKA0# MDA22 C24 DQ_21 DQMb_4 D6 DQMA#5 X 16 ) MDA23 DQ_22 DQMb_5 DQMA#6 B24 DQ_23 DQMb_6 D2 22 CLKA1 CLKA1 MDA24 C23 K3 DQMA#7 CLKA1# MDA25 DQ_24 DQMb_7 22 CLKA1# B23 DQ_25 MDA26 A23 C30 QSA0 QSA#[7..0] MDA27 DQ_26 QS_0 QSA1 22 QSA#[7..0] B22 DQ_27 QS_1 D23 MDA28 C20 B26 QSA2C DQ_28 QS_2 C QSA[7..0] MDA29 B20 B21 QSA3 22 QSA[7..0] DQ_29 QS_3 MDA30 A20 B6 QSA4 read strobe DQMA#[7..0] MDA31 DQ_30 QS_4 QSA5 22 DQMA#[7..0] C19 DQ_31 QS_5 E7 MDA32 C8 E2 QSA6 MDA[63..0] MDA33 DQ_32 QS_6 QSA7 22 MDA[63..0] C7 DQ_33 QS_7 J2 MDA34 B7 MAA[12..0] MDA35 DQ_34 QSA#0 22 MAA[12..0] A7 DQ_35 QS_0B C31 MDA36 A5 E23 QSA#1 MDA37 DQ_36 QS_1B QSA#2 write strobe C4 DQ_37 QS_2B A26 MDA38 B4 A21 QSA#3 A_BA0 MDA39 DQ_38 QS_3B QSA#4 22 A_BA0 A3 DQ_39 QS_4B A6 22 A_BA1 A_BA1 MDA40 G9 D7 QSA#5 MDA41 DQ_40 QS_5B QSA#6 E9 DQ_41 QS_6B E1 MDA42 D9 J1 QSA#7 MDA43 DQ_42 QS_7B G7 DQ_43 MDA44 G5 E20 ODTA0 MDA45 DQ_44 ODT0 ODTA1 F5 DQ_45 ODT1 C11 MDA46 G4 MDA47 DQ_46 CLKA0 F4 DQ_47 CLK0 A18 MDA48 B3 A11 CLKA1 MDA49 DQ_48 CLK1 B2 DQ_49 MDA50 C2 B18 CLKA0# MDA51 DQ_50 CLK0b CLKA1# C1 DQ_51 CLK1b B11B MDA52 E3 B MDA53 DQ_52 RASA0# F3 DQ_53 RAS0b G20 MDA54 F2 D12 RASA1# MDA55 DQ_54 RAS1b F1 DQ_55 MDA56 G2 D20 CASA0# +1.8V MDA57 DQ_56 CAS0b CASA1# G1 DQ_57 CAS1b E12 MDA58 H3 MDA59 DQ_58 CSA0#_0 H2 DQ_59 CS0b_0 E18 MDA60 K2 G18 R116 MDA61 DQ_60 CS0b_1 L3 DQ_61 100/F_4 MDA62 L2 G11 CSA1#_0 MDA63 DQ_62 CS1b_0 L1 DQ_63 CS1b_1 E11 MVREFD F30 D18 CKEA0 +1.8V MVREFD CKE0 CKEA1 F31 MVREFS CKE1 G12 D16 WEA0# R113 R98 4.7K_4 WE0b WEA1# L5 TEST_MCLK WE1b C10 C338 100/F_4 R532 R102 4.7K_4 L7 0.1U/10V_4 100/F_4 R97 240/F_4 TEST_YCLK J7 MEMTEST DRAM_RST J5 +1.8V R101 4.7K_4 MVREFS Change MEMTEST to 240 1% M72-S/M82-S ohm to GND , AMD updateA A R529 C817 0.1U/10V_4 100/F_4 PROJECT : QT8 Quanta Computer Inc. Size Document Number Rev B 1A M7X/M8X/MEM_Interface NB5/RD5 Date: Tuesday, February 19, 2008 Sheet 21 of 45 5 4 3 2 1
    • 5 4 3 2 1 A_BA0 A_BA1 MAA12 MAA11 L2 L3 R2 P7 U5 BA0 BA1 A12 DQ15 DQ14 DQ13 DQ12 B9 B1 D9 D1 D3 MDA9 MDA13 MDA10 MDA15 MDA14 DDR2 BGA MEMORY A_BA0 A_BA1 MAA12 R2 L2 L3 U35 BA0 BA1 DQ15 DQ14 DQ13 B9 B1 D9 D1 MDA6 MDA0 MDA7