• Share
  • Email
  • Embed
  • Like
  • Save
  • Private Content
Dv4
 

Dv4

on

  • 1,035 views

 

Statistics

Views

Total Views
1,035
Views on SlideShare
1,035
Embed Views
0

Actions

Likes
0
Downloads
19
Comments
0

0 Embeds 0

No embeds

Accessibility

Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Dv4 Dv4 Presentation Transcript

    • A B C D E1 12 Compal confidential 2 Schematics Document Mobile AMD S1G3 CPU with ATI3 RS880M(NB) & SB710(SB) core logic 3 2009-03-15 REV:0.34 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Cover Sheet AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 1 of 56 A B C D E
    • A B C D E Compal Confidential Consumer AMD 14" UMA - Ripley 2.0 (NBW20) Accelerometer Thermal Sensor 72QFN1 ST LIS302DLTR ADM1032ARMZ AMD S1G3 CPU DDR2-SO-DIMM X2 1 Page 30 Page 6 DDR2 800MHz 1.8V BANK 0, 1, 2, 3 Page 8, 9 Clock Generator Dual Channel SLG8SP626VTR Fan conn 638-PIN uFCPGA 638 Page 15 Page 4 Page 4, 5, 6, 7 Side-Port DDR2 SDRAM Hyper Transport Link 1024Mbits(64Mbx16) 12 Page 16X16 USB conn x2 daughter board Page 31 LVDS Panel ATI RS880M Interface Page 17 DDR2 400MHz BT Conn Page 31 New Module CRT Page 16 Page 10, 11, 12, 13, 142 Mini-Card WWAN Page 26 2 USB2.0 X12 HDMI A-Link Express II Page 18 4X PCI-E USB conn x1 Page 31 PCI-E BUS*5 Azalia (HDA I/F) USB WebCam SATA Master-1 Module ATI SB710 SATA Master-2 Page 17 SATA Slave CardReader Realtek Mini-Card*2 Express Card FingerPrinter AES1610 JMicron 8102E(10/100M) WLAN & WWAN SATA Slave Module Page 26 Page 19, 20, 21, 22, 23 USBx1 page 35 JMB385-LGEZ0A Page 27 Page 25 Page 26 MDC V1.5 daughter board Page 34 RJ45/11 CONN LPC BUS Audio CKT3 CardReader Socket Page 25 AMP & Audio Jack 3 Codec_IDT9271B7 Page 27 Page 28 TPA6017A2 Page 29 KBC SATA HDD Connector ENE KB926-C0 Page 24 Page 33 Docking CONN. LED SATA ODD Connector Page 24 *RJ-45(LED*2) P41 Touch Pad CONN. Page 34 Int.KBD Page 33 *RJ-11(Pass Through) Multi-Bay HDD/ODD Option Connector *CRT Page 24 *COMPOSITE Video Out RTC CKT. *S-VIDEO OUT Page 19 Consumer IR SPI SPI ROM e-SATA Connector *SPDIF MX25L1605 Page 34 Page 31 *Headphone/Line Out L/R Power OK CKT. AM2C-12G Page 32 *Stereo Mic L/R P354 *Volume Control 4 *Consumer IR *USB x1 Power On/Off CKT. *DC JACK P35 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title DC/DC Interface CKT. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Block Diagram AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev Page 35 Page 36 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 2 of 56 A B C D E
    • A B C D E Symbol Note : 1.0/1.0a For Riply PA-> PA@, RP@ : means Digital Ground For Riply PR-> PR@, RP@, PRM@ For Rachman UMA-> RM@, PRM@ O MEANS ON X MEANS OFF Voltage Rails RP10@ Z ZZ RM10@ Z ZZ : means Analog Ground1 PCB for 1.0/1.0a 1 L Layout Notes PCB-Ripley MB PCB-Rachman UMA MB +5VS Please see VGA@ as no install. No support RX780M. DAZ=DAZ03Y00201 DAZ=DAZ03Y00101 +3VS +1.5VS : Question Area Mark.(Wait check) RP11@,RM11@:For 1.A PCB power plane +0.9V RP10@,RM10@:For 1.0 PCB. +VCCP "*" as default BOM setting +5VALW +1.8V +CPU_CORE *PA@ : means install when Ripley PA. U3 U15 +B PR@ : means install when Ripley PR. SB700 +3VALW +VGA_CORE RM@ : means install when Rachman. RS780 +2.5VS *RP@ : means install when Ripley. RS780 R1 SB700 R1 RS780R1@ SBR1@ State +1.8VS SIDE@ : means install when SidePort support. +1.2VS @ : means just reserve , no build +0.9VGA 45@ : Install when 45 level Assy2 R3 NB and SB: RS780R3@,SBR3@ 2 R1 NB and SB: RS780R1@,SBR1@ S0 O O O O RP11@ RM11@ 1.1 Z ZZ Z ZZ S1 O O O O For Riply PA-> PA@, RP@,RPZ@ PCB for 1.1 S3 For Riply PR-> PR@, RP@, PRM@,RPZ@ O O O X For Rachman UMA-> RM@, PRM@,RMZ@ PCB-Ripley MB PCB-Rachman UMA MB DAZ=DAZ03Y00203 DAZ=DAZ03Y00102 S5 S4/AC 2.0 O O X X RP@ RM@ X76 Z ZZ Z ZZ S5 S4/ Battery only For Riply PA-> PA@/RP@/RPZ@ O X X X PCB for 2.0 X76 S5 S4/AC & Battery For Rachman UMA-> RM@/PRM@/RMZ@ PCB-Ripley MB PCB-Rachman UMA MB dont exist X X X X SMBUS Control Table DAZ=DAZ09000102 DAZ=DAZ09100102 THERMAL SERIAL SENSOR SOURCE INVERTER BATT EEPROM CPU & SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor ADM1032 I / II Slot 23 3 SMB_EC_CK1 I2C / SMBUS ADDRESSING KB926 X V V VCPU X X X X X X SMB_EC_DA1 SMB_EC_CK2 DEVICE HEX ADDRESS SMB_EC_DA2 KB926 X X X V ADM1032 X X X X X X DDR SO-DIMM 0 A0 10100000 I2C_CLK DDR SO-DIMM 1 A4 10100100 I2C_DATA RS780M X X X X X X X V X X CL OCK GENERATOR (EXT.) D2 11010010 DDC_CLK0 DDC_DATA0 RS780M X X X X X X X X V X DDC_CLK1 EC SM Bus1 address EC SM Bus2 address DDC_DATA1 RS780M X X X X X X X X X X SCL0 Device HEX Address Device HEX Address SDA0 SB700 X X X X V V X X X X Smart Battery 16H 0001 011X b CPU 98H 1001 100X b SCL1 24C16 A0H 1010 000X b ADI1032-2 CPU 9AH 1001 101X b SDA1 SB700 X X X X X X V X X X SCL2 SDA2 SB700 X X X X X X X X X V4 4 SCL3 SDA3 SB700 X X X X X X X X X X Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Notes List AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 3 of 56 A B C D E
    • A B C D E1 1 +1.2V_HT VLDT CAP. 250 mil 1 1 1 1 1 1 C1 C2 C3 C4 C5 C6 H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J <10> H_CADIP[0..15] H_CADOP[0..15] <10> H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2 <10> H_CADIN[0..15] H_CADON[0..15] <10> Near CPU Socket +1.2V_HT JCPUA VLDT=500mA D1 HT LINK AE2 +VLDT_B 1 2 VLDT_A0 VLDT_B0 C7 4.7U_0805_10V4Z D2 VLDT_A1 VLDT_B1 AE3 D3 AE4 If VLDT is connected only on one side, one VLDT_A2 VLDT_B2 4.7uF cap should be added to the island D4 AE5 VLDT_A3 VLDT_B3 side. H_CADIP0 E3 AD1 H_CADOP0 H _CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0 E2 AC1 H_CADIP1 L0_CADIN_L0 L0_CADOUT_L0 H_CADOP1 E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 H _CADIN1 F1 AC3 H_CADON1 H_CADIP2 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP2 G3 AB1 H _CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2 G2 AA12 H_CADIP3 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP3 2 G1 L0_CADIN_H3 L0_CADOUT_H3 AA2 H _CADIN3 H1 AA3 H_CADON3 H_CADIP4 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP4 J1 W2 H _CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4 K1 L0_CADIN_L4 L0_CADOUT_L4 W3 H_CADIP5 L3 V1 H_CADOP5 H _CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5 L2 U1 H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6 L1 L0_CADIN_H6 L0_CADOUT_H6 U2 H _CADIN6 M1 U3 H_CADON6 H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7 N3 L0_CADIN_H7 L0_CADOUT_H7 T1 H _CADIN7 N2 R1 H_CADON7 H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8 E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 H _CADIN8 F5 AD3 H_CADON8 H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9 F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 H _CADIN9 F4 AC5 H_CADON9 H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10 G5 AB4 H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10 H5 AB3 H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11 H3 AB5 H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11 H4 AA5 H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12 K3 Y5 H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12 K4 L0_CADIN_L12 L0_CADOUT_L12 W5 H_CADIP13 L5 V4 H_CADOP13 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 M5 V3 H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14 M3 V5 H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14 M4 U5 H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15 N5 T4 H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15 +5VS P5 T3 L0_CADIN_L15 L0_CADOUT_L15 J3 Y1 <10> <10> H_CLKIP0 H_CLKIN0 J2 J5 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKOUT_H0 L0_CLKOUT_L0 W1 Y4 H_CLKOP0 H_CLKON0 <10> <10> PWM Fan Control circuit JP2 <10> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <10> 1 <10> H_CLKIN1 K5 Y3 H_CLKON1 <10> 1 1 1 L0_CLKIN_L1 L0_CLKOUT_L1 C8 C9 1 23 D1 0.1U_0402_16V4Z 2 3 <10> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <10> P1 R3 CH751H-40PT_SOD323-2 4.7U_0805_10V4Z 3 <10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10> 2 2 GND <10> H_CTLIP1 P3 T5 H_CTLOP1 <10> 4 2 L0_CTLIN_H1 L0_CTLOUT_H1 GND <10> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <10> ACES_88231-02001 +VCC_FAN CONN@ FOX_PZ6382A-284S-41F_GRIFFIN CONN@ 1 2 5 6 1 Athlon 64 S1 Processor Socket D Q1 @ D2 9/20 SP07000DM00/SP07000EQ00 G 3 RLZ5.1B_LL34 <33> FAN_PWM S SI3456BDV-T1-E3_TSOP6 2 44 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD CPU S1G2 HT I/F AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 4 of 56 A B C D E
    • A B C D E Processor DDR2 Memory Interface PLACE CLOSE TO PROCESSOR1 WITHIN 1.5 INCH 1 JCPUC <9> DDR_B_D[63..0] MEM:DATA DDR_A_CLK0 DDR_B_D0 DDR_A_D0 DDR_A_D[63..0] <8> C11 MB_DATA0 MA_DATA0 G12 1 DDR_B_D1 A11 F12 DDR_A_D1 DDR_B_D2 MB_DATA1 MA_DATA1 DDR_A_D2 A14 H14 C10 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3 B14 MB_DATA3 MA_DATA3 G14 1.5P_0402_50V9C DDR_B_D4 G11 H11 DDR_A_D4 DDR_A_CLK#0 2 DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5 E11 MB_DATA5 MA_DATA5 H12 DDR_B_D6 D12 C13 DDR_A_D6 DDR_A_CLK1 DDR_B_D7 MB_DATA6 MA_DATA6 DDR_A_D7 A13 E13 DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8 1 A15 MB_DATA8 MA_DATA8 H15 DDR_B_D9 A16 E15 DDR_A_D9 C11 DDR_B_D10 MB_DATA9 MA_DATA9 DDR_A_D10 A19 MB_DATA10 MA_DATA10 E17 1.5P_0402_50V9C DDR_B_D11 A20 H17 DDR_A_D11 DDR_A_CLK#1 2 DDR_B_D12 MB_DATA11 MA_DATA11 DDR_A_D12 C14 E14 +1.8V DDR_B_D13 MB_DATA12 MA_DATA12 DDR_A_D13 D14 F14 DDR_B_D14 MB_DATA13 MA_DATA13 DDR_A_D14 C18 MB_DATA14 MA_DATA14 C17 DDR_B_CLK0 DDR_B_D15 D18 G17 DDR_A_D15 MB_DATA15 MA_DATA15 2 1 DDR_B_D16 D20 G18 DDR_A_D16 R1 DDR_B_D17 MB_DATA16 MA_DATA16 DDR_A_D17 A21 C19 C14 DDR_B_D18 MB_DATA17 MA_DATA17 DDR_A_D18 D24 D22 1.5P_0402_50V9C 1K_0402_1% DDR_B_D19 MB_DATA18 MA_DATA18 DDR_A_D19 C25 E20 DDR_B_CLK#0 2 DDR_B_D20 MB_DATA19 MA_DATA19 DDR_A_D20 B20 E18 1 +MCH_REF DDR_B_D21 MB_DATA20 MA_DATA20 DDR_A_D21 C20 MB_DATA21 MA_DATA21 F18 DDR_B_CLK1 DDR_B_D22 B24 B22 DDR_A_D22 MB_DATA22 MA_DATA22 2 1 1 1 DDR_B_D23 C24 C23 DDR_A_D23 R2 C12 C13 DDR_B_D24 MB_DATA23 MA_DATA23 DDR_A_D24 E23 F20 C15 DDR_B_D25 MB_DATA24 MA_DATA24 DDR_A_D25 E24 F22 1.5P_0402_50V9C 1K_0402_1% DDR_B_D26 MB_DATA25 MA_DATA25 DDR_A_D26 G25 MB_DATA26 MA_DATA26 H24 DDR_B_CLK#1 2 2 2 DDR_B_D27 G26 J19 DDR_A_D27 1 1000P_0402_25V8J DDR_B_D28 MB_DATA27 MA_DATA27 DDR_A_D28 C26 E21 0.1U_0402_16V4Z DDR_B_D29 MB_DATA28 MA_DATA28 DDR_A_D29 D26 E222 DDR_B_D30 MB_DATA29 MA_DATA29 DDR_A_D30 2 G23 MB_DATA30 MA_DATA30 H20 +0.9V +0.9V DDR_B_D31 G24 H22 DDR_A_D31 JCPUB DDR_B_D32 MB_DATA31 MA_DATA31 DDR_A_D32 AA24 Y24 DDR_B_D33 MB_DATA32 MA_DATA32 DDR_A_D33 AA23 MB_DATA33 MA_DATA33 AB24 D10 W10 DDR_B_D34 AD24 AB22 DDR_A_D34 VTT1 MEM:CMD/CTRL/CLK VTT5 DDR_B_D35 MB_DATA34 MA_DATA34 DDR_A_D35 Place them close to CPU within 1" C10 VTT2 VTT6 AC10 AE24 MB_DATA35 MA_DATA35 AA21 B10 AB10 DDR_B_D36 AA26 W22 DDR_A_D36 VTT3 VTT7 DDR_B_D37 MB_DATA36 MA_DATA36 DDR_A_D37 AD10 AA10 AA25 W21 R4 39.2_0402_1% VTT4 VTT8 DDR_B_D38 MB_DATA37 MA_DATA37 DDR_A_D38 VTT9 A10 AD26 MB_DATA38 MA_DATA38 Y22 1 2 AF10 DDR_B_D39 AE25 AA22 DDR_A_D39 MEMZP VTT_SENSE DDR_B_D40 MB_DATA39 MA_DATA39 DDR_A_D40 +1.8V 1 2 AE10 MEMZN VTT_SENSE Y10 PAD T1 AC22 MB_DATA40 MA_DATA40 Y20 R3 39.2_0402_1% DDR_B_D41 AD22 AA20 DDR_A_D41 +MCH_REF DDR_B_D42 MB_DATA41 MA_DATA41 DDR_A_D42 T2 PAD H16 RSVD_M1 MEMVREF W17 AE20 MB_DATA42 MA_DATA42 AA18 DDR_B_D43 AF20 AB18 DDR_A_D43 DDR_A_ODT0 DDR_B_D44 MB_DATA43 MA_DATA43 DDR_A_D44 <8> DDR_A_ODT0 T19 B18 PAD T3 AF24 AB21 DDR_A_ODT1 MA0_ODT0 RSVD_M2 DDR_B_D45 MB_DATA44 MA_DATA44 DDR_A_D45 <8> DDR_A_ODT1 V22 AF23 AD21 MA0_ODT1 DDR_B_ODT0 DDR_B_D46 MB_DATA45 MA_DATA45 DDR_A_D46 U21 W26 DDR_B_ODT0 <9> AC20 AD19 MA1_ODT0 MB0_ODT0 DDR_B_ODT1 DDR_B_D47 MB_DATA46 MA_DATA46 DDR_A_D47 V19 W23 DDR_B_ODT1 <9> AD20 Y18 MA1_ODT1 MB0_ODT1 DDR_B_D48 MB_DATA47 MA_DATA47 DDR_A_D48 Y26 AD18 AD17 DDR_CS0_DIMMA# MB1_ODT0 DDR_B_D49 MB_DATA48 MA_DATA48 DDR_A_D49 <8> DDR_CS0_DIMMA# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16 DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D50 AC14 W14 DDR_A_D50 <8> DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# <9> MB_DATA50 MA_DATA50 U20 W25 DDR_CS1_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51 MA1_CS_L0 MB0_CS_L1 DDR_CS1_DIMMB# <9> DDR_B_D52 MB_DATA51 MA_DATA51 DDR_A_D52 V20 U22 AF19 Y17 MA1_CS_L1 MB1_CS_L0 DDR_B_D53 MB_DATA52 MA_DATA52 DDR_A_D53 AC18 AB17 DDR_CKE0_DIMMA DDR_CKE0_DIMMB DDR_B_D54 MB_DATA53 MA_DATA53 DDR_A_D54 <8> DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB <9> AF16 AB15 DDR_CKE1_DIMMA MA_CKE0 MB_CKE0 DDR_CKE1_DIMMB DDR_B_D55 MB_DATA54 MA_DATA54 DDR_A_D55 <8> DDR_CKE1_DIMMA J20 H26 DDR_CKE1_DIMMB <9> AF15 AD15 MA_CKE1 MB_CKE1 DDR_B_D56 MB_DATA55 MA_DATA55 DDR_A_D56 AF13 MB_DATA56 MA_DATA56 AB13 N19 P22 DDR_B_D57 AC12 AD13 DDR_A_D57 MA_CLK_H5 MB_CLK_H5 DDR_B_D58 MB_DATA57 MA_DATA57 DDR_A_D58 N20 R22 AB11 Y12 DDR_A_CLK0 MA_CLK_L5 MB_CLK_L5 DDR_B_CLK0 DDR_B_D59 MB_DATA58 MA_DATA58 DDR_A_D59 <8> DDR_A_CLK0 E16 A17 DDR_B_CLK0 <9> Y11 W11 DDR_A_CLK#0 MA_CLK_H1 MB_CLK_H1 DDR_B_CLK#0 DDR_B_D60 MB_DATA59 MA_DATA59 DDR_A_D60 <8> DDR_A_CLK#0 F16 A18 DDR_B_CLK#0 <9> AE14 AB14 DDR_A_CLK1 MA_CLK_L1 MB_CLK_L1 DDR_B_CLK1 DDR_B_D61 MB_DATA60 MA_DATA60 DDR_A_D61 <8> DDR_A_CLK1 Y16 AF18 DDR_B_CLK1 <9> AF14 AA143 DDR_A_CLK#1 MA_CLK_H7 MB_CLK_H7 DDR_B_CLK#1 DDR_B_D62 MB_DATA61 MA_DATA61 DDR_A_D62 3 <8> DDR_A_CLK#1 AA16 MA_CLK_L7 MB_CLK_L7 AF17 DDR_B_CLK#1 <9> AF11 MB_DATA62 MA_DATA62 AB12 P19 R26 DDR_B_D63 AD11 AA12 DDR_A_D63 MA_CLK_H4 MB_CLK_H4 MB_DATA63 MA_DATA63 P20 R25 <9> DDR_B_DM[7..0] DDR_A_DM[7..0] <8> MA_CLK_L4 MB_CLK_L4 DDR_B_DM0 DDR_A_DM0 <8> DDR_A_MA[15..0] DDR_B_MA[15..0] <9> A12 MB_DM0 MA_DM0 E12 DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM1 B16 C15 DDR_A_DM1 DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM2 MB_DM1 MA_DM1 DDR_A_DM2 M20 N24 A22 E19 DDR_A_MA2 MA_ADD1 MB_ADD1 DDR_B_MA2 DDR_B_DM3 MB_DM2 MA_DM2 DDR_A_DM3 N22 P26 E25 F24 DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM4 MB_DM3 MA_DM3 DDR_A_DM4 M19 N23 AB26 AC24 DDR_A_MA4 MA_ADD3 MB_ADD3 DDR_B_MA4 DDR_B_DM5 MB_DM4 MA_DM4 DDR_A_DM5 M22 N26 AE22 Y19 DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM6 MB_DM5 MA_DM5 DDR_A_DM6 L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16 DDR_A_MA6 M24 N25 DDR_B_MA6 DDR_B_DM7 AD12 Y13 DDR_A_DM7 DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 MB_DM7 MA_DM7 L21 L24 DDR_A_MA8 MA_ADD7 MB_ADD7 DDR_B_MA8 DDR_B_DQS0 DDR_A_DQS0 L19 MA_ADD8 MB_ADD8 M26 <9> DDR_B_DQS0 C12 MB_DQS_H0 MA_DQS_H0 G13 DDR_A_DQS0 <8> DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0 MA_ADD9 MB_ADD9 <9> DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 <8> DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS1 D16 G16 DDR_A_DQS1 DDR_A_MA11 MA_ADD10 MB_ADD10 DDR_B_MA11 <9> DDR_B_DQS1 DDR_B_DQS#1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS#1 DDR_A_DQS1 <8> L22 L26 <9> DDR_B_DQS#1 C16 G15 DDR_A_DQS#1 <8> DDR_A_MA12 MA_ADD11 MB_ADD11 DDR_B_MA12 DDR_B_DQS2 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS2 K20 L25 <9> DDR_B_DQS2 A24 C22 DDR_A_DQS2 <8> DDR_A_MA13 MA_ADD12 MB_ADD12 DDR_B_MA13 DDR_B_DQS#2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS#2 V24 W24 <9> DDR_B_DQS#2 A23 C21 DDR_A_DQS#2 <8> DDR_A_MA14 MA_ADD13 MB_ADD13 DDR_B_MA14 DDR_B_DQS3 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS3 K24 J23 <9> DDR_B_DQS3 F26 G22 DDR_A_DQS3 <8> DDR_A_MA15 MA_ADD14 MB_ADD14 DDR_B_MA15 DDR_B_DQS#3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS#3 K19 J24 <9> DDR_B_DQS#3 E26 G21 DDR_A_DQS#3 <8> MA_ADD15 MB_ADD15 DDR_B_DQS4 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS4 <9> DDR_B_DQS4 AC25 AD23 DDR_A_DQS4 <8> DDR_A_BS#0 DDR_B_BS#0 DDR_B_DQS#4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS#4 <8> DDR_A_BS#0 R20 MA_BANK0 MB_BANK0 R24 DDR_B_BS#0 <9> <9> DDR_B_DQS#4 AC26 MB_DQS_L4 MA_DQS_L4 AC23 DDR_A_DQS#4 <8> DDR_A_BS#1 R23 U26 DDR_B_BS#1 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5 <8> DDR_A_BS#1 DDR_A_BS#2 MA_BANK1 MB_BANK1 DDR_B_BS#2 DDR_B_BS#1 <9> <9> DDR_B_DQS5 DDR_B_DQS#5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS#5 DDR_A_DQS5 <8> <8> DDR_A_BS#2 J21 MA_BANK2 MB_BANK2 J26 DDR_B_BS#2 <9> <9> DDR_B_DQS#5 AF22 MB_DQS_L5 MA_DQS_L5 AB20 DDR_A_DQS#5 <8> DDR_B_DQS6 AE16 Y15 DDR_A_DQS6 <9> DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 <8> DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6 <8> DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# <9> <9> DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 <8> DDR_A_CAS# T22 U24 DDR_B_CAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7 <8> DDR_A_CAS# DDR_A_WE# MA_CAS_L MB_CAS_L DDR_B_WE# DDR_B_CAS# <9> <9> DDR_B_DQS7 DDR_B_DQS#7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS#7 DDR_A_DQS7 <8> <8> DDR_A_WE# T24 U23 DDR_B_WE# <9> <9> DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7 <8> MA_WE_L MB_WE_L MB_DQS_L7 MA_DQS_L7 FOX_PZ6382A-284S-41F_GRIFFIN FOX_PZ6382A-284S-41F_GRIFFIN Athlon 64 S1 Athlon 64 S14 Processor Processor Socket 4 Socket CONN@ CONN@ Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD CPU S1G2 DDRII I/F AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 5 of 56 A B C D E
    • A B C D E +2.5VDDA VDDA=300mA L1 +2.5VS 1 2 3300P_0402_50V7K 1 2 02/27 Change net name to EN0. +1.8V 1 FBM_L11_201209_300L_0805 R10 10K_0402_5% @ R6 0_0402_5% 1 1 1 1 2 1 2 EN0 <37,39> @ C16 + R5 300_0402_5% 2 B 100U_D2_10VM 4.7U_0805_10V4Z C17 C18 C19 Q3 1 2 H_THERMTRIP#_EC <33> 0.22U_0603_16V4Z R16 0_0402_5% 2 2 2 2 E C CPU_THERMTRIP#_R 3 1 1 2 H_THERMTRIP# <20> PMBT3904_SOT23 R7 0_0402_5% JCPUD +1.8V 2 1 F8 M11 R11 @ 10K_0402_5%1 VDDA1 KEY1 1 Place close to CPU wihtin 1.5" F9 VDDA2 KEY2 W18 1 2 2 B R9 300_0402_5% @ MMBT3904_NL_SOT23-3 1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC Q2 <15> CLK_CPU_BCLK CLKIN_H SVC CPU_SVC <43> E C20 CPU_CLKIN_SC_N A8 A4 CPU_SVD CPU_PRO CHOT#_1.8 3 1 CLKIN_L SVD CPU_SVD <43> H_PROCHOT# <19> 1 C LDT_RST# 0718 Silego -- 216 ohm R8 H_PWRGD_CPU B7 A7 RESET_L 02/12 Remove R59. 1 @ R59 2 0_0402_5% 169_0402_1% LDT_STOP# PWROK CPU_THERMTRIP#_R F10 LDTSTOP_L THERMTRIP_L AF6 CPU_LDT_REQ# C6 AC7 CPU_PROCHOT#_1.8 R17 +1.8V 2 LDTREQ_L PROCHOT_L CPU_MEMHOT#_1.8V <15> CLK_CPU_BCLK# 1 2 AA8 2 1 +1.8V C21 3900P_0402_50V7K CPU_SIC MEMHOT_L R22 1K_0402_5% AF4 SIC Address:100_1100 CPU_SID AF5 @ 300_0402_5% CPU_SVC 1 2 SID THERMDC_CPU CPU_SVD AE6 ALERT_L THERMDC W7 1 2 W8 THERMDA_CPU R23 1K_0402_5% R13 THERMDA 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0 +1.2V_HT R14 1 2 44.2_0402_1% CPU_HTREF1 P6 HT_REF1 0718 AMD --> 1K ohm CPU_VDD0_FB_H <43> CPU_VDD0_FB_H <43> CPU_VDD0_FB_L CPU_VDD0_FB_L F6 E6 VDD0_FB_H VDDIO_FB_H W9 Y9 PAD PAD T42 T43 +1.8V sense no support VDD0_FB_L VDDIO_FB_L +CPU_CORE_NB CPU_VDD1_FB_H Y6 H6 VDD_NB_FB_H CPU_VDD1_FB_L AB6 VDD1_FB_H VDDNB_FB_H VDD_NB_FB_L VDD_NB_FB_H <43> G6 R484 10_0402_5% VDD1_FB_L VDDNB_FB_L VDD_NB_FB_L <43> VDD_NB_FB_H 1 2 CPU_DBRDY G10 VDD_NB_FB_L 1 2 CPU_TMS DBRDY CPU_DBREQ# R485 10_0402_5% AA9 E10 CPU_TCK TMS DBREQ_L AC9 TCK CPU_TRST# AD9 AE9 CPU_TDO Close to CPU CPU_TDI TRST_L TDO AF9 TDI +1.8VS T4 PAD CPU_TEST23_TSTUPD AD7 J7 CPU_TEST28_H_PLLCHRZ_P route as differential +CPU_CORE_0 TEST23 TEST28_H CPU_TEST28_L_PLLCHRZ_N PAD T5 TEST28_L H8 PAD T6 as short as possible R487 10_0402_5% CPU_TEST19_PLLTEST0 H10 testpoint under package TEST18 22 2 1 2 CPU_VDD0_FB_H CPU_TEST18_PLLTEST1 G9 TEST19 TEST17 D7 CPU_TEST17_BP3 PAD T7 R15 1 2 CPU_VDD0_FB_L E7 CPU_TEST16_BP2 PAD T8 R486 10_0402_5% T9 PAD CPU_TEST25_H_BYPASSCLK_H TEST16 CPU_TEST15_BP1 300_0402_5% E9 F7 PAD T10 T11 PAD CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST15 CPU_TEST14_BP0 E8 TEST25_L TEST14 C7 PAD T12 Close to CPU 1 LDT_RST# CPU_TEST21_SCANEN AB8 C3 <19> LDT_RST# TEST21 TEST7 CPU_TEST20_SCANCLK2 AF7 K8 +CPU_CORE_0 CPU_TEST24_SCANCLK1 TEST20 TEST10 1 AE7 C22 @ R489 10_0402_5% CPU_TEST22_SCANSHIFTEN TEST24 AE8 TEST22 TEST8 C4 0.01U_0402_25V4Z 1 2 CPU_VDD1_FB_H CPU_TEST12_SCANSHIFTENB AC8 TEST12 @ 1 2 CPU_VDD1_FB_L CPU_TEST27_SINGLECHAIN AF8 TEST27 2 CPU_TEST29_H_FBCLKOUT_P C9 PAD T13 @R488 10_0402_5% R25 TEST29_H CPU_TEST29_L_FBCLKOUT_N 1 2 0_0402_5% C2 TEST9 TEST29_L C8 PAD T14 AA6 TEST6 Reserve the R488 and R489 for S1G3 CPU A3 H18 +1.8VS RSVD1 RSVD10 A5 H19 RSVD2 RSVD9 B3 AA7 RSVD3 RSVD8 1 2 B5 D5 RSVD4 RSVD7 2 @ C1 C5 R21 @ C939 0.1U_0402_16V4Z RSVD5 RSVD6 300_0402_5% R175 @ R814 FOX_PZ6382A-284S-41F_GRIFFIN +3VS 2 1 2 1 CONN@ 1 H_PWRGD_CPU 2.09V for Gate <19> H_PWRGD_CPU 20K_0402_5% 34.8K_0402_1%~N 1 C23 02/15 Follow Trinity design. 2 G 0.1U_0402_16V7K 2 CPU_SID 3 1 SMB_EC_DA1 02/15 Change R18 and R19 SMB_EC_DA1 <32,33,34,37>3 R18 @ from 390 to 2.2K ohm. 3 S D +1.8V 2 1 Q127 2.2K_0402_5% FDV301N_NL_SOT23-3 +1.8VS R19 03/04 Reserve R175, R814, C939, Q127 and Q129. +1.8V 2 1 2 G 2.2K_0402_5% FDV301N_NL_SOT23-3 2 R36 CPU_SIC @ Q129 3 1 SMB_EC_CK1 SMB_EC_CK1 <32,33,34,37> +1.8V S D 300_0402_5% EC is PU to 5VALW 1 LDT_STOP# FDV301N, the Vgs is: <11,19> LDT_STOP# +1.8V CPU_TEST27_SINGLECHAIN min = 0.65V R24 1 2 @ 300_0402_5% 1 Typ = 0.85V C25 Max = 1.5V HDT Connector @ 220_0402_5% R37 @ 220_0402_5% R38 @ 220_0402_5% R39 @ 220_0402_5% R40 300_0402_5% R41 0.01U_0402_25V4Z CPU_TEST21_SCANEN R26 1 2 300_0402_5% @ +3VS CPU_TEST20_SCANCLK2 R27 2 1 @ 300_0402_5% 1 1 1 1 1 2 CPU_TEST24_SCANCLK1 R28 2 1 300_0402_5% CPU_TEST22_SCANSHIFTEN R29 2 1 @ 300_0402_5% JP3 CPU_TEST12_SCANSHIFTENB R31 2 1 @ 300_0402_5% 0.1U_0402_16V4Z 1 CPU_TEST15_BP1 R32 2 1 @ 300_0402_5% 1 2 CPU_TEST14_BP0 0718 AMD , need check with AMD R33 2 1 @ 300_0402_5% 2 2 2 2 2 C26 3 4 CPU_TEST19_PLLTEST0 R34 @ 300_0402_5% 2 1 CPU_DBREQ# 5 6 CPU_TEST18_PLLTEST1 R35 @ 300_0402_5% 7 8 2 1 +1.8VS 2 CPU_DBRDY U2 CPU_TCK 9 10 CPU_TMS 11 12 +3VS 1 VDD SCLK 8 SMB_EC_CK2 <33> 13 14 2 CPU_TDI R30 THERMDA_CPU 2 CPU_TRST# 15 16 C27 7 SMB_EC_DA2 <33> D+ SDATA 17 18 5 300_0402_5% CPU_TDO U1 THERMDC_CPU 3 19 20 LDT_RST# 6 2 P 100P_0402_25V8K D- ALERT# 21 22 HDT_RST# 4 B 14 CPU_LDT_REQ# 23 24 Y 4 CPU_LDT_REQ# <11,19> 4 5 1 SB_PWRGD <20,33,43> THERM# GND 26 A G 2200p change to NOTE: HDT TERMINATION IS REQUIRED 1 100p FOR REV. Ax SILICON ONLY. @ NC7SZ08P5X_NL_SC70-5 3 C24 ADM1032ARMZ-2REEL_MSOP8 CONN@ SAMTEC_ASP-68200-07 0.01U_0402_25V4Z 9/20 SP020016900 @ Address:100_1101 2 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD CPU S1G2 CTRL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 6 of 56 A B C D E
    • A B C D E 01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0 18A/720mil/36vias JCPUF VDD(+CPU_CORE) decoupling. L +CPU_CORE_0 +CPU_CORE_0 AA4 VSS1 VSS66 J6 JCPUE AA11 J8 VSS2 VSS67 01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0 AA13 VSS3 VSS68 J10 G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12 H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14 +CPU_CORE_0 +CPU_CORE_0 J9 R4 AA19 J16 VDD0_3 VDD1_3 VSS6 VSS71 J11 R7 AB2 J18 VDD0_4 VDD1_4 VSS7 VSS72 J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2 J15 R11 AB9 K7 VDD0_6 VDD1_6 VSS9 VSS74 1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9 K10 T6 AB25 K11 + C30 + C28 + C31 + C29 VDD0_8 VDD1_8 VSS11 VSS76 K12 VDD0_9 VDD1_9 T8 AC11 VSS12 VSS77 K131 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 1 K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15 L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17 2 2 2 2 L7 T14 AC17 L6 VDD0_12 VDD1_12 VSS15 VSS80 L9 U7 AC19 L8 VDD0_13 VDD1_13 VSS16 VSS81 Near CPU Socket L11 L13 VDD0_14 VDD0_15 VDD1_14 VDD1_15 U9 U11 AC21 AD6 VSS17 VSS18 VSS82 VSS83 L10 L12 L15 U13 AD8 L14 VDD0_16 VDD1_16 VSS19 VSS84 Tigris platform will be 4A M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16 M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18 M8 V8 AE13 M7 +CPU_CORE_0 VDD0_19 VDD1_19 VSS22 VSS87 M10 VDD0_20 VDD1_20 V10 AE15 VSS23 VSS88 M9 +CPU_CORE_0 L 4A/160mil/8vias N7 VDD0_21 VDD1_21 V12 AE17 VSS24 VSS89 AC6 N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17 +CPU_CORE_NB N11 W4 AE21 N4 VDD0_23 VDD1_23 VSS26 VSS91 1 1 1 1 Y2 AE23 N8 C32 C33 C34 C35 VDD1_24 VSS27 VSS92 1 1 1 1 K16 AC4 B4 N10 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C36 C37 C38 C39 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93 M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 B8 N18 2 2 2 2 VDDNB_3 VSS30 VSS95 T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2 2 2 2 2 +1.8V V16 V25 B11 P7 VDDNB_5 VDDIO26 VSS32 VSS97 V23 B13 P9 +CPU_CORE_0 VDDIO25 VSS33 VSS98 H25 V21 B15 P11 +CPU_CORE_0 VDDIO1 VDDIO24 VSS34 VSS99 J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17 K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8 L 3A/120mil/6vias K21 VDDIO4 VDDIO21 T25 B21 VSS37 VSS102 R10 1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16 C40 C41 C42 C43 C44 C45 K25 T21 B25 R18 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104 L17 T18 D6 T7 VDDIO7 VDDIO18 VSS40 VSS105 M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9 2 2 2 2 2 2 M21 P25 D9 T11 VDDIO9 VDDIO16 VSS42 VSS107 Under CPU Socket M23 M25 VDDIO10 VDDIO11 VDDIO15 VDDIO14 P23 P21 D11 D13 VSS43 VSS44 VSS108 VSS109 T13 T152 2 N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17 D17 U4 VSS46 VSS111 D19 U6 FOX_PZ6382A-284S-41F_GRIFFIN VSS47 VSS112 D21 VSS48 VSS113 U8 Athlon 64 S1 D23 U10 Processor Socket VSS49 VSS114 D25 U12 CONN@ VSS50 VSS115 E4 VSS51 VSS116 U14 F2 U16 VSS52 VSS117 F11 VSS53 VSS118 U18 F13 V2 VSS54 VSS119 F15 V7 +CPU_CORE_NB decoupling. F17 F19 VSS55 VSS56 VSS57 VSS120 VSS121 VSS122 V9 V11 F21 V13 VDDIO decoupling. +CPU_CORE_NB F23 F25 VSS58 VSS59 VSS60 VSS123 VSS124 VSS125 V15 V17 H7 W6 VSS61 VSS126 H9 Y21 VSS62 VSS127 1 1 1 @ H21 VSS63 VSS128 Y23 +1.8V C52 C53 C54 H23 N6 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VSS64 VSS129 J4 VSS65 2 2 2 FOX_PZ6382A-284S-41F_GRIFFIN 1 1 1 1 1 1 Athlon 64 S1 C46 C47 C48 C49 C50 C51 Processor Socket 22U_0805_6.3V6M 22U_0805_6.3V6M CONN@ 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 2 2 2 2 2 2 +0.9V3 Under CPU Socket Near Power Supply 3 VTT decoupling. 1 C: Change to NBO CAP + C59 220U_Y_4VM 2 Between CPU Socket and DIMM +1.8V +0.9V 1 1 1 1 C55 C56 C57 C58 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 2 2 2 2 1 1 1 1 1 1 1 1 C66 C67 C68 C69 C70 C71 C72 C73 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J 180PF Qty follow the distance between 2 2 2 2 2 2 2 2 +1.8V +1.8V CPU socket and DIMM0. <2.5inch> 1 1 1 1 1 1 Near CPU Socket Right side. C60 C61 C62 C63 C64 C65 +0.9V 0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 2 2 2 2 2 2 A: Add C165 and C176 1 1 1 1 1 1 1 1 to follow AMD Layout C79 C80 C81 C82 C83 C84 C85 C86 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J +1.8V review recommand for EMI 2 2 2 2 2 2 2 24 4 1 C: Change to NBO CAP 1 1 1 1 + C78 Near CPU Socket Left side. C74 C75 C76 C77 220U_Y_4VM 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 2 2 2 2 2 @ Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD CPU S1G2 PWR & GND Size Document Number R ev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 7 of 56 A B C D E
    • A B C D E +V_DDR_MCH_REF +1.8V JP4 +1.8V +0.9V +1.8V 1 2 RP1 VREF VSS DDR_A_D4 D DR_A_D[0..63] DDR_A_MA14 3 VSS DQ4 4 DDR_A_D[0..63] <5> 8 1 1 2 DDR_A_D0 5 6 DDR_A_D5 DDR_A_MA11 7 2 C87 0.1U_0402_16V4Z DDR_A_D1 DQ0 DQ5 DDR_A_DM[0..7] DDR_A_MA7 7 DQ1 VSS 8 DDR_A_DM[0..7] <5> 6 3 1 2 9 10 DDR_A_DM0 DDR_A_MA6 5 4 C88 0.1U_0402_16V4Z DDR_A_DQS#0 VSS DM0 D DR_A_DQS[0..7] 11 DQS0# VSS 121 DDR_A_DQS0 DDR_A_D6 DDR_A_DQS[0..7] <5> 47_0804_8P4R_5% 1 13 DQS0 DQ6 14 15 16 DDR_A_D7 DDR_A_MA[0..15] RP2 VSS DQ7 DDR_A_MA[0..15] <5> DDR_A_D2 17 18 DDR_CKE0_DIMMA 8 1 1 2 DDR_A_D3 DQ2 VSS DDR_A_D12 DDR_A_DQS#[0..7] DDR_A_BS#2 C90 0.1U_0402_16V4Z 19 20 7 2 DQ3 DQ12 DDR_A_D13 DDR_A_DQS#[0..7] <5> DDR_CKE1_DIMMA 21 22 6 3 1 2 DDR_A_D8 VSS DQ13 DDR_A_MA15 C89 0.1U_0402_16V4Z 23 DQ8 VSS 24 5 4 DDR_A_D9 25 26 DDR_A_DM1 DQ9 DM1 47_0804_8P4R_5% 27 VSS VSS 28 DDR_A_DQS#1 29 30 RP3 DQS1# CK0 DDR_A_CLK0 <5> DDR_A_DQS1 31 32 DDR_A_MA4 8 1 1 2 DQS1 CK0# DDR_A_CLK#0 <5> DDR_A_MA2 33 34 7 2 C91 0.1U_0402_16V4Z DDR_A_D10 VSS VSS DDR_A_D14 DDR_A_BS#1 35 36 6 3 1 2 DDR_A_D11 DQ10 DQ14 DDR_A_D15 +1.8V DDR_A_MA0 C92 0.1U_0402_16V4Z 37 DQ11 DQ15 38 5 4 39 40 VSS VSS 47_0804_8P4R_5% 2 RP4 41 42 R43 DDR_A_MA5 8 1 1 2 DDR_A_D16 VSS VSS DDR_A_D20 1K_0402_1% DDR_A_MA8 C93 0.1U_0402_16V4Z 43 44 7 2 DDR_A_D17 DQ16 DQ20 DDR_A_D21 DDR_A_MA9 45 DQ17 DQ21 46 6 3 1 2 47 48 DDR_A_MA12 5 4 C94 0.1U_0402_16V4Z 1 DDR_A_DQS#2 VSS VSS +V_DDR_MCH_REF 49 50 +V_DDR_MCH_REF <9> DDR_A_DQS2 DQS2# NC DDR_A_DM2 47_0804_8P4R_5% 51 52 DQS2 DM2 RP5 53 VSS VSS 54 1 1 2 DDR_A_D18 55 56 DDR_A_D22 C95 C96 DDR_A_BS#0 8 1 1 2 DDR_A_D19 DQ18 DQ22 DDR_A_D23 R44 DDR_A_MA10 C98 0.1U_0402_16V4Z 57 58 7 2 DQ19 DQ23 1K_0402_1% DDR_A_MA1 59 VSS VSS 60 6 3 1 2 DDR_A_D24 61 62 DDR_A_D28 2 2 DDR_A_MA3 5 4 C97 0.1U_0402_16V4Z DDR_A_D25 DQ24 DQ28 DDR_A_D29 1000P_0402_25V8J 63 64 1 DQ25 DQ29 47_0804_8P4R_5% 65 VSS VSS 66 DDR_A_DM3 67 68 DDR_A_DQS#3 0.1U_0402_16V4Z RP6 DM3 DQS3# DDR_A_DQS3 DDR_A_ODT1 69 70 8 1 1 2 NC DQS3 DDR_CS1_DIMMA# C100 0.1U_0402_16V4Z 71 72 7 22 DDR_A_D26 VSS VSS DDR_A_D30 DDR_A_WE# 2 73 DQ26 DQ30 74 6 3 1 2 DDR_A_D27 75 76 DDR_A_D31 DDR_A_CAS# 5 4 C99 0.1U_0402_16V4Z DQ27 DQ31 77 78 DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA 47_0804_8P4R_5% <5> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <5> 81 82 RP7 VDD VDD DDR_A_MA15 DDR_CS0_DIMMA# 83 84 8 1 1 2 DDR_A_BS#2 NC NC/A15 DDR_A_MA14 DDR_A_RAS# C102 0.1U_0402_16V4Z <5> DDR_A_BS#2 85 BA2 NC/A14 86 7 2 87 88 DDR_A_MA13 6 3 1 2 DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_ODT0 C101 0.1U_0402_16V4Z 89 A12 A11 90 5 4 DDR_A_MA9 91 92 DDR_A_MA7 DDR_A_MA8 A9 A7 DDR_A_MA6 47_0804_8P4R_5% 93 A8 A6 94 95 VDD VDD 96 Cross between +1.8V and +0.9V power plan DDR_A_MA5 97 98 DDR_A_MA4 DDR_A_MA3 A5 A4 DDR_A_MA2 99 100 DDR_A_MA1 A3 A2 DDR_A_MA0 101 102 A1 A0 103 104 DDR_A_MA10 VDD VDD DDR_A_BS#1 105 106 DDR_A_BS#1 <5> DDR_A_BS#0 A10/AP BA1 DDR_A_RAS# <5> DDR_A_BS#0 107 108 DDR_A_RAS# <5> DDR_A_WE# BA0 RAS# DDR_CS0_DIMMA# <5> DDR_A_WE# 109 110 DDR_CS0_DIMMA# <5> WE# S0# 111 VDD VDD 112 DDR_A_CAS# 113 114 DDR_A_ODT0 <5> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <5> DDR_CS1_DIMMA# 115 116 DDR_A_MA13 <5> DDR_CS1_DIMMA# NC/S1# NC/A13 117 118 DDR_A_ODT1 VDD VDD <5> DDR_A_ODT1 119 120 NC/ODT1 NC 121 122 DDR_A_D32 VSS VSS DDR_A_D36 123 124 DDR_A_D33 DQ32 DQ36 DDR_A_D37 125 DQ33 DQ37 126 127 128 DDR_A_DQS#4 VSS VSS DDR_A_DM4 129 130 DDR_A_DQS4 DQS4# DM4 131 132 DQS4 VSS DDR_A_D38 133 134 DDR_A_D34 VSS DQ38 DDR_A_D39 135 1363 DDR_A_D35 DQ34 DQ39 3 137 DQ35 VSS 138 139 140 DDR_A_D44 DDR_A_D40 VSS DQ44 DDR_A_D45 141 142 DDR_A_D41 DQ40 DQ45 143 DQ41 VSS 144 145 146 DDR_A_DQS#5 DDR_A_DM5 VSS DQS5# DDR_A_DQS5 147 148 DM5 DQS5 149 150 DDR_A_D42 VSS VSS DDR_A_D46 151 152 DDR_A_D43 DQ42 DQ46 DDR_A_D47 153 154 DQ43 DQ47 155 VSS VSS 156 DDR_A_D48 157 158 DDR_A_D52 DDR_A_D49 DQ48 DQ52 DDR_A_D53 159 160 DQ49 DQ53 161 VSS VSS 162 163 164 DDR_A_CLK1 <5> NC,TEST CK1 165 VSS CK1# 166 DDR_A_CLK#1 <5> DDR_A_DQS#6 167 168 DDR_A_DQS6 DQS6# VSS DDR_A_DM6 169 170 DQS6 DM6 171 172 DDR_A_D50 VSS VSS DDR_A_D54 173 174 DDR_A_D51 DQ50 DQ54 DDR_A_D55 175 176 DQ51 DQ55 177 178 DDR_A_D56 VSS VSS DDR_A_D60 179 DQ56 DQ60 180 DDR_A_D57 181 182 DDR_A_D61 DQ57 DQ61 183 VSS VSS 184 DDR_A_DM7 185 186 DDR_A_DQS#7 DM7 DQS7# DDR_A_DQS7 187 188 DDR_A_D58 VSS DQS7 189 DQ58 VSS 190 DDR_A_D59 191 192 DDR_A_D62 DQ59 DQ62 DDR_A_D63 193 194 VSS DQ63 <9,15,20,30> SMB_CK_DAT0 195 196 SDA VSS <9,15,20,30> SMB_CK_CLK0 197 198 SCL SA0 +3VS 199 VDDSPD SA1 2004 4 1 C103 FOX_AS0A426-N8RN-7F 0.1U_0402_16V4Z CONN@ 2 9/20 SP07000BZ00/SP07000EU00 DDR2 SOCKET H9.2 (REV) Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DDRII SO-DIMM 0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 8 of 56 A B C D E
    • A B C D E +1.8V +1.8V +0.9V +1.8V JP5 RP8 1 2 D DR_B_D[0..63] DDR_B_MA6 8 1 2 1 <8> +V_DDR_MCH_REF VREF VSS DDR_B_D4 DDR_B_D[0..63] <5> DDR_B_MA2 3 4 7 2 C105 0.1U_0402_16V4Z DDR_B_D0 VSS DQ4 DDR_B_D5 DDR_B_DM[0..7] DDR_B_MA0 5 6 DDR_B_DM[0..7] <5> 6 3 1 2 DDR_B_D1 DQ0 DQ5 DDR_CS0_DIMMB# C106 0.1U_0402_16V4Z 7 DQ1 VSS 8 5 4 1 9 10 DDR_B_DM0 D DR_B_DQS[0..7] C104 DDR_B_DQS#0 VSS DM0 DDR_B_DQS[0..7] <5> 47_0804_8P4R_5% 11 DQS0# VSS 12 DDR_B_DQS0 13 14 DDR_B_D6 DDR_B_MA[0..15] DQS0 DQ6 DDR_B_MA[0..15] <5> 15 16 DDR_B_D7 RP91 2 DDR_B_D2 VSS DQ7 DDR_B_DQS#[0..7] DDR_B_MA14 1 17 DQ2 VSS 18 DDR_B_DQS#[0..7] <5> 8 1 2 1 1000P_0402_25V8J DDR_B_D3 19 20 DDR_B_D12 DDR_B_MA11 7 2 C108 0.1U_0402_16V4Z DQ3 DQ12 DDR_B_D9 DDR_B_MA7 21 VSS DQ13 22 6 3 1 2 DDR_B_D8 23 24 DDR_B_MA4 5 4 C107 0.1U_0402_16V4Z DDR_B_D13 DQ8 VSS DDR_B_DM1 25 26 DQ9 DM1 47_0804_8P4R_5% 27 VSS VSS 28 DDR_B_DQS#1 29 30 DDR_B_DQS1 DQS1# CK0 DDR_B_CLK0 <5> 31 32 RP10 DQS1 CK0# DDR_B_CLK#0 <5> DDR_CKE1_DIMMB 33 VSS VSS 34 8 1 2 1 DDR_B_D10 35 36 DDR_B_D14 DDR_B_MA15 7 2 C109 0.1U_0402_16V4Z DDR_B_D11 DQ10 DQ14 DDR_B_D15 DDR_CKE0_DIMMB 37 DQ11 DQ15 38 6 3 1 2 39 40 DDR_B_BS#2 5 4 C110 0.1U_0402_16V4Z VSS VSS 47_0804_8P4R_5% 41 42 DDR_B_D21 VSS VSS DDR_B_D20 RP11 43 44 DDR_B_D17 DQ16 DQ20 DDR_B_D16 DDR_B_MA5 45 DQ17 DQ21 46 8 1 2 1 47 48 DDR_B_MA8 7 2 C111 0.1U_0402_16V4Z DDR_B_DQS#2 VSS VSS DDR_B_MA9 49 DQS2# NC 50 6 3 1 2 DDR_B_DQS2 51 52 DDR_B_DM2 DDR_B_MA12 5 4 C112 0.1U_0402_16V4Z DQS2 DM2 53 54 DDR_B_D18 VSS VSS DDR_B_D22 47_0804_8P4R_5% 55 56 DDR_B_D19 DQ18 DQ22 DDR_B_D23 57 DQ19 DQ23 58 59 60 RP12 DDR_B_D24 VSS VSS DDR_B_D28 DDR_B_MA10 61 62 8 1 2 1 DDR_B_D25 DQ24 DQ28 DDR_B_D29 DDR_B_BS#0 C114 0.1U_0402_16V4Z 63 DQ25 DQ29 64 7 2 65 66 DDR_B_MA1 6 3 1 2 DDR_B_DM3 VSS VSS DDR_B_DQS#3 DDR_B_MA3 C113 0.1U_0402_16V4Z 67 68 5 4 DM3 DQS3# DDR_B_DQS3 69 NC DQS3 70 71 72 47_0804_8P4R_5% DDR_B_D26 VSS VSS DDR_B_D30 73 74 DDR_B_D27 DQ26 DQ30 DDR_B_D31 RP13 75 762 DQ27 DQ31 DDR_B_ODT1 2 77 VSS VSS 78 8 1 2 1 DDR_CKE0_DIMMB 79 80 DDR_CKE1_DIMMB DDR_CS1_DIMMB# 7 2 C116 0.1U_0402_16V4Z <5> DDR_CKE0_DIMMB CKE0 NC/CKE1 DDR_CKE1_DIMMB <5> DDR_B_CAS# 81 82 6 3 1 2 VDD VDD DDR_B_MA15 DDR_B_WE# C115 0.1U_0402_16V4Z 83 NC NC/A15 84 5 4 DDR_B_BS#2 85 86 DDR_B_MA14 <5> DDR_B_BS#2 BA2 NC/A14 87 88 47_0804_8P4R_5% DDR_B_MA12 VDD VDD DDR_B_MA11 89 A12 A11 90 DDR_B_MA9 91 92 DDR_B_MA7 RP14 DDR_B_MA8 A9 A7 DDR_B_MA6 DDR_B_RAS# 93 A8 A6 94 8 1 2 1 95 96 DDR_B_BS#1 7 2 C118 0.1U_0402_16V4Z DDR_B_MA5 VDD VDD DDR_B_MA4 DDR_B_ODT0 97 A5 A4 98 6 3 1 2 DDR_B_MA3 99 100 DDR_B_MA2 DDR_B_MA13 5 4 C117 0.1U_0402_16V4Z DDR_B_MA1 A3 A2 DDR_B_MA0 101 A1 A0 102 103 104 47_0804_8P4R_5% DDR_B_MA10 VDD VDD DDR_B_BS#1 105 A10/AP BA1 106 DDR_B_BS#1 <5> Cross between +1.8V and +0.9V power plan DDR_B_BS#0 107 108 DDR_B_RAS# <5> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <5> DDR_B_WE# 109 110 DDR_CS0_DIMMB# <5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5> 111 112 DDR_B_CAS# VDD VDD DDR_B_ODT0 <5> DDR_B_CAS# 113 114 DDR_B_ODT0 <5> DDR_CS1_DIMMB# CAS# ODT0 DDR_B_MA13 <5> DDR_CS1_DIMMB# 115 NC/S1# NC/A13 116 117 118 DDR_B_ODT1 VDD VDD <5> DDR_B_ODT1 119 120 NC/ODT1 NC 121 122 DDR_B_D32 VSS VSS DDR_B_D36 123 124 DDR_B_D33 DQ32 DQ36 DDR_B_D37 125 126 DQ33 DQ37 127 128 DDR_B_DQS#4 VSS VSS DDR_B_DM4 129 DQS4# DM4 130 DDR_B_DQS4 131 132 DQS4 VSS DDR_B_D38 133 134 DDR_B_D34 VSS DQ38 DDR_B_D39 135 136 DDR_B_D35 DQ34 DQ39 137 138 DQ35 VSS DDR_B_D44 139 1403 DDR_B_D40 VSS DQ44 DDR_B_D45 3 141 DQ40 DQ45 142 DDR_B_D41 143 144 DQ41 VSS DDR_B_DQS#5 145 146 DDR_B_DM5 VSS DQS5# DDR_B_DQS5 147 DM5 DQS5 148 149 150 DDR_B_D42 VSS VSS DDR_B_D46 151 152 DDR_B_D43 DQ42 DQ46 DDR_B_D47 153 154 DQ43 DQ47 155 156 DDR_B_D48 VSS VSS DDR_B_D52 157 158 DDR_B_D49 DQ48 DQ52 DDR_B_D53 159 DQ49 DQ53 160 161 VSS VSS 162 163 164 DDR_B_CLK1 <5> NC,TEST CK1 165 VSS CK1# 166 DDR_B_CLK#1 <5> DDR_B_DQS#6 167 168 DDR_B_DQS6 DQS6# VSS DDR_B_DM6 169 DQS6 DM6 170 171 172 DDR_B_D50 VSS VSS DDR_B_D54 173 174 DDR_B_D51 DQ50 DQ54 DDR_B_D55 175 176 DQ51 DQ55 177 178 DDR_B_D56 VSS VSS DDR_B_D60 179 180 DDR_B_D57 DQ56 DQ60 DDR_B_D61 181 182 DQ57 DQ61 183 VSS VSS 184 DDR_B_DM7 185 186 DDR_B_DQS#7 DM7 DQS7# DDR_B_DQS7 187 VSS DQS7 188 DDR_B_D58 189 190 DDR_B_D59 DQ58 VSS DDR_B_D62 191 192 DQ59 DQ62 DDR_B_D63 193 VSS DQ63 194 <8,15,20,30> SMB_CK_DAT0 195 196 SDA VSS <8,15,20,30> SMB_CK_CLK0 197 198 +3VS SCL SAO 199 200 +3VS VDDSPD SA1 1 201 202 GND GND4 C119 TYCO_292527-4 4 0.1U_0402_16V4Z CONN@ 2 9/20 SP07000ET00/SP07000GN00 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DDRII SO-DIMM 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 9 of 56 A B C D E
    • A B C D E U3B D4 GFX_RX0P GFX_TX0P A5 TMDS_B_DATA2 <18> C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 TMDS_B_DATA2# <18> A3 GFX_RX1P GFX_TX1P A4 TMDS_B_DATA1 <18> B3 GFX_RX1N GFX_TX1N B4 TMDS_B_DATA1# <18> C2 C3 TMDS_B_DATA0 <18> GFX_RX2P GFX_TX2P C1 GFX_RX2N GFX_TX2N B2 TMDS_B_DATA0# <18> E5 D1 TMDS_B_CLK <18> GFX_RX3P GFX_TX3P F5 GFX_RX3N GFX_TX3N D2 TMDS_B_CLK# <18> G5 E2 GFX_RX4P GFX_TX4P G6 GFX_RX4N GFX_TX4N E11 1 H5 GFX_RX5P GFX_TX5P F4 H6 GFX_RX5N GFX_TX5N F3 J6 GFX_RX6P GFX_TX6P F1 J5 F2 GFX_RX6N GFX_TX6N J7 H4 GFX_RX7P GFX_TX7P J8 GFX_RX7N GFX_TX7N H3 L5 H1 GFX_RX8P GFX_TX8P L6 GFX_RX8N GFX_TX8N H2 M8 GFX_RX9P GFX_TX9P J2 L8 J1 GFX_RX9N GFX_TX9N P7 K4 PCIE I/F GFX GFX_RX10P GFX_TX10P M7 K3 GFX_RX10N GFX_TX10N P5 GFX_RX11P GFX_TX11P K1 M5 K2 GFX_RX11N GFX_TX11N R8 M4 GFX_RX12P GFX_TX12P P8 M3 GFX_RX12N GFX_TX12N R6 GFX_RX13P GFX_TX13P M1 R5 M2 GFX_RX13N GFX_TX13N P4 GFX_RX14P GFX_TX14P N2 P3 N1 GFX_RX14N GFX_TX14N T4 P1 GFX_RX15P GFX_TX15P T3 P2 GFX_RX15N GFX_TX15N AE3 AC1 PCIE_ITX_PRX_P0 C152 1 2 0.1U_0402_16V7K New Card <26> PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_PRX_N0 PCIE_ITX_C_PRX_P0 <26> AD4 AC2 C153 1 2 0.1U_0402_16V7K <26> PCIE_PTX_C_IRX_N0 GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 <26> AE2 AB4 PCIE_ITX_PRX_P1 C154 1 2 0.1U_0402_16V7K CardReader <27> PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_PRX_N1 PCIE_ITX_C_PRX_P1 <27> AD3 AB3 C155 1 2 0.1U_0402_16V7K <27> PCIE_PTX_C_IRX_N1 GPP_RX1N GPP_TX1N PCIE_ITX_PRX_P2 PCIE_ITX_C_PRX_N1 <27> AD1 AA2 C156 1 2 0.1U_0402_16V7K <26> PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 <26> AD2 PCIE I/F GPP GPP_TX2N AA1 PCIE_ITX_PRX_N2 C157 1 2 0.1U_0402_16V7K WLAN <26> PCIE_PTX_C_IRX_N2 GPP_RX2N PCIE_ITX_C_PRX_N2 <26> V5 Y1 PCIE_ITX_PRX_P3 C158 1 2 0.1U_0402_16V7K <25> PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_PRX_N3 PCIE_ITX_C_PRX_P3 <25> <25> PCIE_PTX_C_IRX_N3 W6 GPP_RX3N GPP_TX3N Y2 C159 1 2 0.1U_0402_16V7K PCIE_ITX_C_PRX_N3 <25> LAN10/100 U5 Y42 GPP_RX4P GPP_TX4P H_CADOP[0..15] H_CADIP[0..15] 2 U6 GPP_RX4N GPP_TX4N Y3 <4> H_CADOP[0..15] H_CADIP[0..15] <4> U8 V1 PCIE_ITX_PRX_P5 C160 1 2 0.1U_0402_16V7K <26> PCIE_PTX_C_IRX_P5 GPP_RX5P GPP_TX5P PCIE_ITX_PRX_N5 PCIE_ITX_C_PRX_P5 <26> H_CADON[0..15] H_CADIN[0..15] <26> PCIE_PTX_C_IRX_N5 U7 GPP_RX5N GPP_TX5N V2 C161 1 2 0.1U_0402_16V7K PCIE_ITX_C_PRX_N5 <26> TV Tuner<4> H_CADON[0..15] H_CADIN[0..15] <4> <19> SB_RX0P AA8 AD7 SB_TX0P_C C162 1 2 0.1U_0402_16V7K SB_RX0P SB_TX0P SB_TX0N_C SB_TX0P <19> <19> SB_RX0N Y8 AE7 C163 1 2 0.1U_0402_16V7K SB_RX0N SB_TX0N SB_TX0N <19> <19> SB_RX1P AA7 AE6 SB_TX1P_C C164 1 2 0.1U_0402_16V7K SB_RX1P SB_TX1P SB_TX1P <19> <19> SB_RX1N Y7 AD6 SB_TX1N_C C165 1 2 0.1U_0402_16V7K U3A SB_RX1N SB_TX1N SB_TX2P_C SB_TX1N <19> H_CADOP0 H_CADIP0 <19> SB_RX2P AA5 PCIE I/F SB AB6 C166 1 2 0.1U_0402_16V7K Y25 D24 SB_RX2P SB_TX2P SB_TX2N_C SB_TX2P <19> H_CADON0 HT_RXCAD0P HT_TXCAD0P H _CADIN0 <19> SB_RX2N AA6 AC6 C168 1 2 0.1U_0402_16V7K Y24 PART 1 OF 6 D25 SB_RX2N SB_TX2N SB_TX3P_C SB_TX2N <19> H_CADOP1 HT_RXCAD0N HT_TXCAD0N H_CADIP1 <19> SB_RX3P W5 AD5 C169 1 2 0.1U_0402_16V7K V22 E24 SB_RX3P SB_TX3P SB_TX3P <19> HT_RXCAD1P HT_TXCAD1P <19> SB_RX3N Y5 AE5 SB_TX3N_C C167 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H _CADIN1 SB_RX3N SB_TX3N SB_TX3N <19> HT_RXCAD1N HT_TXCAD1N H_CADOP2 V25 F24 H_CADIP2 R55 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H _CADIN2 AC8 1 2 V24 F25 PCE_CALRP(PCE_BCALRP) R56 2K_0402_1% H_CADOP3 HT_RXCAD2N HT_TXCAD2N H_CADIP3 AB8 1 2 +1.1VS U24 F23 PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H _CADIN3 U25 F22 H_CADOP4 HT_RXCAD3N HT_TXCAD3N H_CADIP4 RS880M_FCBGA528 H_CADON4 T25 HT_RXCAD4P HT_TXCAD4P H23 H _CADIN4 T24 H22 H_CADOP5 HT_RXCAD4N HT_TXCAD4N H_CADIP5 RS780M Display Port Support (muxed on GFX) P22 HT_RXCAD5P HT_TXCAD5P J25 H_CADON5 P23 J24 H _CADIN5 HYPER TRANSPORT CPU I/F H_CADOP6 HT_RXCAD5N HT_TXCAD5N H_CADIP6 P25 K24 GFX_TX0,TX1,TX2 and TX3 H_CADON6 HT_RXCAD6P HT_TXCAD6P H _CADIN6 P24 K25 DP0 H_CADOP7 HT_RXCAD6N HT_TXCAD6N H_CADIP7 N24 K23 AUX0 and HPD0 H_CADON7 HT_RXCAD7P HT_TXCAD7P H _CADIN7 N25 K22 HT_RXCAD7N HT_TXCAD7N H_CADOP8 AC24 F21 H_CADIP8 GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H _CADIN8 AC25 HT_RXCAD8N HT_TXCAD8N G21 DP1 H_CADOP9 AB25 G20 H_CADIP9 AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H _CADIN9 AB24 H21 H_CADOP10 HT_RXCAD9N HT_TXCAD9N H_CADIP10 AA24 J20 H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10 AA25 J21 H_CADOP11 HT_RXCAD10N HT_TXCAD10N H_CADIP11 9/20 SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH Y22 J183 H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11 3 Y23 HT_RXCAD11N HT_TXCAD11N K17 H_CADOP12 W21 L19 H_CADIP12 H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12 W20 J19 H_CADOP13 HT_RXCAD12N HT_TXCAD12N H_CADIP13 V21 HT_RXCAD13P HT_TXCAD13P M19 H_CADON13 V20 L18 H_CADIN13 H_CADOP14 HT_RXCAD13N HT_TXCAD13N H_CADIP14 U20 M21 H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14 U21 P21 H_CADOP15 HT_RXCAD14N HT_TXCAD14N H_CADIP15 U19 P18 H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15 U18 M18 HT_RXCAD15N HT_TXCAD15N <4> H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 <4> <4> H_CLKON0 T23 H25 H_CLKIN0 <4> HT_RXCLK0N HT_TXCLK0N <4> H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 <4> <4> H_CLKON1 AA22 L20 H_CLKIN1 <4> HT_RXCLK1N HT_TXCLK1N H_CTLOP0 M22 M24 H_CTLIP0 <4> H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 <4> H_CTLON0 M23 M25 H_CTLIN0 <4> H_CTLON0 H_CTLOP1 HT_RXCTL0N HT_TXCTL0N H_CTLIP1 H_CTLIN0 <4> <4> H_CTLOP1 R21 P19 H_CTLIP1 <4> H_CTLON1 HT_RXCTL1P HT_TXCTL1P H_CTLIN1 <4> H_CTLON1 R20 R18 H_CTLIN1 <4> HT_RXCTL1N HT_TXCTL1N 1 R57 2 301_0402_1% C23 B24 1 R58 2 301_0402_1% HT_RXCALP HT_TXCALP A24 HT_RXCALN HT_TXCALN B25 0718 Place within 1" RS880M_FCBGA528 0718 Place within 1" layout 1:2 layout 1:2 NEED CHECK R68 & R69 WITH AMD4 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL RS880-HT/PCIE Size Document Number R ev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 10 of 56 A B C D E
    • A B C D E1 1 +3VS L2 AVDD=100mA 1 2 +AVDD1 +1.8VS BLM18PG121SN1D_0603 1 L4 +AVDD2 C170 +1.8VS 0_0603_5% 2.2U_0603_6.3V4Z R67 1 2 L6 1 2 NB_LDTSTOP# 1 2 +AVDDQ C172 <6,19> LDT_STOP# BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z U3C 0_0402_5% 2 1 F12 A22 LVDS_A0+ <17> AVDD1(NC) TXOUT_L0P(NC) E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 LVDS_A0- <17> C175 F14 AVDDDI(NC) A21 LVDS_A1+ <17> 2.2U_0603_6.3V4Z TXOUT_L1P(NC) R68 G15 B21 LVDS_A1- <17> 2 AVSSDI(NC) TXOUT_L1N(NC) H15 AVDDQ(NC) TXOUT_L2P(NC) B20 LVDS_A2+ <17> 1 2 NB_ALLOW_LDTSTOP H14 A20 LVDS_A2- <17> <6,19> CPU_LDT_REQ# AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A19 0_0402_5% T46 PAD TV_CRMA TXOUT_L3P(NC) E17 B19 T47 PAD TV_LUMA C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) F17 CRT/TVOUT T48 PAD TV_COMPS Y(DFT_GPIO2) F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 1 2 R ED A18 PA_RS780A4 @ R62 150_0402_1% R ED TXOUT_U0N(NC) <16> RED G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17 1 2 GREEN G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17 placement close to NB ball @ R63 150_0402_1% GREEN E18 D20 <16> GREEN GREEN(DFT_GPIO1) TXOUT_U2P(NC) 1 2 BLUE F18 D21 @ R64 150_0402_1% BLUE GREENb(NC) TXOUT_U2N(NC) <16> BLUE E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18 F19 D19 BLUEb(NC) TXOUT_U3N(NC)2 +1.1VS L9 CR T_HSYNC A11 B16 2 <14,16> CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) LVDS_ACLK+ <17> 1 2 CRT_VSYNC B11 A16 LVDS_ACLK- <17> <14,16> CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) BLM18PG121SN1D_0603 1 F8 D16 +1.8VS <16> UMA_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4) L7 C178 E8 D17 <16> UMA_CRT_DAT DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) 1 2 BLM18PG121SN1D_0603 1 2.2U_0603_6.3V4Z R65 1 2 715_0402_1% G14 L3 +1.8VS L10 C176 2 DAC_RSET(PWM_GPIO1) +VDDLTP18 VDDLTP18(NC) A13 1 2 +1.8VS 1 2 +NB_PLLVDD A12 B13 1 1 BLM18PG121SN1D_0603 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z +NB_HTPVDD PLLVDD(NC) VSSLTP18(NC) 1 D14 PLLVDD18(NC) +1.8VS L11 C179 2 B12 A15 +VDDLT18 C171 C1120 LVTM PLLVSS(NC) VDDLT18_1(NC) 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 1 2 B15 PLL PWR BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z +VDDA18HTPLL VDDLT18_2(NC) 2 L5 2 1 H17 A14 2 VDDA18HTPLL VDDLT33_1(NC) VDDLT33_2(NC) B14 1 2 +1.8VS C180 +VDDA18PCIEPLL D7 1 1 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z VDDA18PCIEPLL1 E7 C14 2 R66 0_0402_5% VDDA18PCIEPLL2 VSSLT1(VSS) C173 C174 D15 VSSLT2(VSS) <14,19,25,26,27,32,33> PLT_RST# 1 2 NB_RESET# D8 C16 0.1U_0402_16V4Z 4.7U_0805_10V4Z NB_PWRGD SYSRESETb VSSLT3(VSS) 2 2 <20> NB_PWRGD A10 C18 NB_LDTSTOP# POWERGOOD VSSLT4(VSS) C10 NB_ALLOW_LDTSTOP C12 LDTSTOPb VSSLT5(VSS) C20 L 0.08A/10mil/1vias +1.8VS 1 2 E20 PM R371 300_0402_5% ALLOW_LDTSTOP VSSLT6(VSS) C22 VSSLT7(VSS) <15> CLK_NBHT C25 HT_REFCLKP Ripely 2.0 support Veri-Bright function <15> CLK_NBHT# C24 HT_REFCLKN E11 CLOCKs <15> NB_OSC_14.318M REFCLK_P/OSCIN(OSCIN) F11 E9 R69 1 2 0_0402_5% UMA_ENVDD <17> REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) NB_PWM LVDS_BLON(PCE_RCALRP) F7 NB_PWM <17> +1.1VS 1 2 1 2 T2 G12 1 2 0_0402_5% ENBKL <33> <15> NBGFX_CLK GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) R71 R72 T1 R73 <15> NBGFX_CLK# GFX_REFCLKN 4.7K_0402_5% 4.7K_0402_5% U1 1 2 @ R1085 1 2 0_0402_5% ENBKL GPP_REFCLKP R1072 100K_0402_5% U23 GPP_REFCLKN 3 <15> CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP) 1 2 V3 @ R1086 100K_0402_5% <15> CLK_SBLINK_BCLK# GPPSB_REFCLKN(SB_REFCLKN) <17> LCD_DDC_CLK B9 I2C_CLK <17> LCD_DDC_DAT A9 B8 I2C_DATA MIS. TMDS_HPD(NC) D9 D10 HPD <18> <18> HDMIDAT_UMA DDC_DATA0/AUX0N(NC) HPD(NC) <18> HDMICLK_UMA A8 DDC_CLK0/AUX0P(NC) SUS_STAT_R# <14> Strap pin <14> RS780_DFT_GPIO_0 B7 D12 1 2 SUS_STAT# <20> DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) Strap pin A7 DDC_DATA1/AUX1N(NC) R77 0_0402_5% THERMALDIODE_P AE8 NB_THERMAL_DA PAD T49 +3VS 2 1 B10 AD8 NB_THERMAL_DC PAD T50 NB temp to SB R88 10K_0402_5% STRP_DATA THERMALDIODE_N G11 D13 1 2 RSVD TESTMODE R80 C8 1.8K_0402_5% <14> AUX_CAL AUX_CAL(NC) Strap pin RS880M_FCBGA528 R Veri-Bright Non Veri-Bright R73 @ R1072 @ R1085 @ R1086 @4 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL RS880 VEDIO/CLK GEN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 11 of 56 A B C D E
    • A B C D E U3D U61 PAR 4 OF 6 MEM_BA0 L2 B9 MEM_DQ12 MEM_A0 AB12 AA18 MEM_DQ0 MEM_BA1 BA0 DQ15 MEM_DQ13 MEM_A1 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1 L3 B1 AE16 AA20 BA1 DQ14 MEM_DQ9 MEM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2 DQ13 D9 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19 MEM_A12 R2 D1 MEM_DQ14 MEM_A3 AE15 Y19 MEM_DQ3 MEM_A11 A12 DQ12 MEM_DQ15 MEM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4 P7 A11 DQ11 D3 AA12 MEM_A4(NC) MEM_DQ4(NC) V171 MEM_A10 MEM_DQ8 MEM_A5 MEM_DQ5 1 M2 A10/AP DQ10 D7 AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17 MEM_A9 P3 C2 MEM_DQ10 MEM_A6 AB14 AA15 MEM_DQ6 MEM_A8 A9 DQ9 MEM_DQ11 MEM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7 P8 A8 DQ8 C8 AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15 MEM_A7 P2 F9 MEM_DQ5 MEM_A8 AD13 AC20 MEM_DQ8 MEM_A6 A7 DQ7 MEM_DQ2 MEM_A9 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9 N7 F1 AD15 AD19 A6 DQ6 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) SBD_MEM/DVO_I/F MEM_A5 N3 H9 MEM_DQ6 MEM_A10 AC16 AE22 MEM_DQ10 MEM_A4 A5 DQ5 MEM_DQ1 MEM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11 N8 H1 AE13 AC18 MEM_A3 A4 DQ4 MEM_DQ0 MEM_A12 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) MEM_DQ12 N2 A3 DQ3 H3 AC14 MEM_A12(NC) MEM_DQ12(NC) AB20 MEM_A2 M7 H7 MEM_DQ4 Y14 AD22 MEM_DQ13 MEM_A1 A2 DQ2 MEM_DQ3 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) MEM_DQ14 M3 G2 AC22 MEM_A0 A1 DQ1 MEM_DQ7 MEM_BA0 MEM_DQ14/DVO_D10(NC) MEM_DQ15 M8 A0 DQ0 G8 AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21 1 MEM_BA1 AE17 R91 MEM_BA2 MEM_BA1(NC) MEM_DQS_P0 +1.8V_MEM_VDDQ AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17 MEM_CLKN K8 A9 W18 MEM_DQS_N0 MEM_COMP_P and MEM_COMP_N trace 100_0402_1% MEM_CLKP CK VDDQ MEM_RAS# MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS_P1 J8 C1 W12 AD20 CK VDDQ C3 MEM_CAS# Y12 MEM_RASb(NC) MEM_DQS1P(NC) AE21 MEM_DQS_N1 width >=10mils and 10mils spacing from 2 VDDQ MEM_CASb(NC) MEM_DQS1N(NC) MEM_CKE K2 CKE VDDQ C7 MEM_WE# AD18 MEM_WEb(NC) other Signals in X,Y,Z directions C9 MEM_CS# AB13 W17 MEM_DM0 VDDQ MEM_CKE MEM_CSb(NC) MEM_DM0(NC) MEM_DM1 +1.8VS VDDQ E9 AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19 G1 MEM_ODT V14 L12 VDDQ MEM_ODT(NC) L13 MEM_CS# L8 G3 AE23 +1.8V_IOPLLVDD 1 2 CS VDDQ MEM_CLKP IOPLLVDD18(NC) +NB_IOPLLVDD G7 V15 AE24 1 2 +1.1VS MEM_WE# VDDQ MEM_CLKN MEM_CKP(NC) IOPLLVDD(NC) 0_0603_5% 0_0603_5% K3 WE VDDQ G9 W14 MEM_CKN(NC) 1 1 IOPLLVSS(NC) AD23 1 MEM_RAS# K7 A1 2 1 MEM_COMP_P AE12 C181 C183 RAS VDD R92 40.2_0402_1% MEM_COMPP(NC) +MEM_VREF1 2.2U_0603_6.3V4Z C182 2.2U_0603_6.3V4Z VDD E1 AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18 MEM_CAS# L7 J9 2 1 MEM_COMP_N 2 0.1U_0402_16V4Z 2 CAS VDD +1.8V_MEM_VDDQ 2 M9 R93 40.2_0402_1% RS880M_FCBGA528 MEM_DM0 VDD F3 LDM VDD R1 MEM_DM1 B3 UDM +1.8V_MEM_VDDQ +VDDL VDDL J1 02/15 Change L12 and L13 from bead to 0 ohm resistor.2 MEM_ODT K9 VSSDL J7 1 C184 02/15 Remove L96. 2 ODT 1U_0603_10V6K MEM_DQS_P0 2 MEM_DQS_N0 F7 LDQS Layout Note: 50 mil for VSSDL E8 LDQS VSSQ A7 B2 VSSQ VSSQ B8 D2 MEM_DQS_P1 VSSQ B7 UDQS VSSQ D8 MEM_DQS_N1 A8 E7 UDQS VSSQ VSSQ F2 F8 +MEM_VREF VSSQ J2 VREF VSSQ H2 H8 VSSQ A2 NC E2 A3 MEM_BA2 NC VSS L1 E3 NC VSS R3 J3 NC VSS R7 N1 NC VSS R8 NC VSS P9 Support 8M x 16bit x 8 bank side port HY5PS561621AFP-25_FBGA84 9/20 SA000012G20 S IC D2 32M16 HY5PS121621CFP-25 FBGA 84P3 3 Side Port disable,VREF need connect to +1.8VS for DDR2 +1.8V_MEM_VDDQ +1.8V_MEM_VDDQ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 1K_0402_1% 1K_0402_1% 1 1 +1.8V_MEM_VDDQ +1.8VS C195 C196 R96 R97 L15 2 2 1 2 1 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_0805_6.3V6M 0_0805_5% +MEM_VREF +MEM_VREF1 2 2 1 1 1 220 ohm @ 100MHz,2A 0.1U_0402_16V4Z 0.1U_0402_16V4Z C608 C607 C201 C202 C203 1 1 2 2 1 1 2 2 2 1K_0402_1% 1K_0402_1% C199 C200 2 2 R98 R99 1 14 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL RS880 Side-Port DDR2 SDRAM AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 12 of 56 A B C D E
    • A B C D E U3F1 1 A25 VSSAHT1 VSSAPCIE1 A2 D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1 E22 VSSAHT3 VSSAPCIE3 D3 G22 D5 VSSAHT4 VSSAPCIE4 L 0.6A/50mil/4vias G24 VSSAHT5 VSSAPCIE5 E4 G25 VSSAHT6 VSSAPCIE6 G1 L16 2A H19 VSSAHT7 VSSAPCIE7 G2 2 1 +VDDHT J22 G4 +1.1VS VSSAHT8 VSSAPCIE8 0.1U_0402_16V4Z 0.1U_0402_16V4Z L17 H7 0_0805_5% VSSAHT9 VSSAPCIE9 1 C206 1 1 C2081 1 L22 VSSAHT10 VSSAPCIE10 J4 C210 0.7A/60mil/4vias L17 L24 R7 C209 L 1 2 +1.1VS L25 VSSAHT11 VSSAHT12 VSSAPCIE11 VSSAPCIE12 L1 4.7U_0805_10V4Z 2 2 C207 2 2 2 0.1U_0402_16V4Z U3E VDDA_12=2.5A FBMA-L11-201209-221LMA30T_0805 M20 VSSAHT13 VSSAPCIE13 L2 N22 L4 0.1U_0402_16V4Z +VDDA11PCIE VSSAHT14 VSSAPCIE14 J17 A6 P20 L7 VDDHT_1 VDDPCIE_1 C211 10U_0805_10V4Z VSSAHT15 VSSAPCIE15 K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 R19 VSSAHT16 VSSAPCIE16 M6 L18 L 0.45A/40mil/3vias L16 VDDHT_3 VDDPCIE_3 C6 C212 10U_0805_10V4Z R22 VSSAHT17 VSSAPCIE17 N4 M16 D6 R24 P6 +VDDHTRX VDDHT_4 VDDPCIE_4 VSSAHT18 VSSAPCIE18 2 1 2A P16 VDDHT_5 VDDPCIE_5 E6 R25 VSSAHT19 VSSAPCIE19 R1 0.1U_0402_16V4Z 0.1U_0402_16V4Z R16 F6 C220 1 2 1U_0402_6.3V4Z H20 R2 0_0805_5% VDDHT_6 VDDPCIE_6 VSSAHT20 VSSAPCIE20 1 1 1 C217 1 1 T16 VDDHT_7 VDDPCIE_7 G7 C219 1 2 1U_0402_6.3V4Z U22 VSSAHT21 VSSAPCIE21 R4 C214 C218 H8 C222 1 2 1U_0402_6.3V4Z V19 V7 C215 VDDPCIE_8 C221 1U_0402_6.3V4Z VSSAHT22 VSSAPCIE22 H18 J9 1 2 W22 U4 GROUND 4.7U_0805_10V4Z C216 0.1U_0402_16V4Z VDDHTRX_1 VDDPCIE_9 C224 0.1U_0402_16V4Z VSSAHT23 VSSAPCIE23 G19 VDDHTRX_2 VDDPCIE_10 K9 2 1 W24 VSSAHT24 VSSAPCIE24 V8 2 2 2 2 2 F20 M9 C223 2 1 0.1U_0402_16V4Z W25 V6 0.1U_0402_16V4Z VDDHTRX_3 VDDPCIE_11 VSSAHT25 VSSAPCIE25 E21 VDDHTRX_4 VDDPCIE_12 L9 Y21 VSSAHT26 VSSAPCIE26 W1 D22 P9 AD25 W2 VDDHTRX_5 VDDPCIE_13 VSSAHT27 VSSAPCIE27 B23 R9 W4 VDDHTRX_6 VDDPCIE_14 VSSAPCIE28 L 0.5A/50mil/4vias A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7 L19 V9 M14 W8 +VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30 +1.2V_HT 2 1 2A AE25 VDDHTTX_1 VDDPCIE_17 U9 N13 VSS13 VSSAPCIE31 Y6 AD24 PJP604 P12 AA42 0_0805_5% VDDHTTX_2 VSS14 VSSAPCIE32 2 1 1 1 1 1 AC23 VDDHTTX_3 VDDC_1 K12 +1.1VS 1 2 +NB_VDDC P15 VSS15 VSSAPCIE33 AB5 AB22 J14 R11 AB1 C225 C226 C227 C228 C229 VDDHTTX_4 VDDC_2 PAD-OPEN 4x4m VSS16 VSSAPCIE34 AA21 U16 R14 AB7 VDDHTTX_5 VDDC_3 VSS17 VSSAPCIE35 Y20 VDDHTTX_6 VDDC_4 J11 T12 VSS18 VSSAPCIE36 AC3 2 2 2 2 2 W19 K15 U14 AC4 VDDHTTX_7 VDDC_5 VSS19 VSSAPCIE37 V18 M12 L 7A/280mil/16vias VDD_CORE=5A U11 AE1 POWER VDDHTTX_8 VDDC_6 VSS20 VSSAPCIE38 U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T17 L11 330U_D2E_2.5VM_R15 V12 AB2 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDHTTX_10 VDDC_8 VSS22 VSSAPCIE40 R17 VDDHTTX_11 VDDC_9 M13 W11 VSS23 P17 M15 W15 VDDHTTX_12 VDDC_10 VSS24 L 0.25A/30mil/2vias M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14 C247 C240 C241 C242 C243 C230 C231 C244 C232 C233 C245 L22 2A VDDC_12 N14 1 AA14 VSS26 VSS2 D11 2 1 +VDDA18PCIE J10 P11 1 1 1 1 1 1 1 1 1 1 1 C234 Y18 G8 +1.8VS VDDA18PCIE_1 VDDC_13 + VSS27 VSS3 P10 P13 AB11 E14 0_0805_5% VDDA18PCIE_2 VDDC_14 VSS28 VSS4 1 1 1 1 1 1 K10 P14 AB15 E15 VDDA18PCIE_3 VDDC_15 VSS29 VSS5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 10U_0805_10V4Z M10 R12 AB17 J15 C235 C246 C236 C237 C238 C239 VDDA18PCIE_4 VDDC_16 2 2 2 2 2 2 2 2 2 2 2 2 VSS30 VSS6 L10 R15 AB19 J12 4.7U_0805_10V4Z VDDA18PCIE_5 VDDC_17 VSS31 VSS7 W9 T11 AE20 K14 2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8 H9 T15 AB21 M11 VDDA18PCIE_7 VDDC_19 VSS33 VSS9 T10 VDDA18PCIE_8 VDDC_20 U12 K11 VSS34 VSS10 L15 R10 T14 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18PCIE_9 VDDC_21 RS880M_FCBGA528 Y9 J16 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18PCIE_10 VDDC_22 AA9 VDDA18PCIE_11 AB9 AE10 VDDA18PCIE_12 VDD_MEM1(NC) +1.8VS AD9 AA11 VDDA18PCIE_13 VDD_MEM2(NC) AE9 Y11 VDDA18PCIE_14 VDD_MEM3(NC) U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10 AB10 C249 2 1 4.7U_0805_10V4Z VDD_MEM5(NC) C248 0.1U_0402_16V4Z +1.8VS F9 AC10 2 1 VDD18_1 VDD_MEM6(NC) C597 0.1U_0402_16V4Z G9 2 1 VDD18_2 1 2 +1.8V_VDD_SP AE11 H11 0.15A/30mil/2vias C598 2 1 0.1U_0402_16V4Z3 +1.8VS R1051 0_0603_5% AD11 VDD18_MEM1(NC) VDD18_MEM2(NC) VDD33_1(NC) VDD33_2(NC) H12 L C599 2 1 0.1U_0402_16V4Z 3 1 1 RS880M_FCBGA528 C251 +3VS 1U_0402_6.3V4Z C252 1U_0402_6.3V4Z 1 2 2 2 0.1U_0402_16V4Z C250 1 2 0.1U_0402_16V4Z C253 +1.8VS L Just for RS780M A11 version boot issue U64 1 6 +3VS VIN VCNTL 1 2 5 C1064 GND NC 1 3 7 1 @ 10U_0805_10V4Z VREF NC C1065 2 R1015 4 VOUT NC 8 1K_0402_1% @ 1U_0603_10V6K 9 2 2 TP @ G2992F1U_SO8 @ +VREF1.35V +1.35VS 1 Q163 R1016 @ 2N7002_SOT23-3 2 1 14 D @ 3K_0402_5% C1067 4 <36> VLDT_EN# 1 2 2 2 R1017 @ 0_0402_5% G C1066 @ 10U_0805_10V4Z S 1 2 2 3 C1068 @ 0.1U_0402_16V7K @ 0.1U_0402_16V7K 1 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL RS880 PWR/GND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 13 of 56 A B C D E
    • A B C D E1 1 DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K <11,16> CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. R101 1K_0402_5% 1 : Disable (RS780) Enable (RX780) 2 1 0 : Enable (RS780) Disable (RX780) R102 @ 1K_0402_5% PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#2 2 DFT_GPIO1: LOAD_EEPROM_STRAPS <11> AUX_CAL 1 2 @ R104 150_0402_1% Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values D4 @ CH751H-40PT_SOD323-2 0 : I2C Master can load strap values from EEPROM if connected, or use RS780 DFT_GPIO1 <11> SUS_STAT_R# 2 1 PLT_RST# <11,19,25,26,27,32,33> default values if not connected RS740/RX780: DFT_GPIO1 RS780:SUS_STAT RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.3 3 DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb <11> RS780_DFT_GPIO_0 2 1 @ R105 1K_0402_5% RX780: Enables the Test Debug Bus using PCIE bus 1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable RS780 use HSYNC to enable SIDE PORT (internal pull high) RS740/RS780: Enables Side port memory ( RS780 use HSYNC#) 1. Disable (RS740/RS780) <11,16> CRT_HSYNC 2 1 0 : Enable (RS740/RS780) R107 3K_0402_5% 2 1 +3VS R1064 3K_0402_5%4 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL RS880 STRAPS AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 14 of 56 A B C D E
    • A B C D E +3VS +3VS_CLK R167 +1.2V_HT +VDDCLK_IO 1 2 R168 0_0805_5% 1 1 1 1 1 1 1 1 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C445 C446 C447 C448 C449 C450 @ C451 0_0805_5% C444 1 1 1 1 1 1 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z C452 C453 C454 C455 C456 C457 2 2 2 2 2 2 2 2 10U_0805_10V4Z 2 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 C458 C459 C460 C4611 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 EMI Caps for single end clock. CLK_48M_USB R170 1 2 33_0402_5% OSC_14M_NB NB_OSC_14.318M CLK_48M_USB <20> 1 1 2 RX780 1.8V 75R/100R CLK_14M_SIO R379 158_0402_1% NB_OSC_14.318M <11> C1074 1 +3VS_CLK CLK_XTAL_OUT @ 1 R380 2 RS780 1.1V 200R/100R 12P_0402_50V8J R1105 1 75_0402_1% 90.9_0402_1% 2 2 1 CLK_XTAL_IN R1106 CLK_14M_SB <19> 2 110_0402_5% 01/23 14.318MHz For SB710 reference C1076 Y2 CLK_NBHT <11> +3VS_CLK +3VS_CLK NB_OSC_14.318M_R C1123 2 CLK_NBHT# <11> NB 12P_0402_50V8J CLK_48M_USB_R 2 1 1 2 CLK_XTAL_OUT 1 2 +3VS_CLK C1075 CLK_CPU_BCLK <6> CLK_XTAL_IN 14.31818MHZ_20P_6X1430004201 R174 8.2K_0402_5% 12P_0402_50V8J SEL_SATA 1U_0402_6.3V4Z 2 27M_SEL 1 12 C464 C465 CLK_CPU_BCLK_R R186 2 1 2 R946 0_0402_1% @ 261_0402_1% CPU 22P_0402_50V8J 22P_0402_50V8J CLK_CPU_BCLK#_R 1 2 2 2 R945 0_0402_1% 1 +3VS_CLK CLK_CPU_BCLK# <6> 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 Routing the trace at least 10mil U10 1 VSS_48 48MHz_0 48MHz_1 VDD_48 REF_0/SEL_HTT66 REF_2/SEL_27 HTT_0/66M_0 HTT_0#/66M_1 PD# CPU_K8_0 CPU_K8_0# XTAL_OUT VSS_REF VDD_REF VDD_HTT VSS_HTT REF_1/SEL_SATA GND XTAL_IN C1106 0.1U_0603_25V7K 2 <8,9,20,30> SMB_CK_CLK0 1 SCL VDD_CPU 54 +3VS_CLK <8,9,20,30> SMB_CK_DAT0 2 53 +VDDCLK_IO SDA VDD_CPU_I/O +3VS_CLK 3 52 VDD_DOT VSS_CPU CLKREQ_NCARD# 4 51 SRC_7#/27M CLKREQ_1# CLKREQ_MCARD2# CLKREQ_NCARD# <26> 5 50 SRC_7/27M_SS CLKREQ_2# CLKREQ_MCARD2# <26> 6 49 +3VS_CLK VSS_DOT VDD_A 7 48 SRC_5# VSS_A 8 SRC_5 VSS_SATA 47 PA_RS7X0A1 <11> CLK_SBLINK_BCLK# 9 SRC_4# SRC_6/SATA 46 CLK_SBSRC_BCLK <19> PA_RS7X0A1 SB LINK <11> CLK_SBLINK_BCLK 10 SRC_4 SRC_6#/SATA# 45 CLK_SBSRC_BCLK# <19> SB SRC 11 44 +3VS_CLK VSS_SRC VDD_SATA CLKREQ_MCARD1# +VDDCLK_IO 12 43 CLKREQ_MCARD1# <26> VDD_SRC_IO CLKREQ_3# CLKREQ4 <26> CLK_PCIE_MCARD1# 13 42 SRC_3# CLKREQ_4# MiniCard_1 <26> CLK_PCIE_MCARD1 14 SRC_3 SB_SRC_SLOW# 41 1 2 +3VS_CLK <26> CLK_PCIE_MCARD2# 15 40 R372 10K_0402_5% For ICS need to pull high. SRC_2# SB_SRC_0 MiniCard_2 <26> CLK_PCIE_MCARD2 16 SRC_2 SB_SRC_0# 39 For SLG is NC +3VS_CLK 17 38 +3VS_CLK VDD_SRC VDD_SB_SRC +VDDCLK_IO 18 37 +VDDCLK_IO VDD_SRC_IO VDD_SB_SRC_IO VSS_SB_SRC VDD_ATIG_IO ATIGCLK_2# ATIGCLK_1# ATIGCLK_0# CLKREQ_0# SB_SRC_1# ATIGCLK_2 ATIGCLK_1 ATIGCLK_0 SB_SRC_1 VDD_ATIG3 3 VSS_ATIG VSS_SRC SRC_1# SRC_0# SRC_1 SRC_0 SLG8SP626VTR_QFN72_10x10 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CLKREQ_NCARD# 1 2 +3VS_CLK +3VS_CLK R324 8.2K_0402_5% CLKREQ_MCARD2# 1 2 R325 8.2K_0402_5% CLKREQ_MCARD1# 1 2 2 R326 8.2K_0402_5% +VDDCLK_IO +3VS_CLK @ R179 CLKREQ_LAN# 1 2 8.2K_0402_5% R1039 8.2K_0402_5% CLKREQ4 1 2 R1045 @ 8.2K_0402_5% NBGFX_CLK <11> 1 +3VS_CLK SEL_SATA NBGFX_CLK# <11> NB GFX CLK_PCIE_MCARD0 <27> CLK_PCIE_MCARD0# <27> Card Reader 2 2 CLKREQ_LAN# CLKREQ_LAN# <25> R181 R180 CLK_PCIE_LAN <25> 8.2K_0402_5% 8.2K_0402_5% GLAN NB CLOCK INPUT TABLE CLK_PCIE_LAN# <25> NB CLOCKS RX780 RS780 CLK_PCIE_NCARD <26> 1 1 27M_SEL New Card CLK_PCIE_NCARD# <26> HT_REFCLKP 100M DIFF 100M DIFF HT_REFCLKN 100M DIFF 100M DIFF 1 configure as SATA output 1 * configure as 27M and 27M_SS output REFCLK_P4 SEL_SATA 27M_SEL 14M SE (1.8V) 14M SE (1.1V) 4 * 0 configure as normal SRC(SRC_6) output 0 configure as SRC_7 output REFCLK_N NC v r ef * default * default GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)* Use voltage divider resistor R379 & R380 to pull low NB_OSC_14.318M 1 configure as single-ended 66MHz output Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title 0* configure as differential 100MHz output * default THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Clock generator AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 15 of 56 A B C D E
    • A B C D E1 CRT CONNECTOR 1 +5VS +R_CRT_VCC +CRT_VCC D36 F2 2 1 1 2 1 1 1 @ D35 @ D37 @ D34 1 RB491D_SOT23 1A_6VDC_MINISMDC110 C475 0.1U_0402_16V4Z +3VS 2 DAN217_SC59 DAN217_SC59 DAN217_SC59 2 3 2 3 2 3 JCRT 6 L47 RGND 11 ID0 <11> RED R ED 1 2 RED_L 1 BLM15AG121SN1D_0402 Red 7 L48 D_DDCDATA GGND 12 GREEN GREEN_L SDA <11> GREEN 1 2 2 Green BLM15AG121SN1D_0402 8 L49 H S YNC BGND +CRT_VCC 13 BLUE BLUE_L Hsync <11> BLUE 1 2 3 Blue BLM15AG121SN1D_0402 +CRT_VCC 9 +5V 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K VSYNC 14 1 Vsync 1 1 1 4 res 1 1 1 75_0402_1% 75_0402_1% 75_0402_1% 1 1 1 10 C1107 C471 C859 C469 C858 C476 C472 D_DDCCLK SGND 0.1U_0603_25V7K 15 R214 R211 R217 SCL 2 52 2 2 2 GND 2 2 2 2 16 2 2 2 GND 17 GND CONN@ SUYIN_070546FR015S263ZR RED_L <35> GREEN_L <35> +3VS BLUE_L <35> +CRT_VCC +CRT_VCC D_VSYNC <35> 1 2 1 2 D_HSYNC <35> R237 R238 C473 5 1 4.7K_0402_5% 4.7K_0402_5% R100 R218 0.1U_0402_16V4Z OE# P 2 6.8K_0402_5% 6.8K_0402_5% 2 4 D_HSYNC R240 1 2 0_0603_5% H S YNC <11,14> CRT_HSYNC 2 1 A Y G <11> UMA_CRT_DAT 1 6 D_DDCDATA U14 D_DDCDATA <35> Q10A SN74AHCT1G125GW_SOT353-5 3 2N7002DW-7-F_SOT363-6 5 1 2 @ R1023 0_0402_5% 4 3 v0.2 ADD D_DDCCLK 1 2 <11> UMA_CRT_CLK D_DDCCLK <35> 5 1 Q10B @ C477 2N7002DW-7-F_SOT363-6 1 1 0.1U_0402_16V4Z OE# P 2 4 D_VSYNC R241 1 2 0_0603_5% VSYNC <11,14> CRT_VSYNC A Y 1 2 @ C857 @ C856 G 10P_0402_50V8J 10P_0402_50V8J3 @ R1022 0_0402_5% U13 3 470P_0402_50V8J 2 2 470P_0402_50V8J SN74AHCT1G125GW_SOT353-5 1 1 3 v0.2 ADD @ C474 @ C470 2 24 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL CRT Connector AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 16 of 56 A B C D E
    • A B C D E +5VALW +5VS +USB_CAM USB_VCCA is +3.9V, R892:100K; R891:215KKohm G916 Vref=1.25V when U54 install 1 1 U54 1 PJP4 PJP61 PAD-OPEN 2x2m PAD-OPEN 2x2m 1 5 R891 G916-390T1UF 1 VIN VOUT 2 @ 215K_0402_1% C718 install when U54 is GND 2 L 2 2 2 2 3 4 C719 RT9193-39GB C720 EN BP 1 RT9193-39GB_SOT23-5 1 10U_0805_10V4Z 10U_0805_10V4Z C718 R892 1 1 1 R1013 0.1U_0402_16V4Z @ 100K_0402_1% Close to JLVDS 2 L 2 0_0402_5% D22 2 @ R1014 4 2 USB20_P5 +USB_CAM VIN IO1 1 2 CAM_SHDN# <21> 0_0402_5% USB20_N5 3 1 IO2 GND @ PRTR5V0U2X_SOT143-4 +LCDVDD +5VALW 1 22 2 R225 R224 +3VS 220_0402_5% 1M_0402_5% 80mil 6 2 1 3 S SI2301BDS-T1-E3_SOT23-3 G Q45A 2 2N7002DW-7-F_SOT363-6 R222 Q43 2 1 2 100K_0402_5% D 2 1 1 3 C863 80mil B+ +LCDVDD 1000P_0402_50V7K +LCDVDD INVPWR_B+ 5 1 <11> UMA_ENVDD Q45B 1 2 1 2N7002DW-7-F_SOT363-6 4 R276 C487 C491 680P_0402_50V7K L44 C1108 2.2K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z C479 1 2 680P_0402_50V7K 2 FBMA-L11-201209-221LMA30T_0805 2 1 1 1 C480 680P_0402_50V7K LVDS CONN Ripely 2.0 Support Veri-Bright function 2 2 JLVDS 1 2 LVDS_A2- 1 2 LVDS_A2- <11> LVDS_A2- C1056 1 2 @ 10P_0402_50V8J LVDS_A2+ 3 4 LVDS_A2+ 3 4 LVDS_A2+ <11> 5 6 LVDS_A1- R1084 1 20_0402_5% INV_PWM 5 6 LVDS_A1- <11> <11> NB_PWM LVDS_A1- C1057 1 2 @ 10P_0402_50V8J LVDS_A1+ 7 8 LVDS_A1+3 7 8 LVDS_A1+ <11> 3 9 10 LVDS_A0- LVDS_A0- <11> LVDS_A0- C1058 LVDS_A0+ 9 10 LVDS_A0+ 1 2 @ 10P_0402_50V8J 11 11 12 12 LVDS_A0+ <11> <33> EC_PWM @ R1078 1 20_0402_5% USB20_P5 13 14 LVDS_ACLK- <20> USB20_P5 13 14 LVDS_ACLK- <11> LVDS_ACLK- C1059 1 2 @ 10P_0402_50V8J LVDS_ACLK+ USB20_N5 15 16 LVDS_ACLK+ <20> USB20_N5 15 16 LVDS_ACLK+ <11> 17 18 17 18 19 20 19 20 21 22 +3VS 21 22 DMIC_DAT +5VS 23 24 DMIC_DAT <28> 23 24 DMIC_CLK R491 25 26 DMIC_CLK <28> 25 26 27 27 28 28 1 2 100_0805_5% 29 30 INV_PWM 29 30 1 C481 31 32 BKOFF# 31 32 BKOFF# <33> 33 34 DAC_BRIG 33 34 DAC_BRIG <33> 35 36 +USB_CAM 2 680P_0402_50V7K 35 36 LCD_DDC_CLK +3VS 37 37 38 38 LCD_DDC_CLK <11> 39 40 LCD_DDC_DAT 39 40 LCD_DDC_DAT <11> 680P_0402_50V7K 680P_0402_50V7K 41 42 BKOFF# 1 2 GND GND @ 4.7K_0402_5% R483 1 1 680P_0402_50V7K 680P_0402_50V7K ACES_88242-4001 1 1 C482 C483 CONN@ LCD_DDC_CLK 1 2 C866 C867 4.7K_0402_5% R274 9/20 SP02000EA00/SP02000BW00 2 2 2 2 @ @ LCD_DDC_DAT 1 2 @ @ 4.7K_0402_5% R2754 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL LCD CONN. / WebCam Size Document Number R ev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 17 of 56 A B C D E
    • A B C D E +3VS +HDMI_5V_OUT 1 2 R176 R209 4.7K_0402_5% 4.7K_0402_5%1 R210 R236 1 2 +HDMI_5V_OUT 6.8K_0402_5% 6.8K_0402_5% 2 1 HDMI_HPD 1 6 HDMI_SDATA C851 <11> HDMIDAT_UMA Q134A 2 2 1 +3VS 2N7002DW-7-F_SOT363-6 2 R615 2 @ R1019 5 1 5 0.1U_0402_16V4Z 2.2K_0402_5% C850 1 2 1 R628 0_0402_5% OE# P 2 4 100K_0402_5% 0.1U_0402_16V4Z 4 3 v0.2 ADD HDMI_SCLK A Y HPD <11> 1 <11> HDMICLK_UMA Q134B 1 G U39 2N7002DW-7-F_SOT363-6 SN74AHCT1G125GW_SOT353-5 3 @ R1018 1 2 0_0402_5% v0.2 ADD2 2 MP:Update D10 to meet HDMI. HDMI_CLK+ 1 2 HDMI_R_CK+ @ R112 0_0402_5% D10 +5VS 2 1 +HDMI_5V_OUT L85 1 2 RB491D_SOT23 1 2 1 4 3 C468 4 3 C507 1 2 0.1U_0402_16V7K HDMI_CLK- WCM-2012-900T_4P 0.1U_0402_16V4Z <10> TMDS_B_CLK# 2 C508 1 2 0.1U_0402_16V7K HDMI_CLK+ HDMI_CLK- 1 2 HDMI_R_CK- <10> TMDS_B_CLK @ R113 0_0402_5% C655 1 2 0.1U_0402_16V7K HDMI_TX0- <10> TMDS_B_DATA0# HDMI_TX0+ C675 1 2 0.1U_0402_16V7K <10> TMDS_B_DATA0 HDMI_TX0+ 1 2 HDMI_R_D0+ @ R115 0_0402_5% C804 1 2 0.1U_0402_16V7K HDMI_TX1- <10> TMDS_B_DATA1# HDMI_TX1+ C827 1 2 0.1U_0402_16V7K L86 <10> TMDS_B_DATA1 HDMI_TX2- 1 1 2 2 HDMI Connector C852 1 2 0.1U_0402_16V7K <10> TMDS_B_DATA2# HDMI_TX2+ +HDMI_5V_OUT C853 1 2 0.1U_0402_16V7K 4 3 <10> TMDS_B_DATA2 4 3 JHDMI WCM-2012-900T_4P 18 HDMI_TX0- HDMI_R_D0- HDMI_SDATA +5V 1 2 16 133 HDMI_CLK- HDMI_TX0- HDMI_TX1- HDMI_TX2- @ R116 0_0402_5% HDMI_SCLK SDA CEC 3 15 SCL Reserved 14 HDMI_CLK+ HDMI_TX0+ HDMI_TX1+ HDMI_TX2+ HDMI_HPD 19 HP_DET 2 HDMI_R_CK- GND 12 CK- GND 5 2 1 2 2 HDMI_TX1+ 1 2 HDMI_R_D1+ HDMI_R_CK+ 10 8 R315 R307 R172 @ R117 0_0402_5% HDMI_R_D0- CK+ GND 9 11 D0- GND 2 2 2 2 715_0402_1% 715_0402_1% 715_0402_1% 715_0402_1% HDMI_R_D0+ 7 20 R173 R304 R139 L87 HDMI_R_D1- D0+ GND 6 21 715_0402_1% 715_0402_1% 715_0402_1% 715_0402_1% HDMI_R_D1+ D1- GND 1 2 4 22 1 2 1 1 R297 R141 1 2 HDMI_R_D2- D1+ GND 3 D2- GND 23 +5VS HDMI_R_D2+ 1 17 1 1 1 1 D2+ DDC/CEC_GND 4 3 4 3 WCM-2012-900T_4P CONN@ SUYIN_100042MR019S153ZL HDMI_TX1- 1 2 HDMI_R_D1- @ R118 0_0402_5% 1 D 1/19 Use one mos to instead of two dule MOS design 2 Q173 G S 2N7002_SOT23-3 HDMI_TX2+ 1 2 HDMI_R_D2+ 3 2 @ R119 0_0402_5% R1104 L88 100K_0402_5% 1 2 1 2 1 4 4 3 3 WCM-2012-900T_4P HDMI_TX2- 1 2 HDMI_R_D2- @ R120 0_0402_5%4 4 L Change PCB Footprint from SW_WCM2012F2S_4P to KING_WCM-2012-900T_4P 03/07 Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm. Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL HDMI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 18 of 56 A B C D E
    • A B C D E +3VALW C506 2 1 Check AMD need pull low or not 5 @ 0.1U_0402_16V4Z U16 2 1 2 NB_RST#_R U15A P B Y 4 PLT_RST# PLT_RST# <11,14,25,26,27,32,33> R300 @ 8.2K_0402_5% SB700 NB_RST#_R 1 NB_RST#_R N2 P4 A A_RST# PCICLK0 G @ NC7SZ08P5X_NL_SC70-5 Part 1 of 5 P3 C492 0.1U_0402_16V7K SB_RX0P_C PCICLK1 <10> SB_RX0P 1 2 V23 P1 PCICLK2 <23> 3 C493 0.1U_0402_16V7K SB_RX0N_C PCIE_TX0P PCICLK2 CLK_PCI_SIO_R R301 1 0_0402_5% PCI_CLK3 <10> SB_RX0N 1 2 V22 P2 2 PC I CLKS SB_RX1P_C PCIE_TX0N PCICLK3 PCI_CLK3 <23> C494 1 2 0.1U_0402_16V7K V24 T4 <10> SB_RX1P SB_RX1N_C PCIE_TX1P PCICLK4 PCI_CLK4 <23> C495 1 2 0.1U_0402_16V7K V25 T3 <10> SB_RX1N SB_RX2P_C PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 <23> 2 1 C496 1 2 0.1U_0402_16V7K U25 <10> SB_RX2P PCIE_TX2P R312 33_0402_5% C497 1 2 0.1U_0402_16V7K SB_RX2N_C U241 <10> SB_RX2N SB_RX3P_C PCIE_TX2N 1 C498 1 2 0.1U_0402_16V7K T23 <10> SB_RX3P SB_RX3N_C PCIE_TX3P C499 1 2 0.1U_0402_16V7K T22 N1 <10> SB_RX3N PCIE_TX3N PCIRST# <10> SB_TX0P U22 PCIE_RX0P PCI EXPRESS INTERFACE <10> SB_TX0N U21 U2 PCIE_RX0N AD0 <10> SB_TX1P U19 PCIE_RX1P AD1 P7 <10> SB_TX1N V19 V4 PCIE_RX1N AD2 <10> SB_TX2P R20 PCIE_RX2P AD3 T1 <10> SB_TX2N R21 PCIE_RX2N AD4 V3 <10> SB_TX3P R18 U1 PCIE_RX3P AD5 <10> SB_TX3N R17 PCIE_RX3N AD6 V1 V2 R305 AD7 2 1 562_0402_1% T25 PCIE_CALRP AD8 T2 +PCIE_VDDR R306 2 1 2.05K_0402_1% T24 W1 L53 PCIE_CALRN AD9 T9 +SB_PCIEVDD AD10 +1.2V_HT 1 2 P24 R6 BLM18PG121SN1D_0603 PCIE_PVDD AD11 1 1 AD12 R7 P25 R5 C504 C505 PCIE_PVSS AD13 AD14 U8 10U_0805_10V4Z 1U_0402_6.3V4Z U5 2 2 AD15 Y7 AD16 W8 AD17 AD18 V9 Close to SB AD19 Y8 AA8 AD20 AD21 Y4 Y3 AD22 PCI_AD23 Y2 PCI_AD23 <23> AD23 PCI_AD24 AD24 AA2 PCI_AD24 <23> AB4 PCI_AD25 AD25 PCI_AD25 <23> N25 AA1 PCI_AD26 <15> CLK_SBSRC_BCLK PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD26 <23> N24 AB3 PCI_AD272 <15> CLK_SBSRC_BCLK# PCIE_RCLKN/NB_LNK_CLKN AD27 PCI_AD27 <23> 2 AB2 PCI_AD28 AD28 PCI_AD28 <23> K23 AC1 NB_DISP_CLKP AD29 K22 AC2 NB_DISP_CLKN AD30 @ C1085 12P_0402_50V8J AD31 AD1 M24 W2 CLK_PCI_SIO2 1 2 NB_HT_CLKP CBE0# M25 U7 NB_HT_CLKN CBE1# C1086 12P_0402_50V8J AA7 PCI INTERFACE CBE2# CLK_PCI_SIO P17 Y1 1 2 CPU_HT_CLKP CBE3# M18 CPU_HT_CLKN FRAME# AA6 W5 C1087 12P_0402_50V8J DEVSEL# CLK_PCI_EC M23 SLT_GFX_CLKP IRDY# AA5 1 2 M22 Y5 SLT_GFX_CLKN TRDY# PAR U6 J19 W6 GPP_CLK0P STOP# J18 W4 GPP_CLK0N PERR# V7 PCI_SERR# <33> SERR# L20 AC3 GPP_CLK1P REQ0# L19 AD4 @ R314 20M_0402_5% GPP_CLK1N REQ1# AB7 REQ2# 1 2 M19 GPP_CLK2P REQ3#/GPIO70 AE6 M20 AB6 PAD T15 GPP_CLK2N REQ4#/GPIO71 C643 AD2 GNT0# 01/23 14.318MHz for SB710 reference N22 GPP_CLK3P GNT1# AE4 1 2 SB_32KHI P22 AD5 GPP_CLK3N GNT2# CLO CK GENERATOR AC6 GNT3#/GPIO72 LPCCLK1 18P_0402_50V8J Y3 1 2 L18 AE5 PAD T16 R308 1 2 33_0402_5% CLK_PCI_SIO CLK_PCI_SIO <32> 25M_48M_66M_OSC GNT4#/GPIO73 1 4 3 R1107 0_0402_5% AD6 PAD T17 R389 OSC NC CLKRUN# V5 LOCK# 1 2 <15> CLK_14M_SB 2 1 J21 20M_0402_5% OSC NC @ R1108 0_0402_5% 14M_X1 AD3 32.768KHZ_12.5PF_Q13MC14610050_10PPM INTE#/GPIO33 C652 AC4 2 INTF#/GPIO34 AE23 SB_32KHO INTG#/GPIO35 3 1 2 2 1 J20 14M_X2 INTH#/GPIO36 AE3 PCI_PIRQH# R967 2 1 0_0402_5% ACCEL_INT <30> @ R1109 1K_0402_5% 18P_0402_50V8J R302 33_0402_5% LPCCLK0 G22 CLK_PCI_EC_R 1 2 CLK_PCI_EC CLK_PCI_EC <23,33> Close to SB E22 LPCCLK1 LPCCLK1 <23> SB_32KHI LPCCLK1 A3 X1 LAD0 H24 LPC_AD0 <32,33> STRAP PIN LAD1 H23 LPC_AD1 <32,33> EC & Debug J25 LPC_AD2 <32,33> LAD2 J24 LPC_AD3 <32,33> LAD3 +1.8VS 2 1 CPU_LDT_REQ# SB_32KHO B3 X2 LFRAME# H25 LPC_FRAME# <32,33> RTC XTAL L PC R318 @ 10K_0402_5% H22 PAD T18 LDRQ0# AB8 LPC_DRQ# <32> LDRQ1#/GNT5#/GPIO68 BMREQ#/REQ5#/GPIO65 AD7 2 1 H_PROCHOT# V15 +3VS SERIRQ SIRQ <32,33> R319 10K_0402_5% CPU_LDT_REQ# F23 <6,11> CPU_LDT_REQ# ALLOW_LDTSTP H_PROCHOT# F24 C3 RTC_CLK <23> STRAP PIN <6> H_PROCHOT# H_PWRGD PROCHOT# RTCCLK <43> H_PWRGD F22 C2 LDT_PG INTRUDER_ALERT# +3VL <6,11> LDT_STOP# G25 B2 +SB_VBAT LDT_STP# VBAT +SB_VBAT +RTCVCC_R +RTCVCC G24 C PU <6> LDT_RST# LDT_RST# +RTCBATT R311 R316 R317 D42 1 2 H_PWRGD_SB 120_0402_5% 120_0402_5% 2 <6> H_PWRGD_CPU RTC 1 2 1 2 1 R876 JBATT1 0_0402_5% 218-0660011 A14 SB7_FCBGA528 1 1 3 1 2 W=20mils 1 W=20mils 1 W=20mils 2 2 2 R1079 9/20 SA00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH C509 C510 DAN202U_SC70 1K_0402_5% 3 J1 GND 1 2 4 2 <43> H_PWRGD 2 2 GND @ JUMP_43X39 0_0402_5% 1U_0402_6.3V4Z CONN@ ACES_85205-02001 1 +RTCBATT_R 0.1U_0402_16V4Z 9/20 SP020008T00 14 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SB710-PCIE/PCI/ACPI/LPC/RTC AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 19 of 56 A B C D E
    • A B C D E <11> NB_PWRGD R1052 2 1 NBPWRGD 0_0402_5% R1053 2 1 @ 100_0402_5% For SB700 A11 divider to U15D 1.8V for RS & RX780 SB700 Part 4 of 5 E1 PCI_PME#/GEVENT4# E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB <15>1 demo circuit LID use RI# 1 H7 SLP_S2/GPM9# F5 G8 USB_RCOMP 1 2 +3VS <33> SLP_S3# SLP_S3# USB_RCOMP G1 11.8K_0402_1% R323 ACPI / WAKE UP EVENTS <33> SLP_S5# SLP_S5# H2 USB MISC SUS_STAT# <33> PWRBTN_OUT# PWR_BTN# 1 2 <6,33,43> SB_PWRGD H1 R388 4.7K_0402_5% SUS_STAT# PWR_GOOD <11> SUS_STAT# K3 SUS_STAT# SB_TEST2 H5 E6 SB_TEST1 TEST2 USB_FSD13P H4 TEST1 USB_FSD13N E7 +3VALW SB_TEST0 H3 TEST0 U SB 1.1 SB_TEST2 <33> GATEA20 Y15 GA20IN/GEVENT0# USB_FSD12P F7 Touch Screen (delete) 1 2 <33> KB_RST# W15 KBRST#/GEVENT1# USB_FSD12N E8 R320 @ 2.2K_0402_5% K4 SB_TEST1 <33> EC_SCI# LPC_PME#/GEVENT3# USB20_P11 1 2 <33> EC_SMI# K24 LPC_SMI#/EXTEVNT1# USB_HSD11P H11 USB20_P11 <26> R321 @ 2.2K_0402_5% PAD T19 F1 J10 USB20_N11 USB-11 New Card SB_TEST0 S3_STATE/GEVENT5# USB_HSD11N USB20_N11 <26> 1 2 J2 R322 @ 2.2K_0402_5% PCIE_WAKE# SYS_RESET#/GPM7# USB20_P10 H6 E11 USB20_P10 <26> WAKE#/GEVENT8# USB_HSD10P USB20_N10 F2 H_THERMTRIP# J6 BLINK/GPM6# USB_HSD10N F11 USB20_N10 <26> USB-10 MiniCard(TV or WWAN) +3VS <6> H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2# NBPWRGD W14 A11 NB_PWRGD USB_HSD9P SMB_CK_CLK0 EC_RSMRST# USB_HSD9N B11 USB-9 Card Reader (delete) R328 1 2 1.2K_0402_5% D3 <33> EC_RSMRST# RSMRST# USB20_P8 C10 USB20_P8 <26> USB_HSD8P 2 R329 1 2 1.2K_0402_5% SMB_CK_DAT0 SB700 has internal PD D10 USB20_N8 USB-8 MiniCard(WLAN) USB_HSD8N USB20_N8 <26> R327 CH751H-40PT_SOD323-2 2.2K_0402_5% AE18 G11 USB20_P7 SATA_IS0#/GPIO10 USB_HSD7P USB20_P7 <31> 1 2 EC_RSMRST# AD18 H12 USB20_N7 USB-7 Fingerprint +3VALW <39,41> 3/5V_OK CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USB20_N7 <31> D58 AA19 1 SMARTVOLT1/SATA_IS2#/GPIO4 USB20_P6 W17 E12 USB20_P6 <31> R331 SMB_CK_CLK1 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P USB20_N6 1 2 2.2K_0402_5% V17 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N E14 USB20_N6 <31> USB-6 Bluetooth W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 R332 1 2 2.2K_0402_5% SMB_CK_DAT1 W21 C12 USB20_P5 <28> SB_SPKR U SB 2.0 SMB_CK_CLK0 SPKR/GPIO2 USB_HSD5P USB20_N5 USB20_P5 <17>2 <8,9,15,30> SMB_CK_CLK0 SMB_CK_DAT0 AA18 SCL0/GPOC0# USB_HSD5N D12 USB20_N5 <17> USB-5 USB Camera 2 <8,9,15,30> SMB_CK_DAT0 W18 SDA0/GPOC1# SMB_CK_CLK1 K1 B12 <26> SMB_CK_CLK1 SMB_CK_DAT1 SCL1/GPOC2# USB_HSD4P +3VALW <26> SMB_CK_DAT1 K2 SDA1/GPOC3# USB_HSD4N A12 USB-4 Left side AA20 DDC1_SCL/GPIO9 +3VS Y18 G12 USB20_P3 GPIO R83 DDC1_SDA/GPIO8 USB_HSD3P USB20_N3 USB20_P3 <35> C1 LLB#/GPIO66 USB_HSD3N G14 USB20_N3 <35> USB-3 Dock 2 1 2 SB_GPIO5 Y19 R540 10K_0402_5% SMARTVOLT2/SHUTDOWN#/GPIO5 USB20_P2 G5 H14 USB20_P2 <31> 10K_0402_5% DDR3_RST#/GEVENT7# USB_HSD2P USB20_N2 USB_HSD2N H15 USB20_N2 <31> USB-2 Left Side A13 USB20_P1 USB20_P1 <31> 1 USB_HSD1P USB20_N1 PCIE_WAKE# USB_HSD1N B13 USB20_N1 <31> USB-1 Right side 2 1 <25> LAN_PCIE_WAKE# R993 47_0402_5% USB20_P0 B14 USB20_P0 <31> USB_HSD0P USB20_N0 <26> MINI_PCIE_WAKE# 2 R994 1 @ 0_0402_5% B9 USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N A14 USB20_N0 <31> USB-0 Right side (S/W Debug Port) B8 USB_OC5#/IR_TX0/GPM5# A8 A18 USB OC R82 0_0402_5% USB_OC4#/IR_RX0/GPM4# KSO_16 <33> EC_LID_OUT# A9 B18 EXP_CPPE# USB_OC3#/IR_RX1/GPM3# KSO_17 <26> EXP_CPPE# 1 2 E5 F21 CR_CPPE# USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 <27> CR_CPPE# 1 2 F8 USB_OC1#/GPM1# SCL2/IMC_GPIO11 D21 R333 33_0402_5% 1 2 R81 0_0402_5% E4 F19 <28> HDA_BITCLK_CODEC USB_OC0#/GPM0# SDA2/IMC_GPIO12 R334 33_0402_5% 1 2 HDABITCLK 1 2 HDA_BITCLK E20 <34> HDA_BITCLK_MDC SCL3_LV/IMC_GPIO13 R335 33_0402_5% 1 2 R1080 0_0402_5% M1 E21 <34> HDA_SDOUT_MDC AZ_BITCLK SDA3_LV/IMC_GPIO14 R336 33_0402_5% 1 2 HDA_SDOUT M2 E19 <28> HDA_SDOUT_CODEC HDA_SDIN0 AZ_SDOUT IMC_PWM1/IMC_GPIO15 <28> HDA_SDIN0 HDA_SDIN1 J7 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 D19 STRAP PIN GPIO16 <23> <34> HDA_SDIN1 J8 AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 STRAP PIN GPIO17 <23> L8 AZ_SDIN2/GPIO44 H D AUDIO M3 G20 R337 33_0402_5% HDA_SYNC AZ_SDIN3/GPIO46 KSI_0 <34> HDA_SYNC_MDC 1 2 L6 G21 R338 33_0402_5% AZ_SYNC KSI_1 <28> HDA_SYNC_CODEC 1 2 M4 D25 AZ_RST# KSI_2 L5 D24 R339 33_0402_5% HDARST# AZ_DOCK_RST#/GPM8# KSI_3 1 2 C25 INTEGRATED uC3 <28> HDA_RST#_CODEC KSI_4 3 R340 33_0402_5% 1 2 C24 <34> HDA_RST#_MDC KSI_5 PAD T41 KSI_6 B25 C23 KSI_7 <23,33> HDARST# STRAP PIN KSO_0 B24 B23 KSO_1 A23 KSO_2 C22 KSO_3 A22 KSO_4 KSO_5 B22 KSO_6 B21 C1088 82P_0402_50V8J A21 HDA_BITCLK_CODEC KSO_7 1 2 H19 PS2_DAT KSO_8 D20 H20 C20 C1089 82P_0402_50V8J PS2_CLK KSO_9 H21 A20 INTEGRATED uC HDA_BITCLK_MDC SPI_CS2#/IMC_GPIO2 KSO_10 1 2 F25 B20 IDE_RST#/F_RST#/IMC_GPO3 KSO_11 B19 C1090 82P_0402_50V8J KSO_12 D22 A19 HDA_SDOUT_MDC PS2KB_DAT KSO_13 1 2 E24 D18 PS2KB_CLK KSO_14 E25 C18 C1091 82P_0402_50V8J PS2M_DAT KSO_15 D23 HDA_SDOUT_CODEC PS2M_CLK 1 2 218-0660011 A14 SB7_FCBGA528 +3VS @ U66 7 1 HDA_BITCLK VDD CLKIN4 HDABITCLK 4 6 2 @ R1081 CLKOUT NC 2 1 5 10K_0402_5% SSON NC 8 @ R1082 +3VS 03/05 Add SSC circuit for HDA_BITCLK. 1 @C1122 4 3 2 1 GND SS 10K_0402_5% 2 0.1U_0402_16V4Z ASM3P623S00BF-08TR_TSSOP8 2 @ R1083 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title SB710 USB/AC97 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 20 of 56 A B C D E
    • A B C D E 10P_0402_50V8J 2 1 C516 SATA_X1 1 1 Y4 R341 25MHz_20pF_6X25000017 10M_0402_5% 2 2 10P_0402_50V8J 2 1 C517 SATA_X21 1 U15B C512 1 2 0.01U_0402_25V7K SATA_STX_DRX_P0 AD9 SB700 AA24 <24> SATA_TXP0 SATA_TX0P IDE_IORDY <24> SATA_TXN0 C513 1 2 0.01U_0402_25V7K SATA_STX_DRX_N0 AE9 Part 2 of 5 AA25 SATA_TX0N IDE_IRQ Y22 IDE_A0 <24> SATA_RXN0_C AB10 SATA_RX0N IDE_A1 AB23 <24> SATA_RXP0_C AC10 SATA_RX0P IDE_A2 Y23 IDE_DACK# AB24 Local Frame Buffer Strapping List C514 1 2 0.01U_0402_25V7K SATA_STX_DRX_P1 AE10 AD25 Copy from Becks. <24> SATA_TXP1 SATA_TX1P IDE_DRQ C515 1 2 0.01U_0402_25V7K SATA_STX_DRX_N1 AD10 AC25 <24> SATA_TXN1 SATA_TX1N IDE_IOR# IDE_IOW# AC24 <24> SATA_RXN1_C AD11 AE11 SATA_RX1N IDE_CS1# Y25 Y24 LFB_ID2 LFB_ID1 LFB_ID0 <24> SATA_RXP1_C SATA_RX1P IDE_CS3# C520 1 2 1000P_0402_50V7K SATA_STX_DRX_P2 AB12 AD24 <31> SATA_TXP2 SATA_TX2P IDE_D0/GPIO15 C521 2 1000P_0402_50V7K SATA_STX_DRX_N2 <31> SATA_TXN2 1 AC12 SATA_TX2N IDE_D1/GPIO16 AD23 Hynix 0 0 0 ATA 66/100/133 IDE_D2/GPIO17 AE22 <31> SATA_RXN2_C AE12 AC22 SATA_RX2N IDE_D3/GPIO18 <31> SATA_RXP2_C AD12 AD21 SATA_RX2P IDE_D4/GPIO19 C518 1 2 0.01U_0402_25V7K SATA_STX_DRX_P3 AD13 IDE_D5/GPIO20 AE20 AB20 Qimonda 0 0 1 <24> SATA_TXP3 SATA_TX3P IDE_D6/GPIO21 C519 1 2 0.01U_0402_25V7K SATA_STX_DRX_N3 AE13 AD19 <24> SATA_TXN3 SATA_TX3N IDE_D7/GPIO22 AE19 SERIAL ATA IDE_D8/GPIO23 <24> SATA_RXN3_C AB14 AC14 SATA_RX3N IDE_D9/GPIO24 AC20 AD20 Samsung 0 1 0 <24> SATA_RXP3_C SATA_RX3P IDE_D10/GPIO25 AE21 IDE_D11/GPIO26 AE14 SATA_TX4P IDE_D12/GPIO27 AB22 AD14 SATA_TX4N IDE_D13/GPIO28 AD22 AD15 IDE_D14/GPIO29 AE23 AC23 LFB_ID0 to LFB_ID2 got internal PU 10K to S5.2 SATA_RX4N IDE_D15/GPIO30 2 AE15 SATA_RX4P LFB_ID2 R344 1 2 1K_0402_5% AB16 R1032 SATA_TX5P LFB_ID1 R367 1 AC16 SATA_TX5N +3VALW 1 2 2 10K_0402_5% G6 @ 1K_0402_5% SPI_DI/GPIO12 LFB_ID0 R345 1 AE16 D2 +3VALW 1 2 2 10K_0402_5% SATA_RX5N SPI_DO/GPIO11 @ 1K_0402_5% AD16 SATA_RX5P SPI_CLK/GPIO47 D1 F4 R1033 SPI ROM SATA_CAL SPI_HOLD#/GPIO31 2 1 V12 SATA_CAL SPI_CS1#/GPIO32 F3 R342 1K_0402_1% SATA_X1 Y12 U15 R343 10K_0402_5% SATA_X1 LAN_RST#/GPIO13 J1 SATA_X2 ROM_RST#/GPIO14 +3VS 1 2 AA12 SATA_X2 M8 FANOUT0/GPIO3 <34> SATA_LED# W11 M5 CR_WAKE# <27> +1.2V_HT SATA_ACT#/GPIO67 FANOUT1/GPIO48 +3VALW M7 L54 FANOUT2/GPIO49 2 1 +PLLVDD_SATA AA11 P5 BLM18PG121SN1D_0603 PLLVDD_SATA FANIN0/GPIO50 P8 HDD_HALTLED# <34> FANIN1/GPIO51 SATA PWR 2 2 W12 XTLVDD_SATA FANIN2/GPIO52 R8 SB_INT_FLASH_SEL 1 C522 C523 C6 THERMAL_DC R1062 1 2 0_0402_5% R1071 1U_0402_6.3V4Z TEMP_COMM 1U_0402_6.3V4Z B6 WLOFF# <26> 1 1 TEMPIN0/GPIO61 150K_0402_5% A6 BT_COMBO_EN# <26> TEMPIN1/GPIO62 A5 WWOFF# <26> 2 TEMPIN2/GPIO63 B5 EC_THERM# <33> TEMPIN3/TALERT#/GPIO64 HW MONITOR +3VS A4 AC_IN_SB 2 1 VIN0/GPIO53 AC_IN <33,38> L55 B4 D56 +XTLVDD_SATA VIN1/GPIO54 BT_OFF <31> 2 1 C4 CH751H-40PT_SOD323-2 VIN2/GPIO55 CAM_SHDN# <17> BLM18PG121SN1D_0603 2 D4 VIN3/GPIO56 LFB_ID0 D53 C524 VIN4/GPIO57 LFB_ID1 3 VIN5/GPIO58 D6 1U_0402_6.3V4Z LFB_ID2 1 VIN6/GPIO59 A7 B7 02/18 Add R1071 and D56 to connect to AC_IN. VIN7/GPIO60 +3VALW L56 F6 +SB_AVDD 2 1 AVDD BLM18PG121SN1D_0603 1 1 G7 AVSS C526 2.2U_0603_6.3V4Z 2 2 218-0660011 A14 SB7_FCBGA528 C525 0.1U_0402_16V4Z4 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SB710 SATA/IDE/SPI Size Document Number R ev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, March 16, 2009 Sheet 21 of 56 A B C D E
    • A B C D E L 0.6A/50mil/4vias U15E U15C 1 2 +1.2VALW 0.45A/40mil/3vias ? R592 @ 0_0805_5% L SB700 +1.2V_SB_CORE +3VS L9 M9 VDDQ_1 Part 3 of 5 VDD_1 L15 M12 1 R593 2 0_0805_5% +1.2V_HT SB700 A2 VDDQ_2 VDD_2 VSS_1 2 1 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A251 C528 22U_0805_6.3V6M 10U_0805_6.3V6M C529 1 U9 N13 B1 CORE S0 C531 1U_0402_6.3V4Z VDDQ_4 VDD_4 1U_0402_6.3V4Z C532 VSS_3 1 2 U16 VDDQ_5 VDD_5 P12 2 1 VSS_4 D7 C530 1 2 1U_0402_6.3V4Z U17 P14 1U_0402_6.3V4Z 2 1 C534 T10 F20 VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5 PCI/GPIO I/O C533 1 2 1U_0402_6.3V4Z V8 R11 1U_0402_6.3V4Z 2 1 C538 U10 G19 C549 1U_0402_6.3V4Z VDDQ_7 VDD_7 1U_0402_6.3V4Z C537 AVSS_SATA_2 VSS_6 1 2 W7 R15 2 1 U11 H8 C535 1U_0402_6.3V4Z VDDQ_8 VDD_8 0.1U_0402_16V4Z C527 AVSS_SATA_3 VSS_7 1 2 Y6 VDDQ_9 VDD_9 T16 2 1 U12 AVSS_SATA_4 VSS_8 K9 C539 1 2 1U_0402_6.3V4Z AA4 0.1U_0402_16V4Z 2 1 C540 V11 K11 C541 0.1U_0402_16V4Z VDDQ_10 AVSS_SATA_5 VSS_9 1 2 AB5 VDDQ_11 V14 AVSS_SATA_6 VSS_10 K16 C542 1 2 0.1U_0402_16V4Z AB21 W9 L4 VDDQ_12 AVSS_SATA_7 VSS_11 Y9 L7 AVSS_SATA_8 VSS_12 L 0.45A/30mil/3vias Y11 AVSS_SATA_9 VSS_13 L10 @ 0_0603_5% L 0.3A/30mil/2vias L60 Y14 AVSS_SATA_10 VSS_14 L11 Y17 AVSS_SATA_11 VSS_15 L12 R12 1 2 +3.3V_SB_IDE Y20 L21 +1.2V_CKVDD 2 1 AA9 L14 +3VS VDD33_18_1 CKVDD_1.2V_1 +1.2V_HT AVSS_SATA_12 VSS_16 AA21 L22 0_0805_5% AB9 L16 VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_13 VSS_17 2 1 AA22 L24 AB11 M6 VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18 IDE/FLSH I/O CLKGEN I/O C543 @ 22U_0805_6.3V6M AE25 L25 C546 1 2 1U_0402_6.3V4Z AB13 M10 C544 VDD33_18_4 CKVDD_1.2V_4 AVSS_SATA_15 VSS_19 1 2 @ 1U_0402_6.3V4Z C545 1 2 1U_0402_6.3V4Z AB15 M11 C547 AVSS_SATA_16 VSS_20 1 2 @ 1U_0402_6.3V4Z C548 2 1 0.1U_0402_16V4Z AB17 AVSS_SATA_17 VSS_21 M13 C536 1 2 @ 1U_0402_6.3V4Z C551 2 1 0.1U_0402_16V4Z AC8 M15 C550 10U_0805_10V4Z AVSS_SATA_18 VSS_22 1 2 AD8 N4 AVSS_SATA_19 VSS_23 AE8 N12 AVSS_SATA_20 VSS_24 VSS_25 N14 +PCIE_VDDR P6 L61 POWER VSS_26 VSS_27 P9 +1.2V_HT 2 1 VSS_28 P10 0_0805_5% A15 P11 AVSS_USB_1 VSS_29 L 0.8A/50mil/4vias P18 PCIE_VDDR_1 +3VALW B15 AVSS_USB_2 VSS_30 P13 2 1 P19 PCIE_VDDR_2 L 0.1A/30mil/2vias ? C14 AVSS_USB_3 VSS_31 P15 C552 4.7U_0805_10V4Z P20 D8 R1 C553 1U_0402_6.3V4Z PCIE_VDDR_3 +S5_3V AVSS_USB_4 VSS_32 1 2 P21 A17 1 2 D9 R2 PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33 A-LINK I/O C555 1 2 1U_0402_6.3V4Z R22 A24 R564 0_0805_5% D11 R42 C554 1U_0402_6.3V4Z PCIE_VDDR_5 S5_3.3V_2 AVSS_USB_6 VSS_34 2