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  1. 1. Synthesis and SimulationDesign GuideUG626 (v 11.4) December 2, 2009
  2. 2. Xilinx Trademarks and Copyright InformationXilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to yousolely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce,distribute, republish, download, display, post, or transmit the Documentation in any form or by any meansincluding, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the priorwritten consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinxassumes no obligation to correct any errors contained in the Documentation, or to advise you of any correctionsor updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may beprovided to you in connection with the Information.THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINXMAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDINGTHE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR APARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILLXILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTALDAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THEDOCUMENTATION.© Copyright 2002-2009 Xilinx Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and otherdesignated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of theirrespective owners. The PowerPC name and logo are registered trademarks of IBM Corp., and used under license.All other trademarks are the property of their respective owners. Synthesis and Simulation Design Guide2 www.xilinx.com UG626 (v 11.4) December 2, 2009
  3. 3. Table of Contents Xilinx Trademarks and Copyright Information......................................................................................... 2Chapter 1 About the Synthesis and Simulation Design Guide ........................................................................ 11 Synthesis and Simulation Design Guide Overview................................................................................. 11 Synthesis and Simulation Design Guide Design Examples ...................................................................... 12 Synthesis and Simulation Design Guide Contents .................................................................................. 12 Additional Resources ........................................................................................................................... 12 Conventions ........................................................................................................................................ 13 Typographical............................................................................................................................... 13 Online Document .......................................................................................................................... 13Chapter 2 Hardware Description Language (HDL) ....................................................................................... 15 Advantages of Using a Hardware Description Language (HDL) to Design FPGA Devices ........................ 15 Top-Down Approach for Large Projects .......................................................................................... 15 Functional Simulation Early in the Design Flow .............................................................................. 16 Synthesis of Hardware Description Language (HDL) Code to Gates ................................................. 16 Early Testing of Various Design Implementations............................................................................ 16 Reuse of Register Transfer Level (RTL) Code................................................................................... 16 Designing FPGA Devices With Hardware Description Language (HDL).................................................. 16 About Designing FPGA Devices With Hardware Description Language (HDL)................................. 16 Designing FPGA Devices with VHDL............................................................................................. 17 Designing FPGA Devices with Verilog............................................................................................ 17 Designing FPGA Devices with Synthesis Tools................................................................................ 17 Improving Device Performance Using FPGA System Features.......................................................... 17 Designing Hierarchy ..................................................................................................................... 18 Specifying Speed Requirements ..................................................................................................... 18Chapter 3 FPGA Design Flow...................................................................................................................... 19 Design Flow Diagram .......................................................................................................................... 20 Design Entry Recommendations ........................................................................................................... 20 Use Register Transfer Level (RTL) Code.......................................................................................... 20 Select the Correct Design Hierarchy ............................................................................................... 21 Architecture Wizard............................................................................................................................. 21 Opening Architecture Wizard ........................................................................................................ 21 Architecture Wizard Components .................................................................................................. 21 Clocking Wizard..................................................................................................................... 21 RocketIO Wizard .................................................................................................................... 22 ChipSync Wizard ................................................................................................................... 22 XtremeDSP Slice Wizard ......................................................................................................... 23 CORE Generator Software .................................................................................................................... 23 EDN and NGC Files ...................................................................................................................... 23 VHO Files..................................................................................................................................... 23 VEO Files ..................................................................................................................................... 23 V and VHD Wrapper Files ............................................................................................................. 23 ASCII Symbol (ASY) Files .............................................................................................................. 24 Functional Simulation Early in the Design Flow..................................................................................... 24 Synthesizing and Optimizing................................................................................................................ 24 Creating a Compile Run Script ....................................................................................................... 24 Running the TCL Script (Precision RTL Synthesis) .................................................................... 24 Running the TCL Script (Synplify) ........................................................................................... 25 Running the TCL Script (XST) ................................................................................................. 26 Modifying Your Code to Successfully Synthesize Your Design ......................................................... 26 Reading Cores............................................................................................................................... 26 Reading Cores (XST)............................................................................................................... 26 Reading Cores (Synplify Pro) .................................................................................................. 26 Reading Cores (Precision RTL Synthesis) ................................................................................. 26 Setting Constraints............................................................................................................................... 26 Specifying Constraints in the User Constraints File (UCF) ................................................................ 27Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 3
  4. 4. Setting Constraints in ISE Design Suite ........................................................................................... 27 Evaluating Design Size and Performance............................................................................................... 27 Estimating Device Utilization and Performance............................................................................... 27 Determining Actual Device Utilization and Pre-Routed Performance................................................ 28 Mapping Your Design Using ISE Design Suite ......................................................................... 28 Mapping Your Design Using the Command Line...................................................................... 29 Evaluating Coding Style and System Features........................................................................................ 29 Modifying Your Code to Improve Design Performance .................................................................... 29 Improving Resource Utilization Using FPGA System Features ......................................................... 29 Using Xilinx Specific Features of Your Synthesis Tool....................................................................... 30 Placing and Routing............................................................................................................................. 30 Timing Simulation ............................................................................................................................... 30Chapter 4 General Recommendations for Coding Practices ........................................................................... 31 Designing With Hardware Description Language (HDL)........................................................................ 31 Naming, Labeling, and General Coding Styles ....................................................................................... 32 Common Coding Style .................................................................................................................. 32 Xilinx Naming Conventions ........................................................................................................... 32 Reserved Names ........................................................................................................................... 32 Naming Guidelines for Signals and Instances.................................................................................. 33 General Naming Rules for Signals and Instances ...................................................................... 33 VHDL and Verilog Capitalization ............................................................................................ 33 Matching File Names to Entity and Module Names ......................................................................... 33 Naming Identifiers ........................................................................................................................ 34 Instantiating Sub-Modules ............................................................................................................. 34 Recommended Length of Line........................................................................................................ 35 Common File Headers ................................................................................................................... 35 Indenting and Spacing................................................................................................................... 36 Specifying Constants............................................................................................................................ 36 Using Generics and Parameters to Specify Dynamic Bus and Array Widths ............................................. 37 TRANSLATE_OFF and TRANSLATE_ON............................................................................................. 38Chapter 5 Coding for FPGA Device Flow ..................................................................................................... 39 VHDL and Verilog Limitations ............................................................................................................. 40 Design Challenges in Using an Asynchronous First-In-First-Out (FIFO) Buffer ........................................ 40 Advantages and Disadvantages of Hierarchical Designs ......................................................................... 41 Using Synthesis Tools with Hierarchical Designs ................................................................................... 41 Restrict Shared Resources .............................................................................................................. 42 Compile Multiple Instances ........................................................................................................... 42 Restrict Related Combinatorial Logic.............................................................................................. 42 Separate Speed Critical Paths ......................................................................................................... 42 Restrict Combinatorial Logic.......................................................................................................... 42 Restrict Module Size...................................................................................................................... 42 Register All Outputs...................................................................................................................... 42 Restrict One Clock to Each Module or to Entire Design .................................................................... 42 Choosing Data Type............................................................................................................................. 43 Use Std_logic (IEEE 1164) .............................................................................................................. 43 Declaring Ports ............................................................................................................................. 43 Arrays in Port Declarations ............................................................................................................ 44 Incompatibility with Verilog.................................................................................................... 44 Inability to Store and Re-Create Original Array Declaration ...................................................... 44 Mis-Correlation of Software Pin Names ................................................................................... 44 Minimize Ports Declared as Buffers ................................................................................................ 44 Using ‘timescale................................................................................................................................... 45 Mixed Language Designs ..................................................................................................................... 45 If Statements and Case Statements ........................................................................................................ 46 4–to–1 Multiplexer Design With If Statement Coding Examples ....................................................... 46 4–to–1 Multiplexer Design With Case Statement Coding Examples................................................... 47 Sensitivity List in Process and Always Statements .................................................................................. 48 Delays in Synthesis Code...................................................................................................................... 49 Registers in FPGA Design..................................................................................................................... 50 Synthesis and Simulation Design Guide4 www.xilinx.com UG626 (v 11.4) December 2, 2009
  5. 5. Input Output Block (IOB) Registers ....................................................................................................... 51 Dual-Data Rate (DDR) Registers..................................................................................................... 51 Latches in FPGA Design ....................................................................................................................... 52 Implementing Shift Registers ................................................................................................................ 53 Describing Shift Registers ..................................................................................................................... 54 Control Signals .................................................................................................................................... 56 Set, Resets, and Synthesis Optimization .......................................................................................... 56 Global Set/Reset (GSR) ............................................................................................................ 56 Shift Register LUT (SRL) ......................................................................................................... 56 Synchronous and Asynchronous Resets ................................................................................... 56 Asynchronous Resets Coding Examples................................................................................... 57 Synchronous Resets Coding Examples ..................................................................................... 57 Using Clock Enable Pin Instead of Gated Clocks ............................................................................. 60 Converting the Gated Clock to a Clock Enable ................................................................................ 60 Initial State of the Registers and Latches ................................................................................................ 61 Initial State of the Shift Registers ........................................................................................................... 62 Initial State of the RAMs....................................................................................................................... 62 Multiplexers ........................................................................................................................................ 62 Finite State Machine (FSM) Components ............................................................................................... 64 Finite State Machine (FSM) Description Style .................................................................................. 64 Finite State Machine (FSM) With One Process ................................................................................. 65 Finite State Machine (FSM) With Two or Three Processes ................................................................. 67 Finite State Machine (FSM) Recognition and Optimization............................................................... 68 Other Finite State Machine (FSM) Features...................................................................................... 68 Implementing Memory ........................................................................................................................ 68 Block RAM Inference ........................................................................................................................... 70 Dual-Port Block RAM in Read-First Mode With Two Write Ports ...................................................... 77 Distributed RAM Inference................................................................................................................... 79 Arithmetic Support .............................................................................................................................. 81 Order and Group Arithmetic Functions .......................................................................................... 89 Resource Sharing .......................................................................................................................... 90 Synthesis Tool Naming Conventions ..................................................................................................... 92 Instantiating FPGA Primitives .............................................................................................................. 92 Instantiating CORE Generator Software Modules................................................................................... 93 Attributes and Constraints.................................................................................................................... 94 Attributes ..................................................................................................................................... 94 Synthesis Constraints .................................................................................................................... 94 Implementation Constraints........................................................................................................... 94 Passing Attributes ......................................................................................................................... 94 Passing Synthesis Constraints ........................................................................................................ 95 About Passing Synthesis Constraints........................................................................................ 95 Passing VHDL Synthesis Attributes ......................................................................................... 96 Passing Verilog Synthesis Attributes ........................................................................................ 97 Pipelining............................................................................................................................................ 97 Before Pipelining........................................................................................................................... 97 After Pipelining ............................................................................................................................ 98 Retiming ............................................................................................................................................. 98Chapter 6 Using SmartModel Technology .................................................................................................... 99 Using SmartModel Technology with ISim.............................................................................................. 99 Using SmartModel Components to Simulate Designs ............................................................................. 99 SmartModel Simulation Flow .............................................................................................................. 100 SmartModel Technology...................................................................................................................... 100 SmartModel Supported Simulators and Operating Systems ................................................................... 100 Installing SmartModels ....................................................................................................................... 101 Installing SmartModels (Method One) ........................................................................................... 101 Installing SmartModels (Method Two)........................................................................................... 101 Installing SmartModels (Method Two on Linux) ...................................................................... 102 Installing SmartModels (Method Two on 64-bit Linux)............................................................. 103 Setting Up and Running Simulation ..................................................................................................... 103Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 5
  6. 6. Chapter 7 Simulating Your Design .............................................................................................................. 105 Adhering to Industry Standards .......................................................................................................... 105 Simulation Flows ......................................................................................................................... 106 Standards Supported by Xilinx Simulation Flow ............................................................................ 106 Xilinx Supported Simulators and Operating Systems ...................................................................... 106 Xilinx Libraries ............................................................................................................................ 107 Simulation Points in Hardware Description Language (HDL) Design Flow............................................. 107 Five Simulation Points in Hardware Description Language (HDL) Design Flow ............................... 108 Simulation Flow Libraries............................................................................................................. 109 VHDL Standard Delay Format (SDF) File....................................................................................... 109 Verilog Standard Delay Format (SDF) File...................................................................................... 109 Register Transfer Level (RTL) ........................................................................................................ 109 Post-Synthesis (Pre-NGDBuild) Gate-Level Simulation ................................................................... 110 Post-NGDBuild (Pre-Map) Gate-Level Simulation .......................................................................... 110 Post-Map Partial Timing (Block Delays) ......................................................................................... 110 Timing Simulation Post-Place and Route (Block and Net Delays)..................................................... 111 Using Test Benches to Provide Stimulus ............................................................................................... 111 Creating a Test Bench ................................................................................................................... 112 Test Bench Recommendations ....................................................................................................... 112 VHDL and Verilog Libraries and Models.............................................................................................. 112 Required Simulation Point Libraries .............................................................................................. 112 First Simulation Point: Register Transfer Level (RTL) ............................................................... 113 Second Simulation Point: Post-Synthesis (Pre-NGDBuild) Gate-Level Simulation ...................... 113 Third Simulation Point: Post-NGDBuild (Pre-Map) Gate-Level Simulation................................ 113 Fourth Simulation Point: Post-Map Partial Timing (Block Delays)............................................. 113 Fifth Simulation Point: Timing Simulation Post-Place and Route (Block and Net Delays)............ 113 Simulation Phase Library Information ........................................................................................... 114 Library Source Files and Compile Order ........................................................................................ 114 Simulation Libraries ..................................................................................................................... 117 UNISIM Library .................................................................................................................... 118 VHDL UNISIM Library.......................................................................................................... 118 Verilog UNISIM Library......................................................................................................... 118 UniMacro Library.................................................................................................................. 118 VHDL UniMacro Library ....................................................................................................... 119 Verilog UniMacro Library ...................................................................................................... 119 CORE Generator Software XilinxCoreLib Library .................................................................... 119 SIMPRIM Library .................................................................................................................. 119 SmartModel Libraries ............................................................................................................ 119 SecureIP Libraries.................................................................................................................. 120 VHDL SecureIP Library ......................................................................................................... 120 Verilog SecureIP Library ........................................................................................................ 120 Xilinx Simulation Libraries (Compxlib) ................................................................................... 120 Reducing Simulation Runtimes ..................................................................................................... 121 Simulation of Configuration Interfaces ................................................................................................. 122 JTAG Simulation .......................................................................................................................... 122 SelectMAP Simulation .................................................................................................................. 122 System Level Description ....................................................................................................... 123 Debugging with the Model..................................................................................................... 123 Supported Features................................................................................................................ 124 Spartan-3AN In-System Flash Simulation ...................................................................................... 125 SPI_ACCESS Supported Commands....................................................................................... 126 SPI_ACCESS Memory Initialization ........................................................................................ 127 SPI_ACCESS Attributes ......................................................................................................... 127 SPI_ACCESS SIM_DEVICE Attribute...................................................................................... 127 SPI_ACCESS SIM_USER_ID Attribute .................................................................................... 127 SPI_ACCESS SIM_MEM_FILE Attribute ................................................................................. 127 SPI_ACCESS SIM_FACTORY_ID Attribute ............................................................................. 127 SPI_ACCESS SIM_DELAY_TYPE Attribute ............................................................................. 128 Disabling BlockRAM Collision Checks for Simulation ........................................................................... 129 Synthesis and Simulation Design Guide6 www.xilinx.com UG626 (v 11.4) December 2, 2009
  7. 7. SIM_COLLISION_CHECK Strings ................................................................................................ 129 Global Reset and Tristate for Simulation ............................................................................................... 129 Using Global Tristate (GTS) and Global Set/Reset (GSR) Signals in an FPGA Device ......................... 130 Global Set/Reset (GSR) and Global Tristate (GTS) in Verilog ............................................................ 130 Design Hierarchy and Simulation ........................................................................................................ 130 Improving Design Utilization and Performance.............................................................................. 130 Good Design Practices .................................................................................................................. 131 Maintaining the Hierarchy............................................................................................................ 131 Register Transfer Level (RTL) Simulation Using Xilinx Libraries ............................................................ 133 Delta Cycles and Race Conditions ................................................................................................. 133 Recommended Simulation Resolution ........................................................................................... 134 Encryption Methodology Used for SecureIP Models ....................................................................... 134 Generating Gate-Level Netlist (Running NetGen) ................................................................................. 135 Disabling X Propagation for Synchronous Elements .............................................................................. 135 Using the ASYNC_REG Constraint ...................................................................................................... 135 MIN/TYP/MAX Simulation ................................................................................................................. 136 Minimum (MIN) .......................................................................................................................... 136 Typical (TYP) ............................................................................................................................... 136 Maximum (MAX)......................................................................................................................... 136 Obtaining Accurate Timing Simulation Results .............................................................................. 136 Run NetGen .......................................................................................................................... 137 Run Setup Simulation ............................................................................................................ 137 Run Hold Simulation ............................................................................................................. 137 Absolute Min Simulation .............................................................................................................. 137 Using the VOLTAGE and TEMPERATURE Constraints .................................................................. 138 Using the VOLTAGE Constraint ............................................................................................. 138 Using the TEMPERATURE Constraint .................................................................................... 138 Determining Valid Operating Temperatures and Voltages ....................................................... 138 NetGen Options for Different Delay Values ............................................................................. 139 Special Considerations for CLKDLL, DCM, and DCM_ADV.................................................................. 139 DLL/DCM Clocks Do Not Appear De-Skewed ............................................................................... 139 TRACE/Simulation Model Differences for DCM/DLL ..................................................................... 139 Non-LVTTL Input Drivers ............................................................................................................ 140 Viewer Considerations ................................................................................................................. 140 Attributes for Simulation and Implementation ............................................................................... 141 Understanding Timing Simulation ....................................................................................................... 141 Importance of Timing Simulation .................................................................................................. 141 Functional Simulation............................................................................................................ 141 Static Timing Analysis and Equivalency Checking ................................................................... 141 In-System Testing .................................................................................................................. 142 Glitches in Your Design ................................................................................................................ 142 VHDL Simulation.................................................................................................................. 142 Verilog Simulation ................................................................................................................. 142 Debugging Timing Problems ........................................................................................................ 142 Timing Problem Root Causes ........................................................................................................ 143 Simulation Clock Does Not Meet Timespec ............................................................................. 143 Unaccounted Clock Skew....................................................................................................... 143 Asynchronous Inputs, Asynchronous Clock Domains, Crossing Out-of-Phase........................... 144 Asynchronous Clocks ............................................................................................................ 144 Asynchronous Inputs............................................................................................................. 144 Out of Phase Data Paths ......................................................................................................... 144 Debugging Tips ........................................................................................................................... 144 Setup and Hold Violations ............................................................................................................ 145 Zero Hold Time Considerations.............................................................................................. 145 Negative Hold Time Considerations ....................................................................................... 145 RAM Considerations ............................................................................................................. 145 Timing Violations ........................................................................................................... 145 Collision Checking.......................................................................................................... 145 Hierarchy Considerations................................................................................................ 146Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 7
  8. 8. Simulation Using Xilinx Supported EDA Simulation Tools .................................................................... 146Chapter 8 Design Considerations................................................................................................................ 147 Understanding the Architecture........................................................................................................... 147 Slice Structure .............................................................................................................................. 147 Hard IP Blocks ............................................................................................................................. 148 Use Block Features Optimally................................................................................................. 148 Evaluate the Percentage of BRAMs or DSP Blocks.................................................................... 148 Lock Down Block Placement .................................................................................................. 148 Compare Hard-IP Blocks and Slice Logic ................................................................................ 148 Use SelectRAM Memory ........................................................................................................ 148 Compare Placing Logic Functions in Slice Logic or DSP Block .................................................. 148 Clocking Resources ............................................................................................................................. 149 Evaluating Clocking Implementation............................................................................................. 149 Clock Reporting ........................................................................................................................... 150 Reviewing the Place and Route Report.................................................................................... 150 Clock Region Reports ............................................................................................................ 150 Global Clock Region Report ................................................................................................... 150 Secondary Clock Region Report.............................................................................................. 151 Defining Timing Requirements ............................................................................................................ 151 Over-Constraining ....................................................................................................................... 151 Constraint Coverage..................................................................................................................... 151 Driving Synthesis................................................................................................................................ 152 Use Proper Coding Techniques ..................................................................................................... 152 Analyze Inference of Logic............................................................................................................ 152 Provide a Complete Picture of Your Design.................................................................................... 152 Use Optimal Software Settings ...................................................................................................... 152 Helpful Synthesis Attributes ......................................................................................................... 153 Additional Timing Options ........................................................................................................... 153 Choosing Implementation Options....................................................................................................... 154 Performance Evaluation Mode ...................................................................................................... 154 Packing and Placement Option...................................................................................................... 154 Physical Synthesis Options ........................................................................................................... 154 SmartXplorer ............................................................................................................................... 154 Timing Closure Mode ............................................................................................................ 155 Best Performance Mode ......................................................................................................... 155 Evaluating Critical Paths ..................................................................................................................... 155 Many Logic Levels ....................................................................................................................... 155 Few Logic Levels.......................................................................................................................... 155 Design Preservation With SmartCompile Technology ............................................................................ 156 Deciding Whether to Use Partitions or SmartGuide Technology ...................................................... 156 When to Use SmartGuide Technology ..................................................................................... 156 When to Use Partitions........................................................................................................... 156 Design Preservation with Partitions............................................................................................... 156 Defining Partitions for Design Preservation ............................................................................. 157 Tips for Using Partitions for Design Preservation..................................................................... 158 Design Preservation with SmartGuide Technology ......................................................................... 158 Optimal Changes for SmartGuide Technology ......................................................................... 158 Constraint Changes That Impact SmartGuide Technology ........................................................ 159 Reimplementing Without SmartGuide Technology .................................................................. 159Appendix A Simulating Xilinx Designs in ModelSim ................................................................................... 161 Simulating Xilinx Designs in ModelSim................................................................................................ 161 Running Simulation from ISE Design Suite (VHDL or Verilog)........................................................ 161 Running Functional Simulation in ModelSim (Standalone) ............................................................. 161 Running Functional Simulation in MTI Standalone (VHDL) ..................................................... 161 Running Functional Simulation in MTI Standalone (Verilog) .................................................... 162 Running Back Annotated Simulation in ModelSim (Standalone)...................................................... 162 Running Back Annotated Simulation in MTI Standalone (VHDL) ............................................. 162 Running Back Annotated Simulation in MTI Standalone (Verilog) ............................................ 163 Simulating SecureIP with ModelSim and Questa................................................................................... 163 Synthesis and Simulation Design Guide8 www.xilinx.com UG626 (v 11.4) December 2, 2009
  9. 9. Appendix B Simulating Xilinx Designs in NCSim ........................................................................................ 165 Running Simulation from ISE Design Suite........................................................................................... 165 Running Simulation in NC-Verilog ...................................................................................................... 165 Running Simulations in NC-Verilog (Method One)......................................................................... 165 Running Simulations in Cadence NC-Verilog (Method Two) ........................................................... 165 Back-Annotating Delay Values from Standard Delay Format (SDF) File .................................... 166 Simulating SecureIP with NC-Verilog ............................................................................................ 166 Multi-Step Process with Precompiled Libraries........................................................................ 166 Single Step Process ................................................................................................................ 166 Running Simulation in NC-VHDL ....................................................................................................... 167 Running Behavioral Simulation With NC-VHDL............................................................................ 167 Running Timing Simulation With Cadence NC-VHDL ................................................................... 167Appendix C Simulating Xilinx Designs in Synopsys VCS-MX and Synopsys VCS-MXi................................... 169 Simulating Xilinx® Designs from ISE Design Suite in Synopsys VCS-MX and Synopsys VCS-MXi ........... 169 Simulating Xilinx Designs in Standalone Synopsys VCS-MX and Synopsys VCS-MXi.............................. 169 Using Library Source Files With Compile Time Options ................................................................. 169 Using Shared Pre-Compiled Libraries............................................................................................ 170 Using Unified Usage Model (Three-Step Process) ........................................................................... 170 Three-Step Process Analysis Phase ......................................................................................... 171 Three-Step Process Elaboration Phase ..................................................................................... 171 Three-Step Process Simulation Phase ...................................................................................... 171 Using Standard Delay Format (SDF) with VCS ............................................................................... 171 Compiling the Standard Delay Format (SDF) file at Compile Time............................................ 171 Reading the ASCII Standard Delay Format (SDF) File at Runtime ............................................. 171 Simulating SecureIP with VCS ............................................................................................................. 172 About Simulating SecureIP with VCS ............................................................................................ 172 Using Library Source Files With Compile Time Options ................................................................. 172 Using SIMPRIM-Based Libraries for Timing Simulation.................................................................. 172Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 9
  10. 10. Synthesis and Simulation Design Guide10 www.xilinx.com UG626 (v 11.4) December 2, 2009
  11. 11. Chapter 1About the Synthesis and SimulationDesign GuideThis chapter provides general information about the Synthesis and Simulation Design Guide. This chapter includes:• Synthesis and Simulation Design Guide Overview• Synthesis and Simulation Design Guide Design Examples• Synthesis and Simulation Design Guide Contents• Additional Resources• ConventionsSynthesis and Simulation Design Guide OverviewThe Synthesis and Simulation Design Guide provides a general overview of designing Field Programmable GateArray (FPGA) devices using a Hardware Description Language (HDL). It includes design hints for the noviceHDL user, as well as for the experienced user who is designing FPGA devices for the first time. Before usingthe Synthesis and Simulation Design Guide, you should be familiar with the operations that are common to allXilinx® tools.The Synthesis and Simulation Design Guide does not address certain topics that are important when creatingHDL designs, such as:• Design environment• Verification techniques• Constraining in the synthesis tool• Test considerations• System verificationFor more information, see your synthesis tool documentation.Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 11
  12. 12. Chapter 1: About the Synthesis and Simulation Design GuideSynthesis and Simulation Design Guide Design ExamplesThe design examples in this Guide were:• Created with VHDL and Verilog Xilinx® endorses Verilog and VHDL equally. VHDL may be more difficult to learn than Verilog, and usually requires more explanation.• Compiled with various synthesis tools• Targeted for the following devices: – Spartan®-3 – Spartan-3E – Spartan-3A – Spartan-6 – Virtex®-4 – Virtex-5 – Virtex-6Synthesis and Simulation Design Guide ContentsThe Synthesis and Simulation Design Guide contains the following:• Chapter One, About the Synthesis and Simulation Design Guide, gives general information about this Guide• Chapter Two, Hardware Description Language (HDL), describes how to design Field Programmable Gate Arrays (FPGA devices) using a Hardware Description Language (HDL).• Chapter Three, FPGA Design Flow, describes the steps in a typical FPGA design flow.• Chapter Four, General Recommendations for Coding Practices, contains general information relating to Hardware Description Language (HDL) coding styles and design examples to help you develop an efficient coding style.• Chapter Five, Coding for FPGA Flow, contains specific information relating to coding for FPGA devices.• Chapter Six, Using SmartModels, describes special considerations when simulating designs for Virtex®-4 devices and Virtex-5 devices. These devices are for designs based on IP cores and customized modules. The family incorporates RocketIO™ and PowerPC® CPU and Ethernet MAC cores in the FPGA architecture• Chapter Seven, Simulating Your Design, describes the basic Hardware Description Language (HDL) simulation flow using Xilinx® and third party tools.• Chapter Eight, Design Considerations, describes understanding the architecture, clocking resources, defining timing requirements, driving synthesis, choosing implementation options, and evaluating critical paths.• Appendix A provides information on Simulating Xilinx Designs in ModelSim.• Appendix B provides information on Simulating Xilinx Designs in NCSim.• Appendix C provides information on Simulating Xilinx Designs in Synopsys VCS-MX and Synopsys VCS-MXi.Additional ResourcesTo find additional documentation, see the Xilinx website at:http://www.xilinx.com/literature.To search the Answer Database of silicon, software, and IP questions and answers, or to create a technicalsupport WebCase, see the Xilinx website at:http://www.xilinx.com/support. Synthesis and Simulation Design Guide12 www.xilinx.com UG626 (v 11.4) December 2, 2009
  13. 13. Chapter 1: About the Synthesis and Simulation Design GuideConventionsThis document uses the following conventions. An example illustrates each convention.TypographicalThe following typographical conventions are used in this document: Convention Meaning or Use Example Courier font Messages, prompts, and program files speed grade: - 100 that the system displays Courier bold Literal commands that you enter in a ngdbuild design_name syntactical statement Helvetica bold Commands that you select from a File > Open menu Keyboard shortcuts Ctrl+C Italic font Variables in a syntax statement for ngdbuild design_name which you must supply values References to other manuals See the Command Line Tools User Guide for more information. Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. Square brackets [ ] An optional entry or parameter. ngdbuild [option_name] However, in bus specifications, such as design_name bus[7:0], they are required. Braces { } A list of items from which you must lowpwr ={on|off} choose one or more Vertical bar | Separates items in a list of choices lowpwr ={on|off} Vertical ellipsis Repetitive material that has been IOB #1: Name = QOUT IOB #2: omitted Name = CLKIN . . . Horizontal ellipsis . . . Repetitive material that has been allow block . . . block_name omitted loc1 loc2 ... locn;Online DocumentThe following conventions are used in this document: Convention Meaning or Use Example Blue text Cross-reference link See the section Additional Resources for details. Refer to Title Formats in Chapter 1 for details. See Figure 2-5 in the Virtex®-6 Handbook.Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 13
  14. 14. Synthesis and Simulation Design Guide14 www.xilinx.com UG626 (v 11.4) December 2, 2009
  15. 15. Chapter 2Hardware Description Language (HDL)This chapter describes Hardware Description Language (HDL). This chapter includes:• Advantages of Using a Hardware Description Language (HDL) to Design FPGA Devices• Designing FPGA Devices With Hardware Description Language (HDL)Designers use an HDL to describe the behavior and structure of system and circuit designs. UnderstandingFPGA architecture allows you to create HDL code that effectively uses FPGA system features. To learn moreabout designing FPGA devices with HDL:• Enroll in training classes offered by Xilinx® and by synthesis tool vendors.• Review the HDL design examples in this Guide.• Download design examples from Xilinx Support.• Take advantage of the many other resources offered by Xilinx, including: – Documentation – Tutorials – Service packs – Telephone hotline – Answers databaseFor more information, see Additional Resources.Advantages of Using a Hardware Description Language (HDL)to Design FPGA DevicesUsing a Hardware Description Language (HDL) to design high-density FPGA devices has the followingadvantages:• Top-Down Approach for Large Projects• Functional Simulation Early in the Design Flow• Synthesis of Hardware Description Language (HDL) Code to Gates• Early Testing of Various Design Implementations• Reuse of Register Transfer Level (RTL) CodeTop-Down Approach for Large ProjectsDesigners use a Hardware Description Language (HDL) to create complex designs. The top-down approach tosystem design works well for large HDL projects that require many designers working together. After the designteam determines the overall design plan, individual designers can work independently on separate code sections.Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 15
  16. 16. Chapter 2: Hardware Description Language (HDL)Functional Simulation Early in the Design FlowYou can verify design functionality early in the design flow by simulating the HDL description. Testing yourdesign decisions before the design is implemented at the Register Transfer Level (RTL) or gate level allows youto make any necessary changes early on.Synthesis of Hardware Description Language (HDL) Code to GatesSynthesizing your hardware description to target the FPGA device implementation:• Decreases design time by allowing a higher-level design specification, rather than specifying the design from the FPGA device base elements.• Reduces the errors that can occur during a manual translation of a hardware description to a schematic design.• Allows you to apply the automation techniques used by the synthesis tool (such as machine encoding styles and automatic I/O insertion) during optimization to the original Hardware Description Language (HDL) code. This results in greater optimization and efficiency.Early Testing of Various Design ImplementationsUsing a Hardware Description Language (HDL) allows you to test different design implementations early in thedesign flow. Use the synthesis tool to perform the logic synthesis and optimization into gates.Xilinx® FPGA devices allow you to implement your design at your computer. Since the synthesis time is short,you have more time to explore different architectural possibilities at the Register Transfer Level (RTL) You canreprogram Xilinx FPGA devices to test several design implementations.Reuse of Register Transfer Level (RTL) CodeYou can retarget Register Transfer Level (RTL) code to new FPGA devices with minimum recoding.Designing FPGA Devices With Hardware Description Language(HDL)This section discusses Designing FPGA Devices With Hardware Description Language (HDL), and includes:• About Designing FPGA Devices With Hardware Description Language (HDL)• Designing FPGA Devices with VHDL• Designing FPGA Devices with Verilog• Designing FPGA Devices with Synthesis Tools• Improving Device Performance Using FPGA System Features• Designing Hierarchy• Specifying Speed RequirementsAbout Designing FPGA Devices With Hardware Description Language(HDL)If you are used to schematic design entry, you may find it difficult at first to create Hardware DescriptionLanguage (HDL) designs. You must make the transition from graphical concepts, such as block diagrams, statemachines, flow diagrams, and truth tables, to abstract representations of design components. To ease thistransition, keep your overall design plan in mind as you code in HDL. Synthesis and Simulation Design Guide16 www.xilinx.com UG626 (v 11.4) December 2, 2009
  17. 17. Chapter 2: Hardware Description Language (HDL)To effectively use an HDL, you must understand the:• Syntax of the language• Synthesis and simulator tools• Architecture of your target device• Implementation toolsDesigning FPGA Devices with VHDLVHSIC Hardware Description Language (VHDL) is a hardware description language for designing integratedcircuits. Since VHDL was not originally intended as an input to synthesis, many VHDL constructs are notsupported by synthesis tools. The high level of abstraction of VHDL makes it easy to describe the system-levelcomponents and test benches that are not synthesized. In addition, the various synthesis tools use differentsubsets of VHDL.The examples in this Synthesis and Simulation Design Guide work with most FPGA synthesis tools. The codingstrategies presented in the remaining sections of this Guide can help you create Hardware Description Language(HDL) descriptions that can be synthesized.Designing FPGA Devices with VerilogVerilog is popular for synthesis designs because:• Verilog is less verbose than traditional VHDL.• Verilog is standardized as IEEE-STD-1364-95 and IEEE-STD-1364-2001.Since Verilog was not originally intended as an input to synthesis, many Verilog constructs are not supportedby synthesis tools. The Verilog coding examples in this Guide were tested and synthesized with current,commonly-used FPGA synthesis tools. The coding strategies presented in the remaining sections of this Guidecan help you create Hardware Description Language (HDL) descriptions that can be synthesized.SystemVerilog is a new emerging standard for both synthesis and simulation. It is not known if, or when, thisstandard will be adopted and supported by the various design tools.Whether or not you plan to use this new standard, Xilinx® recommends that you:• Review the standard to ensure that your current Verilog code can be readily carried forward as the new standard evolves.• Review any new keywords specified by the standard.• Avoid using the new keywords in your current Verilog code.Designing FPGA Devices with Synthesis ToolsMost synthesis tools have special optimization algorithms for Xilinx® FPGA devices. Constraints and compilingoptions perform differently depending on the target device. Some commands and constraints in ASIC synthesistools do not apply to FPGA devices. If you use them, they may adversely impact your results.You should understand how your synthesis tool processes designs before you create FPGA designs. Most FPGAsynthesis vendors include information in their documentation specifically for Xilinx FPGA devices.Improving Device Performance Using FPGA System FeaturesTo improve device performance, area utilization, and power characteristics, create Hardware DescriptionLanguage (HDL) code that uses FPGA system features such as DCM, multipliers, shift registers, and memory.For a description of these and other features, see the device data sheet and user guide.The choice of the size (width and depth) and functional characteristics must be taken into account byunderstanding the target FPGA resources and making the proper system choices to best target the underlyingarchitecture.Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 17
  18. 18. Chapter 2: Hardware Description Language (HDL)Designing HierarchyUsing a Hardware Description Language (HDL) gives added flexibility in describing the design. Not all HDLcode is optimized the same. How and where the functionality is described can have dramatic effects on endoptimization. For example:• Certain techniques may unnecessarily increase the design size and power while decreasing performance.• Other techniques can result in more optimal designs in terms of any or all of those same metrics.This Guide will help instruct you in techniques for optional FPGA design methodologies.Design hierarchy is important in both the implementation of an FPGA and during interactive changes. Somesynthesizers maintain the hierarchical boundaries unless you group modules together. Modules should haveregistered outputs so their boundaries are not an impediment to optimization. Otherwise, modules should be aslarge as possible within the limitations of your synthesis tool.The “5,000 gates per module” rule is no longer valid, and can interfere with optimization. Check with yoursynthesis vendor for the preferred module size. As a last resort, use the grouping commands of your synthesizer,if available. The size and content of the modules influence synthesis results and design implementation. ThisGuide describes how to create effective design hierarchy.Specifying Speed RequirementsTo meet timing requirements, you must set timing constraints in both the synthesis tool and the placement androuting tool. If you specify the desired timing at the beginning, the tools can maximize not only performance,but also area, power, and tool runtime.This may result in a design that:• Achieves the desired performance• Is smaller• Consumes less power• Requires less processing timeFor more information, see Setting Constraints. Synthesis and Simulation Design Guide18 www.xilinx.com UG626 (v 11.4) December 2, 2009
  19. 19. Chapter 3FPGA Design FlowThis chapter describes the steps in a typical FPGA design flow. This chapter includes:• Design Flow Diagram• Design Entry Recommendations• Architecture Wizard• CORE Generator™ Software• Functional Simulation• Synthesizing and Optimizing• Setting Constraints• Evaluating Design Size and Performance• Evaluating Coding Style and System Features• Placing and Routing• Timing SimulationSynthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 19
  20. 20. Chapter 3: FPGA Design FlowDesign Flow DiagramDesign Entry RecommendationsXilinx® recommends the following for design entry:• Use Register Transfer Level (RTL) Code• Select the Correct Design HierarchyUse Register Transfer Level (RTL) CodeUse Register Transfer Level (RTL) code, and, when possible, do not instantiate specific components. Followingthese two practices allows for:• Readable code• Ability to use the same code for synthesis and simulation• Faster and simpler simulation• Portable code for migration to different device families• Reusable code for future designsIn some cases instantiating optimized CORE Generator™ software modules is beneficial with RTL. Synthesis and Simulation Design Guide20 www.xilinx.com UG626 (v 11.4) December 2, 2009
  21. 21. Chapter 3: FPGA Design FlowSelect the Correct Design HierarchySelect the correct design hierarchy to:• Improve simulation and synthesis results• Improve debugging• Allow parallel engineering, in which a team of engineers can work on different parts of the design at the same time• Improve placement and routing by reducing routing congestion and improving timing• Allow for easier code reuse in both current and future designsArchitecture WizardUse Architecture Wizard to configure advanced features of Xilinx® devices. Architecture Wizard consists ofseveral components for configuring specific device features. Each component functions as an independentwizard. For more information, see Architecture Wizard Components.Architecture Wizard creates a VHDL, Verilog, or Electronic Data Interchange Format (EDIF) file, depending onthe flow type passed to it. The generated Hardware Description Language (HDL) output is a module consistingof one or more primitives and the corresponding properties, and not just a code snippet. This allows the outputfile to be referenced from the HDL Editor. No User Constraints File (UCF) is output, since the necessaryattributes are embedded inside the HDL file.Opening Architecture WizardYou can open Architecture Wizard from:• ISE® Design Suite For more information, see the ISE Design Suite Help, especially Working with Architecture Wizard IP.• The CORE Generator™ software Select any of the Architecture Wizard IP from the list of available IP in the CORE Generator software window.• The command line Type arwz.Architecture Wizard ComponentsArchitecture Wizard components include:• Clocking Wizard• RocketIO™ Wizard• ChipSync Wizard• XtremeDSP™ Slice WizardClocking WizardThe Clocking Wizard enables:• Digital clock setup• DCM and clock buffer viewing• DRC checkingSynthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 21
  22. 22. Chapter 3: FPGA Design FlowThe Clocking Wizard allows you to:• View the DCM component• Specify attributes• Generate corresponding components and signals• Execute DRC checks• Display up to eight clock buffers• Set up the Feedback Path information• Set up the Clock Frequency Generator information and execute DRC checks• View and edit component attributes• View and edit component constraints• View and configure one or two Phase Matched Clock Dividers (PMCDs) in a Virtex®-4 device• View and configure a Phase Locked Loop (PLL) in a Virtex-5 device• Automatically place one component in the XAW file• Save component settings in a VHDL file• Save component settings in a Verilog fileRocketIO WizardThe RocketIO Wizard enables serial connectivity between devices, backplanes, and subsystems.The RocketIO Wizard allows you to:• Specify RocketIO type• Define Channel Bonding options• Specify General Transmitter Settings, including encoding, CRC, and clock• Specify General Receptor Settings, including encoding, CRC, and clock• Provide the ability to specify Synchronization• Specify Equalization, Signal integrity tip (resister, termination mode ...)• View and edit component attributes• View and edit component constraints• Automatically place one component in the XAW file• Save component settings to a VHDL file or Verilog fileChipSync WizardThe ChipSync Wizard applies to Virtex-4 devices and Virtex-5 devices only.The ChipSync Wizard:• Facilitates the implementation of high-speed source synchronous applications.• Configures a group of I/O blocks into an interface for use in memory, networking, or any other type of bus interface.• Creates Hardware Description Language (HDL) code with these features configured according to your input: – Width and IO standard of data, address, and clocks for the interface – Additional pins such as reference clocks and control pins – Adjustable input delay for data and clock pins – Clock buffers (BUFIO) for input clocks – ISERDES/OSERDES or IDDR/ODDR blocks to control the width of data, clock enables, and tristate signals to the fabric Synthesis and Simulation Design Guide22 www.xilinx.com UG626 (v 11.4) December 2, 2009
  23. 23. Chapter 3: FPGA Design FlowXtremeDSP Slice WizardThe XtremeDSP Slice Wizard applies to Virtex-4 devices and Virtex-5 devices only.The XtremeDSP Slice Wizard facilitates the implementation of the XtremeDSP Slice. For more information,see the:• data sheet for Virtex-4 devices and Virtex-5 devices• XtremeDSP for Virtex-4 FPGAs User Guide• Virtex-5 XtremeDSP User GuideCORE Generator SoftwareThe CORE Generator™ software delivers parameterized Intellectual Property (IP) optimized for Xilinx® FPGAdevices. It provides a catalog of ready-made functions ranging in complexity from FIFOs and memories to highlevel system functions. High level system functions can include:• Reed-Solomon Decoder and Encoder• FIR filters• FFTs for DSP applications• Standard bus interfaces (for example, the PCI™ and PCI-X™ bus interfaces)• Connectivity and networking interfaces (for example, the Ethernet, SPI-4.2, and PCI EXPRESS® microprocessor interfaces)For a typical core, the CORE Generator software produces the following files:• EDN and NGC Files• VHO Files• VEO Files• V and VHD Wrapper Files• ASY FilesEDN and NGC FilesThe Electronic Data Interchange Format (EDIF) Netlist (EDN) file and NGC files contain the information requiredto implement the module in a Xilinx FPGA device. Since NGC files are in binary format, ASCII NDF files mayalso be produced to communicate resource and timing information for NGC files to third party synthesis tools.The NDF file is read by the synthesis tool only and is not used for implementation.VHO FilesVHDL template (VHO) template files contain code that can be used as a model for instantiating a COREGenerator software module in a VHDL design. VHO files come with a VHDL (VHD) wrapper file.VEO FilesVerilog template (VEO) files contain code that can be used as a model for instantiating a CORE Generatorsoftware module in a Verilog design. VEO files come with a Verilog (V) wrapper file.V and VHD Wrapper FilesV (Verilog) and VHD (VHDL) wrapper files support functional simulation. These files contain simulation modelcustomization data that is passed to a parameterized simulation model for the core. In the case of Verilogdesigns, the V wrapper file also provides the port information required to integrate the core into a Verilogdesign for synthesis.Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 23
  24. 24. Chapter 3: FPGA Design FlowSome cores may generate actual source code or an additional top level Hardware Description Language (HDL)wrapper with clocking resource and Input Output Block (IOB) instances to enable you to tailor your clockingscheme to your own requirements. For more information, see the core-specific documentation.The V (Verilog) and VHD (VHDL) wrapper files mainly support simulation and are not synthesizable.ASCII Symbol (ASY) FilesASCII Symbol (ASY) symbol information files allow you to integrate the CORE Generator software modulesinto a schematic design for Mentor Graphics or ISE® Design Suite tools.Functional Simulation Early in the Design FlowUse functional or Register Transfer Level (RTL) simulation to verify syntax and functionality.When you simulate your design, Xilinx® recommends that you:• Perform Separate Simulations With larger hierarchical Hardware Description Language (HDL) designs, perform separate simulations on each module before testing your entire design. This makes it easier to debug your code.• Create a Test Bench Once each module functions as expected, create a test bench to verify that your entire design functions as planned. Use the same test bench again for the final timing simulation to confirm that your design functions as expected under worst-case delay conditions.You can use ModelSim simulators with ISE® Design Suite. The appropriate processes appear in ISE Design Suitewhen you choose ModelSim as your design simulator, provided you have installed any of the following:• ModelSim Xilinx Edition III• ModelSim SE or ModelSim PEYou can also use these simulators with third-party synthesis tools in ISE Design Suite.Synthesizing and OptimizingTo improve results and decrease run time, follow these recommendations:• Creating a Compile Run Script• Modifying Your Code to Successfully Synthesize Your Design• Reading CoresFor more information, see your synthesis tool documentation.Creating a Compile Run ScriptTCL scripting can make compiling your design easier and faster. With advanced scripting, you can:• Run a compile multiple times using different options• Write to different directories• Run other command line toolsRunning the TCL Script (Precision RTL Synthesis)To run the TCL script from Precision RTL Synthesis:1. Set up your project in Precision.2. Synthesize your project.3. Run the commands shown in Precision RTL Synthesis Commands to save and run the TCL script. Synthesis and Simulation Design Guide24 www.xilinx.com UG626 (v 11.4) December 2, 2009
  25. 25. Chapter 3: FPGA Design FlowPrecision RTL Synthesis Commands Function Command Save the TCL script File > Save Command File Run the TCL script File > Run Script Run the TCL script from a command line c:precision -shell -file project.tcl Complete synthesis add_input_file top.vhdl setup_design -manufacturer xilinx-family virtex—ii -part 2v40cs144 -speed 6 compile synthesizeRunning the TCL Script (Synplify)To run the TCL script from Synplify:Select File > Run TCL Script.ORType synplify -batch script_file.tcl at a UNIX or DOS command prompt. Enter the following TCL commandsin Synplify.Synplify Commands Function Command Start a new project project -new Set device options set_option -technology virtex set_option -part XCV50E set_option -package CS144 set_option -speed_grade -8 Add file options add_file -constraint watch.sdc add_file -vhdl -lib work macro1.vhd add_file -vhdl -lib work macro2.vhd add_file -vhdl -lib work top_levle.vhd Set compilation and mapping options set_option -default_enum_encoding onehot set_option -symbolic_fsm_compiler true set_option -resource_sharing true Set simulation options set_option -write_verilog false set_option -write_vhdl false Set automatic Place and Route (vendor) options set_option -write_apr_cnstrnt true set_option -part XCV50E set_option -package CS144 set_option -speed_grade -8Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 25
  26. 26. Chapter 3: FPGA Design Flow Function Command Set result format and file options project -result_format edif project -result_file top_level.edf project -run project -save “watch.prj” Exit exitRunning the TCL Script (XST)For information on options used with the Xilinx Synthesis Technology (XST) see the XST User Guide.Modifying Your Code to Successfully Synthesize Your DesignYou may need to modify your code to successfully synthesize your design. Certain design constructs that areeffective for simulation may not be as effective for synthesis. The synthesis syntax and code set may differ slightlyfrom the simulator syntax and code set.Reading CoresThe synthesis tools discussed in this section support incorporating the information in the CORE Generator™software NDF files when performing design timing and area analysis.Including the IP core NDF files in a design when analyzing a design results in better timing and resourceoptimizations for the surrounding logic. The NDF is used to estimate the delay through the logic elementsassociated with the IP core. The synthesis tools do not optimize the IP core itself, nor do they integrate the IPcore netlist into the synthesized design output netlist.Reading Cores (XST)Run Xilinx Synthesis Technology (XST) using the read_cores switch. When the switch is set to on (the default),XST reads in Electronic Data Interchange Format (EDIF) and NGC netlists. For more information, see:• XST User Guide• ISE® Design Suite helpReading Cores (Synplify Pro)When reading cores in Synplify Pro, Electronic Data Interchange Format (EDIF) is treated as another sourceformat, but when reading in EDIF, you must specify the top level VHDL or Verilog in your project.Reading Cores (Precision RTL Synthesis)Precision RTL Synthesis can add Electronic Data Interchange Format (EDIF) and NGC files to your project assource files. For more information, see the Precision RTL Synthesis help.Setting ConstraintsSetting constraints:• Allows you to control timing optimization• Uses synthesis tools and implementation processes more efficiently• Helps minimize runtime and achieve your design requirementsThe Precision RTL Synthesis and Synplify constraint editing tools allow you to apply constraints to yourHardware Description Language (HDL) design. Synthesis and Simulation Design Guide26 www.xilinx.com UG626 (v 11.4) December 2, 2009
  27. 27. Chapter 3: FPGA Design FlowFor more information, see your synthesis tool documentation.You can add the following constraints:• Clock frequency or cycle and offset• Input and Output timing• Signal Preservation• Module constraints• Buffering ports• Path timing• Global timingSpecifying Constraints in the User Constraints File (UCF)Constraints defined for synthesis can also be passed to implementation in a Netlist Constraints File (NCF) or theoutput Electronic Data Interchange Format (EDIF) file. However, Xilinx® recommends that you do not pass theseconstraints to implementation. Instead, specify your constraints separately in a User Constraints File (UCF). TheUCF gives you tight control over the overall specifications by giving you the ability to:• Access more types of constraints• Define precise timing paths• Prioritize signal constraintsFor recommendations on constraining synthesis and implementation, see Design Considerations. Forinformation on specific timing constraints, together with syntax examples, see the Constraints Guide.Setting Constraints in ISE Design SuiteYou can set constraints in ISE® Design Suite with:• Constraints Editor• PACE (CPLD devices only)• PlanAhead™For more information, see the ISE Design Suite Help.Evaluating Design Size and PerformanceYour design must:• Function at the specified speed• Fit in the targeted deviceAfter your design is compiled, use the reporting options of your synthesis tool to determine preliminary deviceutilization and performance. After your design is mapped by ISE® Design Suite, you can determine the actualdevice utilization.At this point, you should verify that:• Your chosen device is large enough to accommodate any future changes or additions• Your design performs as specifiedEstimating Device Utilization and PerformanceUse the area and timing reporting options of your synthesis tool to estimate device utilization and performance.After compiling, use the report area command to obtain a report of device resource utilization. Some synthesistools provide area reports automatically. For correct command syntax, see your synthesis tool documentation.Synthesis and Simulation Design GuideUG626 (v 11.4) December 2, 2009 www.xilinx.com 27

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