This is presentation of an Saber integration with Cadence IC layout to solve thermal issues related to self-radiation and heat radiation between devices. I have added footnotes so readers can understand the information on the slides.
What you are about to see here is the presentation of a new tool based on Saber for thermal and fully electro-thermal circuit simulations. The name of this tool is Thermsim and has been developed by a team from Bosch in Reutlingen, Germany. Historically speaking, there has been a lots of research in the area of electro-thermal circuit simulations, but the Bosch case is the first one to be fully integrated in a CAD design environment. Thermsim can be used to determine the temp. distribution on chip level and investigate electro-thermal coupling in integrated circuits. We are going to mention a few words about IC’s as electro-thermal systems and go over the thermal modeling and the flow of electro-thermal simulation.Then, we’ll take a look at the integration of Thermsim in the CAD environment. We will also look at an example of application using this tool. Finally, we’ll reach our conclusions about the potential use and advantages of thermsim.
Semiconductors dissipate power and 'adding bigger fans' is not always a desirable nor feasable solution to fix thermal problems. This will e.g. not solve the risks of thermal crosstalk.&quot; Change &quot;minimized&quot; into &quot;optimized&quot; in this line! Minimizing the thermal resistance is not (!) always a design goal. On chip level, minimizing Rth means larger area of driver stages and that increases cost. So the task is to _optimize_ the Rth, meaning we have to find the minimum device area that has still acceptable thermal resistance.
Many Integrated Circuits (in - for instance - the industrial, automotive, consumer electronics) should be considered as electro-thermal systems. The electrical part is formed by the circuit as defined by its circuit diagram. This circuit is physically defined by the layout in a suitable technology. The physical design defines the geometries and positions of the devices in the circuit which have strong impact on the temperature rise due to self heating in dissipating devices and due to thermal cross talk. The IC-package and the complete system also strongly determine the thermal behavior. The link between the electrical and thermal behavior is that the electrical device characteristics are temperature dependent. Therefore the thermal system behavior is coupled to the electrical system and unwanted coupling may lead to circuit failure.
The thermal system (consisting of Silicon die, package and its thermal environment) can be considered as a thermal multiport. The terminals of this multiport are: one connection for each device whose thermal behavior has to be simulated. A thermal heat flow („dissipated power“) will be flowing into these terminals as through variable and the model of the thermal system will deliver a temperature as the results of these heatflows (temperature is the accross variable). The temperature at each terminal gives the temperature of the corresponding device. Principally, this kind of thermal multiport model can be used for purely thermal simulation as well as for coupled electrothermal simulation . In the first case ideal thermal heat sources are connected to the thermal model. In the second case, an electro-thermal netlist is connected to the model.
As shown on the previous slide in an coupled electro thermal simulation an electro-thermal netlist is coupled with an model for the thermal system behavior. This slide shows this coupling. The left branch of the figure shows that a normal electrical netlist is converted into an electro-thermal netlist. This conversion step is carried out automatically, if an electrothermal simulation has to be done. The devices in the original electrical netlist that are to be simulated electrothermally will be labeled by an additional attribute. The netlist transformation/conversion will replace the labeled device instances by an electrothermal device model which have an additional thermal pin. All device instances with thermal pins will be connected to an instance of the thermal system model (the „thermal multi-port model“) of the previous slide. The MAST model for the thermal multi-port (right branch) is generated depending on thermal system properties, such as the device geometry, package details, thermal boundary conditions, material data. The simulation is done by Saber.
This slide shows an example of the physical structure which is described by a thermal model. Basically the thermal models consist of box-shaped regions. In this example the green box at the bottom is a alumium base plate . On top of this a ceramic substrate (blue region) has been glued ( glue layer is a very thin intermediate layer not well visible on the scale of the figure). On the ceramic a Si die (red) is glued (thin green intermediate glue layer). On the top surface of the die, the yellow shapes are the 9 different heat sources , present on this IC. The little green dots are so called monitor points where the temp. can be monitored for postprocessing or thermally dependent devices (that do not act as heatsources because their dissipation is negligible) may be affected by temp. Thermal boundary conditions can be defined at the surfaces of the regions. In this example a constant temperature boundary condition was used at the bottom of the base plate. This way an ideal heat sink at the bottom is modeled.
This slide discusses some implementation details of the thermal model. The model solves the differential equation for describing the heat flow by diffusion in the solid. This equation is solved matematically as a Finite Difference (FD) Model. Thus, it is a physical model! The FD Model is implemented as an equivalent thermal RC-network. Heat sources (dissipating devices) and monitor points (non-dissipating devices, but thermally dependent) are defined at the surface. There are several important modeling options: T-Dependent thermal material properties: e.g. Silicon‘s thermal conductivity is strongly temperature dependent. Thermal conductivity may get different values in different directions (anisotropy) (think about metal planes in a PCB) Thermal compact models can be added as boundary conditions. This way more efficient behavioral type of models can be used. As boudary conditions one can define not only constant temperatures but also heat transfer coefficient models to model - for instance - the heat removal by radiation and convection.
This slide summarizes the main features of Thermsim: Thermsim gives the option of both thermal and fully coupled electro-thermal simulation. These analysis may be in the steady state regime or transient regime. Even small signal AC is possible, although less relevant in most cases. The simulation is completely carried out with Saber , so the main benefit of thermsim is the integration of thermal simulation in a IC design environ. Providing an easy method for fast thermal and electro-thermal simulation and the capability of carrying out fully coupled electro-thermal circuit simulations.
Thermsim - the thermal simulation add-on package for Saber - has been fully integrated into the ASIC design flow. The main objectives of this integration is to make an electro-thermal simulation option available to circuit designers, who are usually not experts for thermal analysis. If designers have such a tool they can carry out thermal analysis themselves and therefore shorter design validation times can be accomplished. In order to make the tool usable for IC designers it has been fully integrated into the design flow. Where possible, it uses the tools from the conventional design flow. Functionality that could not be integrated into the standard tools has been implemented into a GUI. Furthermore, important and possibly error prone tasks, such as generation of electrothermal netlists, has been automated.
The main new functionality, in addition to the standard design flow is the generation of thermal models. A flexible model generator is written. The visualization (2 D Isotherm plots showing the temperature distribution in the chip) is integrated into the GUI too. Conversion of electrical into electro-thermal netlists is done in the background after a netlist is written by the schematic entry tool. A possiblilty to export thermal data (to external post - processing tools) or isotherm shapes (to display temperature distributions in the layout) is provided. The interface with the layout editor enables the extraction of device shapes from an available layout or the display of simulated isotherms in the layout. This interface is based on ASCII files, the extraction and isotherm display code has been inplemented as userware in the layout editor.
This slide shows the standard design flow. The circuit that is entered in the schematic entry tool outputs a netlist. This netlist is first used to simulate the electrical behavior of the electronic circuit, to verify that the electrical specs are met. If the circuit design has been completed, the netlist is used to draw the physical design in the layout editor. Finally this will result in a mask set and now the IC can be processed.
Slide 14:This slide shows the extension to the design flow in order to simulate electro-thermally and to have thermal constraint data visually available in the layout editor. Here again, an electronic system is entered into the schematic entry tool. Now, an electro-thermal netlist is generated, instead of an electrical netlist. This netlist contains an instance of a thermal multiport model that has to be generated for this particular simulation case. This model generation is one of the functions of the Thermsim GUI. In the GUI the positions of the devices that are to be simulated electro-thermally are drawn (to know which devices have to be drawn, a file containing the identifiers of the model instances is imported into the GUI). The thermal model behavior also depends on the type of package that is selected for this case. The package model templates are stored in a package model library. Once the thermal multiport model is generated the electrothermal simulation can be performed. After simulation the results can be viewed with Saber Scope. The temperature distribution on e.g. the chip surface can be visualized as 2D isotherm plots using the Thermsim GUI. Furthermore the interface between Thermsim and the layout editor are shown: the possibility to extract device geometries from the layout and the possibility to display simulated temperature distributions in the layout.
Slide 15:This slides shows a simple yet illustrative example of an electro thermal simulation case. The schematic contains a power DMOS transistor that has a pulsed gate voltage signal. The other part of the circuit consists of a differential bipolar transistor pair with shorted bases (delta Vbe=0) In case both transistors have equal temperatures, their collector currents are equal. The devices in this example all have an attribute &quot;thermal&quot; to label them as electro-thermally relevant devices and to include them in the electro-thermal analysis. The layout plot shows the irregularly shaped DMOS and the 2 smaller bipolar transistors at its side. Thermal coupled = will disipate heat and also be affected by heat., thermal dependent = will be affected by heat.
Slide 16: This graph shows the simulated temperature of the DMOS (upper curve). The self heating and cooling down due to the pulsed power dissipation is clearly visible. The lower curves show the temperatures of the bipolar transistors, which are heated up because of the thermal cross talk with the nearby DMOS. We see that the paired transistors have slightly different temperatures and that their temperature difference (and its sign) is varying as a function of time.
Slide 17:This slide shows the power dissipation in the DMOS (lower curve) and the temp. of this device (upper curve, which was also shown in the previous slide). Clearly visible is the dependence of the power dissipation on the temperature. This is due to the temperature dependence of the drain current of a MOS device (Ids decreases with increasing temperature). Such an effect can only be simulated accurately when taking the full electro thermal coupling into account! Without electro-thermal coupling the peak power levels of the DMOS would have been constant during time.
This graph shows the temperature difference between the two bipolar transistors (lower curve). Because there is a temperature difference between them, the collector currents are not equal (upper two curves). The differences between the collector currents are changing depending on the sign and the amount of the temperature difference. This again can only be simulated with an electro-thermal simulation tool such as Thermsim. Without taking electro-thermal coupling into account, the collector current would have been equal.
Slide 19: This slide illustrates the visualization of the temperature distribution on the chip surface. Isotherm plots can be viewed for different cross-sections of the die and at different time points of the simulation. It is possible to visualize the time evolution of the temperature by animated movies of isotherm plots. Then you have the nice thermal movie again.
Slide 20: The left graph shows the initial placement of the bipolar transistors in the layout. Because they are not positioned on an isotherm they experience a slightly different temperature, as was seen in the previous slides. Now, the availability of thermal information allows us to optimize the position of the bipolar to reduce there temperature difference (right graph).
Slide 21: After repositioning of the bipolar transistors the temperature differences are much reduced (lower curve) and hence the difference between the collector currents have become considerably smaller (upper curves).
Point 4: Here, it's good to emphasize that transient thermal simulation is especially important, because chip designers can usually estimate the static thermal resistance quite well, but tend to largely overestimate the *transient* temperature increases. Here thermal analysis can be a great help to reduce chip area and cost, by preventing over-dimensioning of power drivers. Regarding point 5 (chip, PCB, MEMS): the present implementation in the Bosch design environment (especially the GUI) is putting emphasis on silicon die and its package as the thermal model (as presented in this talk). However, in principle, the modeling approach and package use is not limited to this and may as well be used for MEMS and PCBs.
This slide shows the conversion of an electrical netlist into an electro-thermal netlist. The black writing is the original electrical netlist. The red characters have been added by the conversion routine
Electro Thermal IC Simulation With Saber
North American ASSURE Conference Portland, OR, May 15 - 17, 2002 Electro-thermal IC Simulation with Saber Presented by Michael Domnitei, MSE E
Outline <ul><li>Introduction </li></ul><ul><li>Integrated circuits as electro-thermal systems </li></ul><ul><li>Thermal and electro-thermal simulation </li></ul><ul><li>Thermal modeling with Thermsim </li></ul><ul><li>Simulation features of Thermsim </li></ul><ul><li>Integration in the CAD environment </li></ul><ul><li>Simulation example </li></ul><ul><li>Conclusions </li></ul>
Saber History <ul><li>The Saber simulator was originally developed and marketed in 1986 by Analogy, Inc., Beaverton, Oregon. </li></ul><ul><li>In February 2000, Avant! Corporation acquired Analogy. </li></ul><ul><li>In June 2002, Avant! merged with Synopsys, Inc. </li></ul><ul><li>Synopsys, Inc. is now the leader in high performance software and model libraries for top-down design and behavioral simulation of mixed-signal and mixed-technology systems. </li></ul><ul><li>Saber simulator suite of tools runs on Unix, Linux and Windows. </li></ul><ul><li>Saber also runs in computer grid environments for distributed iterative analysis (DIA) to speed up Monte Carlo analysis. </li></ul><ul><li>Mixed-signal and mixed-technology simulation at any combination of levels is native to Saber design tools. </li></ul>
What is Saber? <ul><li>Saber is a suite of tools used for analog, digital and mixed-signal and mixed-technology simulations. </li></ul><ul><li>The suite includes Saber Sketch™ for design capture, Saber Guide™ for control (simulations), and CosmosScope™ for post process analysis. </li></ul><ul><li>Saber Sketch lets you create and edit designs, SaberGuide allows interactive simulation control, and CosmosScope allows for graphical data analysis and viewing. </li></ul><ul><li>All of the applications are designed for graphically based interaction, although keyboard entry and a command language are available to those who prefer text-based commands and batch scripts runs for automation and customization (in production env.). </li></ul>
Why is Saber Unique? <ul><li>Saber is a single-kernel mixed-signal simulator that uses Synopsys’ patented Calaveras™ algorithm to synchronize analog and digital signals. </li></ul><ul><li>Saber is also the first simulator to be based upon a true Mixed-Signal Hardware Description Language - MAST . </li></ul><ul><li>SaberHDL uses VHDL-AMS and/or MAST models. </li></ul><ul><li>MAST is a powerful mathematics-based modeling language that allows models to be described at any level of abstraction - from high-level behavioral models, to detailed level models. This makes Saber suitable for both Top-down and Bottom-up design methodologies. </li></ul>
What Types of Analyses can Saber do? <ul><li>DC </li></ul><ul><li>DC Transfer Analysis </li></ul><ul><li>Time-domain (transient) </li></ul><ul><li>Frequency </li></ul><ul><ul><li>Small-signal AC </li></ul></ul><ul><ul><li>Noise </li></ul></ul><ul><ul><li>Distortion </li></ul></ul><ul><ul><li>Two-Port </li></ul></ul><ul><li>Linear Systems Analysis </li></ul><ul><ul><li>Pole-Zero </li></ul></ul><ul><ul><li>Linear Time Response </li></ul></ul><ul><ul><li>Frequency Response </li></ul></ul><ul><li>Stress </li></ul><ul><li>Statistical </li></ul><ul><ul><li>Monte Carlo </li></ul></ul><ul><ul><li>Statistical Summary </li></ul></ul><ul><ul><li>Histogram </li></ul></ul><ul><li>Parametric </li></ul><ul><ul><li>Sensitivity </li></ul></ul><ul><ul><li>Vary </li></ul></ul><ul><li>Fourier </li></ul><ul><ul><li>Fourier </li></ul></ul><ul><ul><li>FFT </li></ul></ul><ul><ul><li>IFFT </li></ul></ul><ul><li>Fault Detection </li></ul>
<ul><li>Thermal Analysis is the simulation and extraction of the relationship between the physical behavior and/or other properties of a system and its temperature. The essence of this analysis is that the system's response is recorded as a function of temperature and time. </li></ul><ul><li>By investigating the electro-thermal behavior designers can: </li></ul><ul><ul><li>Determine maximum temperatures in dissipating structures </li></ul></ul><ul><ul><li>Dimension dissipating structures </li></ul></ul><ul><ul><li>Better package selection </li></ul></ul><ul><ul><li>Improve reliability </li></ul></ul><ul><ul><li>Shorten time to market cycle by increasing design efficiency. </li></ul></ul>Benefits of the thermal and electro-thermal simulation during ASIC development
Observations <ul><li>Semiconductors dissipate power and in many cases it's not possible to use fans or it's not sufficient to simply add “ a bigger fan" as a downstream fix for thermal problems. </li></ul><ul><li>Heat flow must be planned and thermal resistances must be optimized. </li></ul><ul><li>Elevated temperatures are a major contributor to lower semiconductor reliability. </li></ul><ul><li>If heat isn't removed at a rate equal to or greater than its rate of generation, junction temperatures will rise and shorten component’s life time. </li></ul>
Integrated circuits as electro-thermal systems Electro-thermal system
Thermal and electro-thermal simulation Thermal multiport model Si die, package, environment Thermal multiport model T 1 T n T 2 P 1 P 2 P n Thermal simulation Thermal multiport model Electro- thermal netlist P 1 P 2 P n T 1 T n T 2 Electrothermal simulation
Thermal and electro-thermal simulation SABER Netlist conversion Electical netlist Electrothermal netlist Thermal Module Generator Thermal System Properties Thermal Multiport MAST Model Material Data Principles of a fully coupled electro-thermal simulation
Thermal modeling with Thermsim Example of a 3D thermal simulation structure
Thermal modeling with Thermsim <ul><li>Thermal multiport implementation: </li></ul><ul><li>Finite Difference Model of chip and package (partial); solving the heat diffusion equation: </li></ul><ul><li> </li></ul>Implemented as equivalent thermal RC-network Heat sources and monitor points on the chip surface Optional : temperature dependent material properties Optional : simple model for anisotropic thermal conductivity Optional : compact models for modelling package behavior Optional : Boundary Condition models (heat transfer coefficient for radiation and convection)
Simulation features of Thermsim Thermal simulation Fully coupled electro-thermal simulation Steady state analysis Transient analysis Simulation with Saber
Integration into the CAD environment <ul><li>Advantages of thermsim integration into a CAD flow: </li></ul><ul><ul><li>User friendly </li></ul></ul><ul><ul><li>Used by circuit and layout designers </li></ul></ul><ul><ul><li>Shorter cycle time for design validation </li></ul></ul><ul><li>Accomplished by: </li></ul><ul><ul><li>Using tools from standard design flow </li></ul></ul><ul><ul><li>Automation </li></ul></ul><ul><ul><li>Graphical user interface </li></ul></ul>
Integration in the CAD environment <ul><ul><li>Thermal Model generation </li></ul></ul><ul><ul><li>Visualization (2 D plots temperature distribution) </li></ul></ul><ul><ul><li>Netlist conversion (electrical electro-thermal) </li></ul></ul><ul><ul><li>Data export to post - processing tools & layout editor </li></ul></ul><ul><ul><li>Device geometry extraction from layout </li></ul></ul><ul><ul><li>Isotherm display in layout editor (ASCII files interface) </li></ul></ul>
CAD environment with no thermal analysis Chip Production Netlist Schematic entry tool Saber Layout editor Device model lib Spec Netlist
Thermsim integration into the CAD environment Electrothermal netlist Model instance list Device geometries Isotherm data Saber simulation results Thermal multiport model template Thermal package library Thermsim GUI Chip Production Schematic entry tool Saber Layout editor Device model lib Spec
Simulation example BJT’s collector currents and their temperature difference
Simulation results example Temperature distribution at chip surface
Simulation results example Temperature display in layout editor / layout change showing the BJT’s position with respect to isolines
Simulation example BJT collector currents and Delta T after layout change
Conclusions <ul><ul><li>Thermsim is fully operational </li></ul></ul><ul><ul><li>Electro-thermal integrated circuit simulation </li></ul></ul><ul><ul><li>Thermal and coupled electro-thermal simulation </li></ul></ul><ul><ul><li>DC and transient simulation </li></ul></ul><ul><ul><li>Chip level, PCB level, electro-thermal MEMS </li></ul></ul><ul><ul><li>Thermal behavior of packages included </li></ul></ul><ul><ul><li>Fully integrated into the CAD flow </li></ul></ul><ul><ul><li>Use by circuit designers </li></ul></ul><ul><ul><li>Applied in ASIC design in industry </li></ul></ul><ul><ul><li>Add-on option for Saber </li></ul></ul>