Some notes in Fabrication
● These notes have no specific pattern.
● Basic knowledge anout BJT and FET is
● Statutory warnings : Some comments are
Device fabrication in General
● We need a substrate to start.
● Semicondutors are used as base substrate for device
● Silicon (Si) is the most prominent substrate. Even though
devices on some other semiconductors (e.g. Gallium
Arsenide) are theoretically faster, they are not used as
mainline commercial product as Industry has invested too
much in Si. Success of Si is due to its native oxide (SiO2)
insulating properties and the ease with it can be grown.
● CZ method is used for make crystals.
● Doping, lithography, etching, implantation, chemical
depositions etc are done to fabricate a device.
● Its a very complex process, bussiness of details.
The discovery CZ method - Serrendipity at its best.
”While everybody in the semiconductor world knows the "Czochralski grown crystals",
(almost) nobody knows Jan Czochralski.”
Czocharalski was born in
Poland in 1885. He studied
chemistry. Accidently, in
1916, while working, he
dipped his pen in the molten-
tin pot instead of inkpot. When
he pulled it quickly, He saw
tha a thin thread of metal was
hanging out at the tip of the
Some ascribe the idea of
tunneling microscopy to him
Pulling out our crystal! The CZ
This method is mostly used in industries to grow
semiconductors, metals and gems.
Basically, it involves pulling out the crystal from the
moltl. A seed (a small crystal of <100> or <111>
orientation) is dipped into the molt and pulled out
slowly in upward direction. Meanwhile, the crystal
revolves at very high speed. For silicon, the pulling
rate are typically few (4-5) cm/min and revolving
speed are 1500 – 2500 rev/min. This values are
dependent on the size of the final product required.
Meanwhile, doping can be administered at the same
The product is called ingot as shown on the right hand
side. It is cut into wafers in appropriate crystal
direction <100> <111> etc.
Crystal defects are a prominent issue.
Cutting the ingot into wafers
The ingots need to be cut into wafers. A wafer is a
very thin flat structure as shown in figure. All the
process happens on this wafer. It should be thin
enough, not to waste the Si and thick enough to
survive all the processes.
Generally multi-wire saw is used. Coudn't find a pic.
Wafers are polished in a clean envioment called
cleanroom. Cleaner than class 100 is standard in
industry and >class 100 in academics.
The most impotant aspect of the wafer is the
mobility of electrons in wafer. That is what a design
engineer demands from a process engineer.
”There is a widespread misconception that solar
energy is clean energy. The process of making
solar cell (based on Si or GaAs) are very carbon
extensive, Nukes are cleaner, so is wind and
Lets start fabricating!
As we know, its a bussiness of details. Make your
process flow in advance and consults the
operatoes/experts before using them. Process
which are not compatible with others and might
At first, before BJT, as MOSFET was fabricated
but it did not work. Later, after 12 years, it was
revealed that the faliure is due to the presence of
Na ions. These ions are very mobile in Si and can
not be depleted from the channel. So the chennel
can not be turned off!. A drop of your sweat inside
the Si process room will cause the disaster.
Everything will have to be cleaned up else
nothing will work in this assemmbly line.
Now get to the other things!
A little bit of quantum..
While a string-theorist is happy that his system have no inconsistensies, a quantum
theorist is recieving funding from semiconductor industries. Because it can predict the
behaviours of small devices.
Tunnelling, Carbon Nano tubes, Single electron transistors, and most imporatantly
Band-Diagram and their consistensy with the observations are reasons of quantum
theory suceess and its embrace by the industries.
A tunnelling is an counterintutive phenomenon in which a particle pass through the solid
(loosely speaking). This probability is significat in small cmos devices. A challange in
furthur reducing the MOS size.
Carbon nano tubes, is of vast interests. A 2 dimensional (generally Graphite) solid is
wrapped up like a tube. Google it for more details.
Others... if interested, We may prepare another ppt.
CMOS-FET – The second most imporatant
semiconductor device. The first one if
ofcourse our loved one HB pencil.
We are going to talk about this device mainly. This is not so simple structure to start with.
After presentation, you may like to have a second look.
CMOS – Complemetry MOS-FET (Metal Oxide Semicondutor) Field Effect transistor.
Both p-type and n-type MOSFET are combined to give CMOS-FET.
Processes in Fabrication : Photolithography
(the most important process)
Lithography – (greek) : litho means 'stone',
grapho means 'to write'.
A photoresist (a monomer/polymer) is spun-off
on the wafer to make coating. Then a mask is
put on and the wafer is exposed to the light
(narrow band spectrum – uv in genreral). The
photoresist is get hard or soft at the exposed
area. This can be selectibly etched away. Once
the photoresist is removed, you can see the
substrate from the top. Now, you have got the
wafer on which certain areas are covered and
certain area are bare. You can do etching,
doping etc which will affect the only exposed
A >100 nm resolution can be achieved using
this technology. X-rays litho, can produce finer
images but hard to use. DNA lithography are of
In future, where d
Processes in Fabrication: Etching
Depends on the particular task. For the list of the
common processes you can read any standard book or
We'll look at few of them in presentation, very roughly!!
Transistor and Shockley
Three guys (Shockley included) invented this device and got the
nobel for that and all blah blah...
An atheist! Never attended a church. And a practical joker and
considered racist due to his views on white and blacks. Filed a
libel suit against a journalist who called him hilteraite and won it.
Got $1 in damage!
When he died, his children and friends received the news via print
media. He lived with his wife only.
His equations about MOS-FET are still in the same form, though
enhanced time by time so is the working theory of the MOS-FET.
The first patent for the field-effect transistor principle was filed in
Canada by Austrian-Hungarian physicist Julius Edgar Lilienfeld
on October 22, 1925, but Lilienfeld published no research articles His work ”electrons and
about his devices, and they were ignored by industry. Shockley holes in semiconductor” is
and his buddies never gave credit to him. semiconductor is a magnum
opus. Read any book by S.
Same story is with Karmarkar algorithm. Karmarker is a renowed M. Sze for furthur details
computer scientist, was associated with UCLA and Tata Institute and historic sketches.
of Fundamental Research, Mumbai. The controversy seems to be
removed from wikipedia.
Still nothing controversial than the Nobel prize for DNA discovery!
What so special about VLSI
Billion Dollar Industry, so glamorous.
Almost everywhere in electronics!
Progress in technology have been very extensive. If automobile industry had been on the
same track then a Ferrari would cost approx Rs 7.00 and will run almost 34000 Km in liter
So small. The minimum feature size in a typical chip is less than your nail grows in 2
seconds, (Obviously not entirely true, some chips have bigger geometries, and some nails
might grow rapidly).
The cost! Some mobile today cost less than some of the pizza's. Ha! What a development!
CMOS – 65 nm process
The 65 nanometer (65 nm) process is an
advanced lithographic node used in
volume CMOS semiconductor fabrication.
Printed linewidths (i.e., transistor gate
lengths) can reach as low as 25 nm on a
nominally 65 nm process, while the pitch
between two lines may be greater than
130 nm. See Table 40a in the 2006
industry roadmap . For comparison,
cellular ribosomes are about 20 nm end-
to-end. A crystal of bulk silicon has a
lattice constant of 0.543 nm, so such+
transistors are on the order of 100 atoms
across. By September 2007, Intel, AMD,
IBM, UMC, Chartered and TSMC were
producing 65 nm chips.
Gate thickness is approx 1.2 nm causing
Approx 11 layers of interconnects are
used in a typical processor exists today.
If it is industry then maintaining cost is the major problems. Academics have fabricated
CMOS with feature size as small as 5-6 nm, as well as other structures as FIN-FET,
multi-Gate structures etc. But that increases the cost multi-fold
Reliability : Millions of transistor works together. You can not afford loosing some of
them. Variation in feature size can vary as much as 200%. In this range, the device
must work satisfactorily.
Process Compatibility : If a new material is introduces with enhanced properties, it it
compatible other process; eg If platinum is used as interconnects instead of Cu (which
diffuse into semiconductor), can it be etch away as easily as Cu. Would that increases
cost? Would it pollute the system?
And a million other technical stuff!
In VLSI ”If you solve one problems it'll create 10 new one. Are the gains significant?”
Reseach in Fabrication
Put elements from the periodic table into the semicondutor
and hope for best!
If successful! Don't forget to produce hot air in media.
Social and environmental hazards
STATUTORY WARNING : comments are highly personal.
Most of the social scientist believes that too much mindless use of e-technology (build over
VLSI only) will not augur well for the society in long run. e.g. children playing video games,
watching TV's etc. (There are report across the globes that government are trying to
restrict the use, e.g. Recent time limit restriction on children watching TV in Australia which
have been ridiculed by children parents by the way!”
Silicon garbage. This is a main concern! e.g. World over people are changing mobiles very
rapidly and discarding them at alarming rate even though they are still working (But that is
why its a billion dollar industry.). The e-garbage from developed company generally
shipped to the developing countries like India, China, Pakistan etc. (We are still indexed
137 on Human Development Index though.) due to lax rules of these governments .
As in India and China, the trend is fast catching up! That is alarming. Anyway we can hide
behind the poor to say ”look our per capita emission is so less!”. While when it comes to
economic issues ”We are one of the largest economy in the world.” No body worries about
per capita income or human development index. Can we survive with this attitude?
A ”good but not-so-scholarly” account can be found in report . I could not found a better
You can use GNU Electric software to simulate the devices and you'll get some ideas
how to design a chip.
Ngspice and irsim, BITSIM can be used to simulate the circuits made by mosfets.
Following campuses have recourses in this fields.
1. IIT Bombay (Microelectroics and VLSI)
2. IISc Bangalore (Nanoelectonics Center or CEDT)
3. IIT Kgp, IIT Madras, IIT Delhi's VLSI programms.
4. Tata Institute of Fundamental Research (Material Science and Nano Dept)
5. Jawaharlal Nehru Center for Advanced Scientific Research, Bangalore (Material
6. DRDO labs (GAETAC in Hydrabad).
7. And of-course, you can look for US! In Europe, however, UK and Italy have nice bonds
with Indian students.
For theoretical studies:
1. You need a PC and enough food to survive and access to Internet
2. Institute of Mathematical Sciences (IMSc or MAT-Science), Chennai is a theoretical
institute in Solid State Physics (condensed matter physics).