Chapter4.1 2-mikroprocessor

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Chapter4.1 2-mikroprocessor

  1. 1. Data Movement Instructions A Course in Microprocessor Electrical Engineering Department University of Indonesia
  2. 2. MOV Revisited <ul><li>The MOV instruction introduces the ma-chine language instructions available with various addressing modes and instructions </li></ul><ul><ul><li>It is the native binary code that the micro-processor understands and uses as its instructions to control its operation </li></ul></ul><ul><li>See the format of the instructions in Fig. 4.1 </li></ul>
  3. 3. MOV Revisited (cont’d) <ul><li>The Opcode </li></ul><ul><ul><li>The opcode selects the operation (addition, subtraction, move, etc) performed by the microprocessor </li></ul></ul><ul><ul><li>The opcode is either one or two bytes long for most machine language instructions (Fig. 4.2 ) </li></ul></ul><ul><ul><ul><li>The first six bits of the first byte are the binary op-code </li></ul></ul></ul><ul><ul><ul><li>The remaining two bits indicate the direction (D) of the data flow and whether the data are byte or a word (W) </li></ul></ul></ul>
  4. 4. MOV Revisited (cont’d) <ul><ul><li>Refer to Fig. 4.3 for the binary bit pattern of the second op-code byte (reg-mod-r/m) </li></ul></ul><ul><li>MOD field </li></ul><ul><ul><li>The MOD field specifies the addressing mode (MOD) or the type of addressing for the selected instruction, and whether the displacement is present with the selected type ( Table 4.1 and 4.2 ) </li></ul></ul><ul><ul><li>Distinguish the MOV AL, [DI]; MOV AL, [DI+2] and MOV AL, [DI+1000H] </li></ul></ul>
  5. 5. MOV Revisited (cont’d) <ul><li>Register Assignments </li></ul><ul><ul><li>Table 3.3 lists the register assignments for the REG field and the R/M field (MOD=11) </li></ul></ul><ul><ul><li>Examine the 8BECH binary instruction ( Fig. 4.4 ) </li></ul></ul><ul><li>R/M Memory Addressing </li></ul><ul><ul><li>If the MOD field contains a 00, 01, or 10, the R/M field takes on a new meaning ( Table 4.4 ) </li></ul></ul><ul><ul><li>Figure 4.5 illustrates the machine language version of the 16-bit instruction MOV DL,DI or instruction (8A15H) </li></ul></ul>
  6. 6. MOV Revisited (cont’d) <ul><li>Special Addressing Mode </li></ul><ul><ul><li>It occurs whenever memory data are referenced by only the displacement mode of addressing for 16-bit instruction s ---> MOV [1000H],DL </li></ul></ul><ul><ul><li>Whenever an instruction has only a displace-ment, the MOD field is always a 00 and the R/M field is always a 110 (see Fig. 4.6 , Fig. 4.7 ) </li></ul></ul><ul><li>32-bit Addressing </li></ul><ul><ul><li>Table 4.5 . Shows the coding for R/M used to specify the 32-bit addressing modes </li></ul></ul>
  7. 7. MOV Revisited (cont’d) <ul><ul><li>The scaled-index byte (R/M=100) is mainly used when two registers are added to specify the memory address in an instruction ( Fig. 4.8 ) </li></ul></ul>
  8. 8. MOV Revisited (cont’d) <ul><li>An Immediate Instruction </li></ul><ul><ul><li>suppose the instruction MOV WORD PTR [BX +1000H], 1234H that moves 1234 into the word-sized memory location addressed by the sum of 1000H, BX, and DS x 10H </li></ul></ul><ul><ul><li>The six byte instruction uses two bytes for the op-code, W, MOD, and R/M fields, two other bytes are the data of 1234H, and the last two are the displacement of 1000H See Fig. 4.9 </li></ul></ul>
  9. 9. MOV Revisited (cont’d) <ul><li>Segment MOV Instructions </li></ul><ul><ul><li>If the contents of a segment register are moved by the MOV, PUSH, or POP instructions, a special set of register bits (REG field) selects the segment register (see Table. 4.6 ) </li></ul></ul><ul><ul><li>Figure 4.10 shows a MOV BX,CS instruction converted to binary </li></ul></ul><ul><ul><li>The op-code is different for the prior MOV </li></ul></ul><ul><ul><li>Segment registers can be moved between any 16-bit memory location or 16-bit memory location </li></ul></ul>
  10. 10. PUSH/POP <ul><li>These are important instructions that store and retrieve data from the LIFO stack memory </li></ul><ul><ul><ul><li>There are six forms of the PUSH and POP instructions: register, memory, immediate, segment register, flags, and all registers </li></ul></ul></ul><ul><li>PUSH </li></ul><ul><ul><li>It transfer two or four bytes of data to the stack </li></ul></ul><ul><ul><li>PUSHA instruction copies the contents of the internal register set, except the segment registers to the stack </li></ul></ul>
  11. 11. PUSH/POP (cont’d) <ul><ul><li>The PUSHA ( push all ) instruction copies the registers to the stack in the following order: AX, BX, CX, DX, BX, SP, BP, SI, and DI </li></ul></ul><ul><ul><li>The PUSHF ( push flags ) instruction copies the content of the flag register to the flack </li></ul></ul><ul><ul><li>Figure 4.11 shows the operation of the PUSH AX </li></ul></ul><ul><ul><ul><li>AX --> SS:[SP-1] = AH, SS:[SP-2] = AL, and after- ward SP = SP - 2 </li></ul></ul></ul><ul><ul><li>Figure 4.12 illustrates the result of the PUSHA instruction </li></ul></ul>
  12. 12. PUSH/POP (cont’d) <ul><ul><li>Table 4.7 lists the forms of the PUSH instruction </li></ul></ul><ul><li>POP </li></ul><ul><ul><li>It performs the inverse operation of PUSH, i.e., removes data from the stack and places it into the target 16-bit register, or a 16-bit memory location </li></ul></ul><ul><ul><li>POPF (pop flags) removes 16-bit number from the stack and places it into the flag register </li></ul></ul><ul><ul><li>The POPFD removes 32-bit number from the stack & places it into the extended flag register </li></ul></ul>
  13. 13. PUSH/POP (cont’d) <ul><ul><li>The POPA (pop all) removes 16-bit data from the stack and places it into the following registers in order: DI, SI, BP, SP, BX, DX, CX, and AX; this is a reverse order from the way they are placed on the stack by the PUSHA </li></ul></ul><ul><ul><li>Figure 4.13 shows how the POP BX removes data from stack into BX </li></ul></ul><ul><ul><li>Table 4.8 lists the op-codes used for the POP and all of its variations </li></ul></ul>
  14. 14. PUSH/POP (cont’d) <ul><li>Initializing the Stack </li></ul><ul><ul><li>If the stack area is initialized, load both the SS and SP registers; SS is normally designated with the bottom location of the stack segment </li></ul></ul><ul><ul><li>Fig. 4.14 shows how the beginning of stack segment is formed and used in PUSH CX </li></ul></ul><ul><ul><li>A stack segment is set up as illustrated in example 4.1 and example 4.2 </li></ul></ul>
  15. 15. (a) 16-bit instruction mode Opcode 1-2 bytes Immediate 0-1 bytes MOD-REG-R/M 0-1 bytes Displacement 0-1 bytes (b) 32-bit instruction mode (80386 through Pentium 4 only) Opcode 1-2 bytes Immediate 0-1 bytes MOD-REG-R/M 0-1 bytes Displacement 0-1 bytes Scaled-index 0-1 bytes Register size 0-1 bytes Address size 0-1 bytes Figure 4-1 The formats of the 8086-Pentium 4 instructors. (a) The 16-bit form and (b) the 32-bit form.
  16. 16. Figure 4-2 Byte 1 of many machine language instructions, showing the position of the D- and W-bits. Figure 4-3 Byte 2 of many machine language instructions, showing the position of the MOD, REG and R/M fields. W D Opcode MOD REG R/M
  17. 17. Opcode = MOV D = Transfer to register (REG) W = Word MOD = R/M is a register REG = BP R/M = SP FIGURE 4-4 The 8BEC instruction placed into bytes 1 and 2 formats from Figures 4-2 and 4-3. This instruction is a MOV BP,SP 0 0 1 1 0 1 1 1 1 1 0 1 0 0 0 1 R/M REG MOD W D Opcode Opcode = MOV D = Transfer to register (REG) W = Byte MOD = No displacement REG = DL R/M = DS:[DI] FIGURE 4-5 A MOV DL,[DI] instruction converted to its machine language form. 1 0 1 0 1 0 0 0 0 1 0 1 0 0 0 1 R/M REG MOD W D Opcode
  18. 26. R/M is a register 11 16-bit signed displacement 10 8-bit sign-extended displacement 01 No displacement 00 Function MOD TABLE 4-1 MOD field for the 16-bit instruction mode R/M is a register 11 32-bit signed displacement 10 8-bit sign-extended displacement 01 No displacement 00 Function MOD TABLE 4-2 MOD field for the 32-bit instruction mode (80386-Pentium 4 only)
  19. 27. EDI DI BH 111 ESI SI DH 110 EBP BP CH 101 ESP SP AH 100 EBX BX BL 011 EDX DX DL 010 EAX CX CL 001 EAX AX AL 000 W = 1 ( Doubleword) W = 1 (Word) W = 0 (Byte) Code TABLE 4-3 REG and R/M (when MOD = 11) assignments

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