Chapter2.3 4-mikroprocessor


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Chapter2.3 4-mikroprocessor

  1. 1. The Microprocessor and Its Architecture A Course in Microprocessor Electrical Engineering Department University of Indonesia
  2. 2. Protected Mode Memory Addressing <ul><li>Protected mode memory addressing (80286 and above) allows access to data and programs located above the first 1MB of memory as well as within the first 1MB of memory </li></ul><ul><li>The segment register contains a selector instead of segment addresses </li></ul><ul><ul><li>a selector selects a descriptor from descriptor table </li></ul></ul><ul><ul><li>The descriptor describes the memory segment’s location, length, and access rights ( Fig.2.6 ) </li></ul></ul>
  3. 3. Protected Mode Memory Addressing (cont’d) <ul><ul><li>The selector selects one of 8,192 descriptors from one of two tables of descriptors </li></ul></ul><ul><ul><li>There are two descriptor tables: one contains global descriptors and other contains local descriptors </li></ul></ul><ul><ul><li>The global descriptors contain segment definitions that apply to all programs, while the local des-criptors are usually unique to an applications </li></ul></ul><ul><ul><li>Each descriptor table contains 8,192 descriptors (i.e. a total 16,384 descriptors are available to an application at any time) --> eq. 16,834 memory segment </li></ul></ul>
  4. 4. Protected Mode Memory Addressing (cont’d) <ul><ul><li>The base address portion of the descriptor indicates the starting location of the memory segment </li></ul></ul><ul><ul><li>The segment limit contains the last offset address found in a segment </li></ul></ul><ul><ul><li>The G bit ( Granularity ; for 80386 through Pen-tium Pro) specifies a segment limit of from 1B to 1MB in length if G = 0, and any multiple of 4KB if G = 1 </li></ul></ul><ul><ul><li>The AV bit is used by some operating systems to indicate that the segment is available (AV=1) or not available (AV=0) </li></ul></ul>
  5. 5. Protected Mode Memory Addressing (cont’d) <ul><ul><li>The D bits indicates whether the instructions to access register and memory data is 16-bit instructions (D=0) or 32-bit instructions (D=1) </li></ul></ul><ul><ul><li>The access rights bytes ( Fig.2.7 ) controls access to the protected mode memory segment </li></ul></ul><ul><li>Descriptors are chosen from table by the segment register </li></ul><ul><ul><li>Fig . 2.8 shows how the segment register functions in the protected mode system </li></ul></ul><ul><ul><li>Fig.2.9 shows how the segment register, containing a selector, chooses a descriptor from the global descriptor table </li></ul></ul>
  6. 6. Program Invisible Registers <ul><li>The program invisible are not directly addressed by software (i.e. invisible) </li></ul><ul><li>Figures 2.10 Illustrates the program-invisible registers </li></ul><ul><ul><li>These registers control the microprocessor when operated in the protected mode </li></ul></ul><ul><ul><li>The program-invisible portion of these registers is often called cache memory; do not confuse with the normal level 1 or level 2 caches found in the microprocessor </li></ul></ul>
  7. 7. Program Invisible Registers <ul><li>The GDTR (global descriptor table register) and IDTR (interrupt descriptor table register) contain the base address of the descriptor table and its limit (i.e. 16-bits) </li></ul><ul><ul><li>the location of the local descriptor table is selected from the global descriptor table </li></ul></ul><ul><ul><li>One of the global descriptor is set up to address the local descriptor table </li></ul></ul>
  8. 8. Memory Paging <ul><li>The memory paging mechanism located within the 80386 and above allows any physical memory location to be assign to any linear address </li></ul><ul><ul><li>The linear address is defined as the address generated by a program, and with the memory paging unit, the linear address is invisibly translated into any physical address </li></ul></ul><ul><ul><ul><li>This allows an application written to function at a specific address to be relocated through the paging mechanism </li></ul></ul></ul>
  9. 9. Memory Paging (cont’d) <ul><ul><ul><li>It also allows memory to be placed into areas where no memory exists </li></ul></ul></ul><ul><li>The paging unit is controlled by the contents of the microprocessor’s control registers (CR0 - CR3 or CR4, Figure 2.11 ) </li></ul><ul><li>The linear address is broken into three sections that are used to access the page directory entry, page table entry, and page offset address (Figure. 2.12 ) </li></ul>
  10. 10. Memory Paging (cont’d) <ul><li>See Figure. 2.13 </li></ul><ul><ul><li>The page directory contains 1,024 doubleword addresses that locate up to 1,024 page tables </li></ul></ul><ul><ul><li>The page directory and each page table are 4K bytes in length </li></ul></ul><ul><ul><li>See Figure. 2.14 as well </li></ul></ul>