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Ratan Devpura Analog/Mixed signal IC engineer Professional Profile

Contents
Summary
Work Experience
Masters Research Work
Professional Skills
Project Details
Future Goals
Appendix

Summary
Passionate towards Analog Mixed signal circuit design. Worked on different amplifier topologies for various mixed signal systems along with ADC, DAC and VGA (Variable Gain Amplifier) designs.
Good at Design/Simulation tools like Cadence, Synopsis, Mentor Graphics etc. and excellent documentation skills.
Eager to learn more in Analog circuit design, Self learner and really passionate towards analog circuits.
Worked at Qualcomm & Motorola as an engineering intern & worked at Analog-Rails as Analog IC intern & Analog circuit design volunteer at Signal Processing Group.
Built different amplifier designs being used in various modern mixed signal systems in AMI & TSMC processes.
B.E. from C.K.Pithawala college of engineering & Technology, India in Electronics & Communications.
M.S. from San Diego State University in Electrical & Computer Engineering with GPA of 3.55/4.0

Work Experience
2) Analog IC intern (08/2009-10/2009)@ Analog-Rails
Migration of analog circuits from 65nm technology to 45nm & 32nm process technology, running simulation using GnuCap circuit simulator and comparing results with different circuit simulators like Hspice and Spectre.
Worked on simulation environment of the tool to verify various single stage & two stage amplifiers topologies.
Verifying the tool performance by creating analog/digital circuits and their layouts and identifying DRC/LVS errors after doing automated placement & routing of the layout.
Analog IC volunteer (10/2009-11/2009)@ SPG consulting
Design & simulation of DC to DC boost regulator circuit for high voltage IC design applications.

Work Experience
3) Engineering Intern(06/2009-07/2009)@ Motorola
Employed in Motorola Mobile devices Android platform software integration group to perform QA testing to check functionality of the products.
Delivered excellent test cases to perform sanity testing more effectively for phones on latest software builds provided by the developers, that saved lot of testing time for the rest of the group.
4) Engineering Intern(06/2007-05/2008)@ Qualcomm
Worked in ASIC System group to perform USB electrical compliance testing & to debug any USB related issues.
Performed complete testing of different USB features including Host, peripheral & HID etc & provided logs for any issues.
Prepared test cases to test functionality of USB core inside Qualcomm’s latest ASIC chips.

Masters Research Work
Master’s Thesis (02/2008-05/2009)
Built a Low Power High Gain amplifier using 0.18um CMOS technology for LDO (Low drop out voltage regulator) applications.
Developed a novel frequency compensation technique to achieve small compensation capacitors to reduce chip area & low power while driving large capacitive loads.
Used indirect feedback compensation scheme and lower power supply to achieve low power design.
2) Research Project Work(05/2008-06/2008)
Built layout of digitally controlled CMOS Variable Gain Amplifier (VGA) designed in AMI 0.5u including 5-bit current steering D/A (digital to analog) converter for wireless receiver systems.

Professional Skills Coursework: CMOS mixed signal circuit design, VLSI circuit design, Analog/Digital integrated circuits, Digital logic design, ASIC Design, Digital signal processing (DSP), RF/Microwave devices, and Power electronics. IC design/simulation tools : Xilinx ISE, Modelsim, Cadence, Mentor Graphics IC-station, HSpice, Mentor Graphics Design Architect, Calibre DRC/LVS, LT-Spice. Programming Languages: VHDL, MATLAB, basic Verilog and C. Industry Lab Instruments: Oscilloscopes, Function generators, Logic analyzers, Power supply, DVM. Transistor level circuit design (CMOS/Bipolar), Schematic design, Layout design, Semiconductor physics, PCB circuits. Experience with Microsoft office suite, Operating systems (Windows, Linux). Good communication skills, Project leadership, Team player with self-start-up and quick learning abilities.

Project Details
Analog IC design:

CMOS Op-amp Design : Built a 3-stage amplifier using 0.5um CMOS technology to achieve Gain of 100dB & GBW of 40MHz & simulated using Hspice.
CMOS Voltage Reference Design : Designed Beta Multiplier voltage reference circuit to provide constant output voltage which is stable with any power supply & temperature variations.
Differential Amplifier : Built a CMOS differential amplifier in 0.35um technology which is used in high performance analog & mixed signal circuits and performed DRC/LVS using Calibre tool.
Cascode Common Source Amplifier Design : Designed using 0.5um CMOS technology and built layout of CS amplifier & biasing circuitry to provide 20uA of current and simulated using Hspice.

Project Details
Digital IC design:

Layout Design: Designed a layout of D Flip Flop & Tri-state Inverter using Mentor Graphics IC Station.
CMOS ring oscillator: Built a ring oscillator using series of CMOS inverters to achieve 10MHz of operating frequency.
Transistor Level Design of CMOS circuits : Designed 3-input, 6-input & 9-input NAND logic gates using Mentor Graphics Design Architect schematic capture tool.
2-D DCT Design : Designed 2-Dimensional DCT using VHDL and synthesized using Leonardo spectrum tool.
Digital UART Design : Built UART using VHDL and synthesized whole design using Xilinx ISE tools.

Future Goals
Want to become an outstanding circuit design engineer with my passion & hard work in analog/mixed signal area.
I would like to built innovative analog circuits which can save cost of the overall chip along with power & area.
Want to become a key member of the IC design organization.
Self learner and ready to learn more in circuit design.

Appendix

LDO (Low Drop-Out Voltage Regulator)
The pass transistor M1 in LDO acts as a load to the ampliﬁer as it is very big transistor provides more than 100pF of capacitive load. By simulation, we can extract the exact value of this load capacitor.
Resistors R 1 & R 2 provides negative feedback around the amplifier to track the value of the output voltage.
Low power LDO design requires very efficient amplifier design to maintain low drop out voltage for LDO.
There are lots of multistage amplifier topologies available which are suitable for LDO design but all multistage amplifiers requires accurate frequency compensation scheme to maintain stability in low power environment.

Challenges for Amplifier design for LDO:
To design an amplifier that can drive larger capacitive load and achieve larger Gain-Bandwidth product while maintaining low power requirements.
Achieve lower compensation capacitors to reduce overall chip area while maintaining stability of the amplifier.
Need of an adequate frequency compensation topology to maintain stability to drive larger capacitive load.
Achieve higher gain & higher Gain-Bandwidth product while operating at power supply (VDD) less then 1.8V.
Required excellent biasing circuit which is stable enough with any variations in power supply & temperature that can accurately bias different stages in multistage amplifier design.

Amplifier design approach for LDO:
Created low impedance nodes to connect compensation capacitors which in turn increases speed of the amplifier. Also, required compensation capacitors are smaller that saves lot of chip area.
Used indirect feedback compensation to maintain stability of the amplifier.
Excellent biasing of the transistors to get high gain & bandwidth required for LDO applications.
Overall power consumption is reduced as less current is required to drive larger capacitive load.
Designed biasing circuit that provides bias voltages to bias different levels in overall amplifier design and also stable with any variations in power supply & temperature.

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