Physical designing of low power operational amplifier


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Physical designing of low power operational amplifier

  1. 1. DEVENDRA SINGH KUSHWAHA M.Tech(1102808503) VLSI Design Contact: +918373915779 Department of Electronics and Communication (Area of Specialization-VLSI Design) 2011-2013 Under the Guidance of XXXXXXXXXXXXXXXXXXXXX Topic- A Novel approach to Designing of Low Power Operational Amplifier 1
  2. 2. Contents Chapter 1 Introduction…………………………………………………………………………...3 Chapter 2 Literature survey and recent development…………………………………………… 8 Chapter 3 Inferences drawn out of literature survey…………………………………………..15 Chapter 4 Problem formulation………………………………………………………………...17 Chapter 5 Scope of work………………………………………………………………………...20 Chapter 6 Methodology………………………………………………………………………….22 Chapter 7 Expected Outcome…………………………………………………………………...24 Chapter 8 Tools and Software Requirement…………………………………………………… 26 2
  3. 3. Chapter 1 INTRODUCTION 3
  4. 4. The operational amplifier is one of the most important and useful circuit in analog electronic circuitry and Signal Processing. Designing and building an Operational Amplifier consist various levels of complexities and hence make it a versatile device ranging from a dc bias generation to high speed amplifications to filtering. One of the major applications of Operational Amplifiers seems in Analog Signal Processing where wide varieties of circuits are made up, Operational Amplifier as their integral part. Not only in Laboratories, Academia or institutions, it is very useful components in industries as well. Operational Amplifier also plays a very important role in Digitals Circuit Design. Operational amplifiers had their origins in analog computers, where they were used to do mathematical operations in many linear, non-linear and frequency-dependent circuits. Characteristics of a circuit using an Operational Amplifier are set by external components with little dependence on temperature changes or manufacturing variations in the Operational Amplifier itself, which makes Operational Amplifiers popular building blocks for circuit design. The circuit symbol for an Operational Amplifier is shown below, Fig 1: Operational Amplifier structure Where: • V+: non-inverting input • V−: inverting input • Vout: output • VS+: positive power supply • VS−: negative power supply The power supply pins (VS+ and VS−) can be labeled in different ways. Often these pins are left out of the diagram for clarity, and the power configuration is described or assumed from the circuit. The amplifier's differential inputs consist of a V+ input and a V− input, and ideally the Operational Amplifier amplifies only the difference in voltage between the two, which is called the differential input voltage. The output voltage of the Operational Amplifier is given by the equation: 4
  5. 5. Where V+ is the voltage at the non-inverting terminal, V− is the voltage at the inverting terminal and AOL is the open-loop gain of the amplifier (the term "open-loop" refers to the absence of a feedback loop from the output to the input). Here in this project we are aiming to design and fabricate a novel low power Operational Amplifier. To this approach we should first have known what the basic building blocks are for a better Operational Amplifier. If we consider an ideal Operational Amplifier, an output can be received using the characteristics like differential input, infinite voltage gain, infinite CMRR, infinite input resistance and zero output resistance. Most of the ideal things are not ideally generated, but a proper approach towards the idealness can make us achieve the properties that are close to them. In a real Operational Amplifier however these characters cannot be generated but their performance has to be sufficiently good for the circuit behavior to closely approximate the characters of an ideal Operational Amplifier in most applications. A basic Operational Amplifier consists of 4 main blocks namely a. Current Mirror b. Differential Amplifier c. A Level shifter, differential to single ended gain stage d. An Output buffer Fig: 2 Circuit diagram of Operational Amplifier showing all stages 5
  6. 6. Fig: 3 An NMOS Current mirror Fig:4 A Differential Amplifier Fig: 5 Common Source stage with Current Source load 6
  7. 7. BLOCK DIAGRAM Input (Vdd) Vout Vss Fig 6: Block diagram of an Operational Amplifier IDEALIZED CHARACTERISTICS (a) Differential Voltage Gain: Infinite (b) Common mode gain: Zero (c) Input impedance (Zin): Infinite (d) Output impedance, (Zout): Zero (e) CMRR: Infinity (f) Bandwidth, (BW): Infinite (g) Offset Voltage, (Vo): Zero 7 Biasing Amplifier Differential Amplifier Amplifier Stage
  9. 9. W. T. Holman et al. (1) presented a low noise CMOS based Operational Amplifier in a 120nm Digital Technology. The chip area is 3.0mm2 and a corner frequency less than 10Hz is found.  Gain Bandwidth Product 3.1MHz  PSRR(dc) -118dB  CMRR(dc) -73.4dB  Output Slew Rate 2.0V/us  Quiescent Current 0.75mA  Input Supply ±2.5V  As a part of wideband random noise generation.  This Operational Amplifier uses a standard differential input stage and a diode based bootstrapped biased network.  The 1/f equivalent input noise can be reduced without affecting white noise by uniformly scaling the width and length of the device after setting the value of the Trans conductance to obtain the desired white noise level. Ming-Dou Ker et al. [3] presented a CMOS Operational Amplifier in a 130nm low-voltage process. In this  The effect of MOSFET gate-oxide reliability on Operational Amplifier is investigated with the two stage and folded-cascode structures in a 130nm low voltage CMOS process  The test operation conditions include unity-gain buffer (closed loop) and comparator (open loop) configuration.  The gate-oxide reliability in the Operational Amplifier can be improved by the stacked configuration under small input and output application. The following problems were faced of thin gate-oxide of the MOS transistor:  Gate-oxide breakdown  Tunneling current  Hot carrier effect All these problems effect the degrade the lifetime of the MOS transistor 9
  10. 10. The author used H-Spice for the simulation of the circuit and obtained 64.7dB and 47.8˚open- loop gain and phase margin respectively. Loikkanen. M et al.[4] presented a high current CMOS Operational Amplifier. They told:  Low voltage CMOS Operational Amplifier, which is capable of driving heavy resistance and capacitive loads.  Robust and power efficient compensation is achieved by using Miller Compensation together with a high bandwidth stage.  Unity gain bandwidth (UGB) 5.7MHz  Phase margin 61˚  Load 1nF||1KΩ  Current 2.4mA@ 1.5V power supply  At 3V supply the amplifier is able to source or sink more than 100mA into 1nF||10Ω load  The author uses compensation method  The Simple Miller Compensation (SNC) is a usable technique for driving heavy resistive loads, due to its simplicity and robustness to withstand small signal trans conductance variations of the output stage.  In this paper, theory and measurement results of a class AB power amplifier, which has rail-to-rail input and output and uses miller compensation with the high bandwidth stage to stabilize the amplifier. A two pole, high speed Operational Amplifier modeling methods and techniques are presented by Makris C.A et al. [5]. They told that:  Settling time is very important parameter since it determines the maximum speed of the operation of the circuit.  In this paper miller approximation is used to show a quite significant error when applied to high frequency Operational Amplifier designs.  High frequency Operational Amplifier architectures are generally of two types (a) Single stage externally compensated (b) Two stage internally compensated 10
  11. 11. Schlogl, F. et al.[6] described a 120nm Operational Amplifier with high gain down to ±0.3V power supply.  3-stage Operational Amplifier  120nm digital CMOS technology  86dB supply voltage range @ ±0.3V to ±0.6V  Positive feedback is primarily implemented for a good common-mode rejection  Transit frequency 46MHz  Phase margin 66˚ @±0.6V power supply  Load 10pF  Current consumption less than 1.8mA in the temperature range -30˚C to +150˚C  Two pseudo cascodes in the input differential stage for gain enhancement  The fully differential circuits have many advantages compared to single ended circuits  This is so because if the signal voltage is doubled, the suppression of ground disturbances is very good the input voltage range for Operational Amplifiers is about in the middle of the power supply (no need of rail-to-rail input). Because of the higher signal voltage the SNR can be increased.  A wide input voltage is achieved due to the bulk regulation of the input transistor  The pseudo cascodes have the advantage that they do not need biasing circuits compared to normal cascodes  The positive feedback loads in the first and the second result in a good common mode rejection Kaulberg et al. [7] designs a CMOS current mode Operational Amplifier. It is known as a fully differential input differential output current Operational Amplifier. Also it has  Three 2nd generation current conveyors  It can be configured to provide either a constant Gain-Bandwidth Product (GBP) in a fully balanced current mode feedback amplifier or a constant bandwidth (BW) in a trans impedance feedback amplifier.  The GBP is obtained as 3MHz 11
  12. 12.  Offset current 0.8µA  Due to flexible interconnections of three 2nd generation current conveyor, a versatile current mode building block has been achieved. Schlogl et al. [8] demonstrated a low voltage Operational Amplifier in 120nm digital CMOS technology  The power supply and the Early voltages are lowered as per the need (below about 10V for gate lengths below 400nm) as well as the gain of the transistor stage is low.  In shrinking the threshold voltage of the transistors decreases less than supply voltage  The replica gain enhancement technique is affected due to mismatching of components  Another problem is that the multiple signal path causes a slow settling component in the step response  The fully differential circuits have many advantages compared to single-ended circuits. The signal voltage is doubled, the ground disturbance suppression is very good and the input voltage for Operational Amplifier is near the middle of the power supply(no need of rail-to-rail) input  The gain was improved by about 20dB compared to simulations of a standard non- cascoded two stage Operational Amplifier  A wide input range is achieved due to the bulk control of the input transistors Schlogl et al. [9] designed a high-gain, high speed Operational Amplifier in digital 120nm CMOS in fully differential 6-stage 3-signal path Operational Amplifier.  A differential gain of 120dB @1.2V power supply is obtained  The use of six common mode controller(CMC) leads to a good common mode behavior and an AB output stage.  Unity gain frequency 866MHz  Phase margin 36˚  Slew rate 890V/µs  Stage 1: This input stage is a differential amplifier with P-channel transistor P1 and P2 and N-Channel load 12
  13. 13.  Stage 2: This stage is realized with cascaded P-Channel input transistors and self- cascaded N-Channel loads  Stage 3: In this third stage two signals paths are added  Stage 4: The amplifier stage 4 controls the N-channel output transistors  Stage 5: It controls the P-Channel output transistors  Stage 6: This last stage is used to correct the phase at high frequency and is compensated by the load capacitances Sarbishaei et al. [10] described a high gain, high speed low-power class AB Operational Amplifier  A positive scheme is used to increase the voltage gain  Good utilization of current driven bulk technique the output voltage swing is improved  Two cross coupled flipped voltage follower blocks, class AB behavior is achieved to make the Operational Amplifier compatible for high speed low power applications  Class AB technique was employed to get a higher slew rate with low power  To overcome the swing limitations, CDB technique was applied to load transistors to decrease threshold voltage  This Operational Amplifier can be used as the first stage Operational Amplifier with rail- to-rail output Hiyuan Li ey al. [11] says that Low noise Operational Amplifier can be designed with current driven bulk in 250nm CMOS technology. Also  Effect of substrate biasing on equivalent input referred voltage noise En, and presents a low noise Operational Amplifier design with current driving bulk technology  250nm CMOS technology is used  It improves noise performance  En=2.91µV/Hz1/2 @1Hz, En=3.38nV/Hz1/2 @1MHz, GBP 280.5MHz, DC gain 76dB, total Harmonic Distortion(THD) 76dB @50KHz  Power consumption 2.35mW @2.5V power supply  Current driven bulk is used as a technology for minimum noise 13
  14. 14.  This Operational Amplifier has better noise performance, better linearity and Bandwidth by smaller area and similar power dissipation  GBP is adequate for high frequency analog applications Vincence et al. [12], in the study of Low Voltage Class AB Operational Amplifier tells that  Minimum selector circuit is used to control the Class AB operation of the output stage  The Operational Amplifier basic characteristics are analyzed and simulated using SMASH 4.0 simulator with ACM model of the MOSFET  1.5V input, quiescent current 4.5µA for a unity gain frequency of 1MHz  Design integrated an AMS 0.8µm technology Raikos et al. [15] says in the paper that  A low voltage Differential Amplifier is conducted by bulk-driven PMOS transistor  A local positive feedback is utilized that boosts the input trans conductance and improve the noise performance  A 5th order Chebyshevs active RC filter with 500KHz cutoff frequency and 1dB ripple is built based on the proposed amplifier  1V power supply voltage  350nm CMOS technology Pletersek et al. [16] discusses Low supply voltage, Low noise fully differential programmable gain amplifiers. He tells that  Low voltage, fully differential, low noise, programmable gain microphone amplifier is designed  Differential band gap reference and low voltage programmable gain power amplifier is used  120nm technology  The measured equivalent input referred RMS noise voltage of 5.1nV/Hz1/2 in the voice frequency band was achieved  The output buffer is capable of delivering 30mW power into 50Ω load at 3V power supply 14
  15. 15. J.Mahattanakul et al. [17] in their paper designed a two stage CMOS Operational Amplifier with flexible noise power balancing scheme  2-stage CMOS Operational Amplifier design procedure  Balance between noise performance and power consumption 15
  16. 16. Chapter 3 INFERENCES DRAWN OUT OF LITERATURE SURVEY The literature survey tells that 16
  17. 17.  Most of the work has been done on 120nm CMOS technology  Noise can be reduced by adjusting the trans conductance of the CMOS device  Low noise Operational Amplifier can be designed with current driven bulk CMOS technology  The three main stages of Operational Amplifier are differential, level shifter and amplifier stages  Cascoded structures are better that cascades for enhanced gain. Hence designing becomes better using Cascode connection  Miller Compensation Method  Class AB amplifier is used for better slew rate  Rail to rail Operation  Positive feedback is primarily implemented for a good common-mode rejection  The fully differential circuits have many advantages over single ended circuits  A wide input voltage range is achieved due to the bulk regulation of the input transistor Chapter 4 17
  18. 18. PROBLEM FORMULATION 1. Finite Gain: Operational amplifiers are mainly used to amplify the input signal and the higher its open loop gain the better as in many applications they are used with a feedback loop, so ideal Operational Amplifiers are characterized by a gain of infinity. For practical Operational Amplifiers, the voltage gain is finite. Typical values for low frequencies and small signals are A = 102 – 105, corresponding to 40-100 dB gain. 18
  19. 19. 2. Input impedance, (Zin): The Input impedance of an Operational Amplifier for an ideal device has to be infinite to prevent any current flowing from the source supply into the amplifiers input circuitry. 3. Bandwidth, (BW): An ideal operational amplifier has an infinite Frequency Response and can thus be used to amplify signals of any frequency. However as evident from the frequency response curve below the gain of the amplifier is not constant irrespective of frequency and after the first pole it begins to drop with a slope of 20dB/decade thus the higher the frequency of the first pole the higher the range of frequencies over which it operates desirably. 4. Finite Linear Range: The linear relation V0 = A (Va-Vb) between the input and output voltages are valid only for a limited range of V0. Normally the maximum value of V0 for linear operation is somewhat smaller than the positive dc supply voltage, the minimum value of V0 is somewhat positive with respect to the negative voltage. 5. Offset Voltage: The amplifiers output is supposed to be completely independent of common potentials applied to both inputs and is supposed to be zero when the voltage difference between the inverting and non-inverting inputs is zero. For an ideal Operational Amplifier, if Va = Vb (which is easily obtained by short circuiting the input terminals) then V0 = 0. In real devices, this is not exactly true, and a voltage V0, off ≠ 0 will occur at the output for shorted inputs. Since v0,off is usually directly proportional to the gain, the effect can be more conveniently described in terms of the input offset voltage Vin, off, defined as the differential input voltage needed to restore v0=0 in the real devices. For MOS Operational Amplifiers Vin, off is about 5-15mV. 6. Common Mode Rejection Ratio (CMRR): The common-mode input voltage is defined by Vin,c = (Va + Vb)/2 as contrasted with the differential-mode input voltage Vin,d = Va - Vb. The differential gain AD and also the common-mode gain AC which can be measured as shown in figure, where Ac = V0/ Vin,c. The CMRR is now defined as AD/Ac or in logarithmic value CMRR = 20 log10(AD / Ac) in dB. Typical CMRR values for MOS amplifiers are in the 60-80 dB range. The CMRR measures how much the Operational Amplifier can suppress common-mode signals at its inputs. These normally represent undesirable noise, and hence a large CMRR is an important requirement. 7. Frequency Response: Because of stray capacitances, finite carrier motilities and so-on, the gain A decreases at high frequencies. It is usual to describe this effect in terms of the unity gain bandwidth, that is the frequency f0 at which |A (f0)| = 1. For MOS Operational Amplifiers, f0 is usually in the range of 1-10MHz. It can be measured with the Operational Amplifier connected in a voltage-follower configuration. 19
  20. 20. 8. Slew Rate: For a large input step voltage, some transistors in the Operational Amplifier may be driven out of their saturation regions or completely cut-off. As a result the output will follow the input at a slower finite rate. The maximum rate of change dV0/dt is called slew rate. It is not directly related to the frequency response. For typical MOS Operational Amplifiers slew-rates of 1~20 V/μs can be obtained. 9. Nonzero Output Resistance: For a real MOS Operational Amplifier, the open loop output impedance is nonzero. It is usually resistive, and is of the order of 0.1-5KΩ for Operational Amplifiers with an output buffer, it can be much higher (~1MΩ) for Operational Amplifiers with un-buffered output. This affects the speed with which the Operational Amplifier can charge a capacitor connected to its output and hence the highest signal frequency. 10. Noise: The MOS transistor generates noise, which can be described in terms of an equivalent current source in parallel with the channel of the device. The noisy transistors in an Operational Amplifier give rise to a noise voltage von at the output of the Operational Amplifier, this can be again modeled by an equivalent voltage source Vn = Von/A at the Operational Amplifier input. Unfortunately, the magnitude of this noise is relatively high, especially in the low frequency band where the flicker noise of the input devices is high; it is about 10 times the noise occurring in an Operational Amplifier fabricated in bipolar technology. In a wideband (say in the 10Hz to 1MHz range), the equivalent input noise source is usually of the order of 10~50μV RMS, in contrast to the 3~5μv achievable for low- noise bipolar Operational Amplifiers. Fig:7 Despcription of 3rd stage i.e. Level Shifter Chapter 5 SCOPE OF WORK 20
  21. 21. PARAMETERS SPECIFICATION OBJECTIVE(EXPECTED AFTER SIMULATION AND LAYOUT) Gain 10 V/V || 20 dB 10.3 V/V || 20.0 dB 3-dB bandwidth 20 kHz. 220KHz Unity Gain Bandwidth(UGB) NA 3Mhz CMRR >50 dB >80dB 21
  22. 22. PSRR NA 90dB/60dB Slew Rate 10 v/μs 12 v/μs Power Dissipation 1mW 0.45mW Input Common Mode Range(ICMR) 1.2v-2.4v -1v-2.2v Output Offset Voltage NA -500mV Chapter 6 METHODOLOGY 22
  23. 23. The proposed work will be carried out following the sequential steps mentioned below: 23 Start Literature Survey and Review Judge and justify the possible Problems
  24. 24. Fig 8: Flowchart Showing the Methodology to Carry Out the Proposed Work Chapter 7 EXPECTED OUTCOME 24 Scope of Work Requirements and available facilities Introduction to Software Generating Netlist and placing components Simulation and Waveform Analysis Layout Performance comparison between the results of modified swarm -optimization and available methods Conclusion End
  25. 25. The following outcomes are expected by the investigator from the proposed work: 1. This new modified algorithm shall be able to find the best load management in different situations. 2. The proposed system shall provide very effective and efficient residential load management. 3. The proposed algorithm shall make it possible to automatically adjust the consumption of residential load in order to satisfy power constraints 25
  26. 26. 4. Introduction of additional objective functions shall minimize the cost, since the rates of electricity are different for peak hours and off peak hours. Fig:9 BODE diagram of an Operational Amplifier showing pole, margin,gain @relevent frequency Fig:10 Frequency response of an ideal Operational Amplifier Chapter 8 TOOL AND SOFTWARE REQUIREMENT 26
  27. 27. The software tool needed for this proposed low-power Operational Amplifier is TANNER EDA Tool version 13.0 or TANNER EDA Tool 15.1 TANNER Tanner IC Work Flow Tanner Tools are fully-integrated solutions consisting of tools for schematic entry, circuit simulation, waveform probing, full-custom layout editing, placement and routing, netlist extraction, LVS and design rule checking (DRC) verification. 27
  28. 28. Introduction This document gives a rough overview of how to design & simulate things with Tanner Tools. There are four basic steps: 1. Design the schematic in S-EDIT. 2. Simulate the schematic to make sure it behaves as you expect using T-SPICE. 3. Layout the schematic in L-EDIT. 28
  29. 29. 4. Perform an LVS (Layout VS Schematic) to make sure your layout is functionally the same as the schematic you designed in S-EDIT. 5. Simulate the layout using T-SPICE with a high-level spice model, making sure L-EDIT generates the parasitic capacitances so they are included in the simulation. REFERENCES [1] W. T. Holman, J. A. Connelly, J. O. Perez, “A Low Noise Operational Amplifier in a 1.2μM Digital Technology”, IEEE Journal 2007 [2] Maryam Borhani, Farhad Razaghian, “Low Power Operational Amplifier Based on Weak Inversion with Miller-Cascoded Frequency Compensation”, IEEE Journal 2009. [3] Ming-Dou Ker; Jung-Sheng Chen, “Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process”, IEEE Journal 2008. 29
  30. 30. [4] Loikkanen. M, Kostamovaara. J, “High current CMOS operational amplifier”, IEEE Conference 2005. [5] Makris C.A, Toumazou. C, “Two pole, high speed operational amplifier modelling, mehods and techniques”, IEEE Conference 1989. [6] Schlogl, F.; Dietrich, H.; Zimmermann, H. “120nm CMOS operational amplifier with high gain down to ±0.3V supply”, IEEE Conference 2003, Pages: 121 – 124. [7] Kaulberg, T. “A CMOS current-mode operational amplifier”, IEEE Journal 1993, Pages: 849 – 852. [8] Schlogl, F.; Zimmermann, H. “Low-voltage operational amplifier in 0.12 μm digital CMOS technology” IET Journal 2004, Pages: 395 – 398. [9] Schlogl, F.; Dietrich, H.; Zimmermann, H. “High-gain high- speed operational amplifier in digital 120nm CMOS”, IEEE Conference 2004, Pages: 316 – 319. [10] Sarbishaei, H.; Kahookar Toosi, T.; Zhian Tabasy, E.; Lotfi, R. “A high-gain high- speed low-power class AB operational amplifier”, IEEE Conference 2005, Pages: 271- 274 Vol. 1 [11] hiyuan Li; Jianguo Ma; Mingyan Yu; Yizheng Ye “Low noise operational amplifier design with current driving bulk in 0.25μm CMOS technology”, IEEE Conference 2005 , Pages: 630 - 634 [12] Vincence, V.C.; Galup-Montoro, C.; Schneider, M.C., “Low-voltage class AB operational amplifier”, IEEE Conference 2001, Page(s): 207 – 211. [13] Rajput, S.S.; Jamuar, S.S., “Low voltage, low power, high performance current mirror for portable analogue and mixed mode applications”, IET Journal 2001, Page(s): 273 – 278. [14] Rajput, S.S.; Jamuar, S.S., “Ultra low voltage current mirror op amp and its applications”, IEEE Conference 2002, Page(s): 145 - 148 vol.1. [15] Raikos, G.; Vlassis, S., “Low-voltage differential amplifier”, IEEE Conference 2009, Page(s): 136 – 139. [16] Pletersek, A.; Strle, D.; Trontelj, J., “Low supply voltage, low noise fully differential programmable gain amplifiers”, IEEE Conference 1995 , Page(s): 105 – 112. [17] J.Mahattanakul and J.Chutichatuporn, “Design Procedure for Two-Stage Cmos Operational Amplifier Flexible noise power balancing scheme” IEEE trans.Circuits syst.I fundam.Theory App vol 52 no.8 pp 1508-1514 Aug 2005. [18] J.Mahattanakul ,“Design Procedure for Two-Stage Cmos Opamp employing current buffer” IEEE trans. Circuits syst.II Fundam. Theory App vol. 52 no.8 pp 1508-1514 Nov 2005. 30
  31. 31. [19] Behzad Razavi, Design of CMOS Analog Integrated Ckts, Mc-Graw Hill College, 2001. [20] S.S. Rajput and S.S. Jamuar, "Low voltage, low power high performance current mirror for portable analogue and mixed mode applications." In Proc. IEE Circuits Devices and Systems, 2001, vol. 148, no. 5 pp. 273-278. [21] C. Zhang, A. Srivastava, P. K. Ajmera, "A 0.8 V CMOS amplifier design", Analog Integrated Circuits and Signal Processing, 47, pp 315-321, 2006, Springer Science. [22] Analog MOS Integrated Circuits for Signal Processing by Roubik Greogorian Gabor C. Temes. [23] s_Ccts_HTML/sld034.htm [24] P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press: New York, 2002 [25] [26] [27] [28] [29] for opamp amplifier circuits [30] AMPLIFIER/OPERATIONAL AMPLIFIER-1.html for calculating gain [31] [32] [33] [34] [35] [36] Video Lecture 31