HDTV Chip From NXP (PNX85500)
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  • 1. PNX85500 Single Chip LCD TV Systemwith integrated 120Hz HD Frame Rate ConverterColin Osborne / Ralf KargePNX85500 Single Chip LCD TV SystemHot Chips 2009August, 25, 2009
  • 2. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge2Presentation OutlineIntroductionSystem Integration– More TV System on a Chip– PNX85500 TV SolutionDesign Challenges– Architecture– Memory Bandwidth and Latency– Verification and EmulationHigh-lighted FeaturesConclusions
  • 3. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge3Introducing the TV550 SystemTV550 System comprises the world’s first Digital TV SoC in C045: PNX85500• Channel demodulators, networking (USB, HDMI, Ethernet, SD card reader),120 Hz, H.264 HD decoding, advanced Picture Quality Algorithms, etc.Extremely high level of functional integration• Full application (networking, H.264 HD decoding, advanced gfx, FRC, …) allon 2x16-bit DDR2 footprint!Smallest memory requirement for the total system• Avoid expensive EMI protection with built-in spread-spectrum on both LVDSas well as DDR interfacesDrives industry’s lowest cost-of-ownership/bill-of-material• Minimize upfront development costs and time-to-market for global rollout• One development, one PCB line, one test set upEnables development for global chassis roll out thanks tolow system costs
  • 4. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge4IntroductionSystem Integration– More TV System on a Chip– PNX85500 TV SolutionDesign Challenges– Architecture– Memory Bandwidth and Latency– Verification and EmulationHigh-lighted FeaturesConclusions
  • 5. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge5TV550 System IntegrationCVBS,Y/C,RGB L/RL/RL,RYCbCrNXPPNX8543MIPS32@300 MHzPixel OSD, TV Control,HDMI,USB,PC-AVIDDR2256MBFLASH128 MBPNX8543LVDS-2CVBSSPDIFL,RAudio AmplifierDVB-C ChannelDecoderTDA10024TunerTDA18272SPDIFRGB, HVL/RPCMCIANXPTFA981032 bitDDR2-666TSLow-IFAnalog IF IPTDA8296CVBS/SIFEthernetMACDVB-T ChannelDecoderTDA10048Silicon TunerSwitchTDA9996CI+HDMISwitchHD 1080p100/120Hz50/60HzNXPPNX5120Frame RateConversionPNX8550032 bitDDR2-666DDR2128MB
  • 6. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge6TV550 System IntegrationCVBS,Y/C,RGB L/RL/RL,RYCbCrNXPPNX8543MIPS32@300 MHzPixel OSD, TV Control,HDMI,USB,PC-AVIDDR2256MBFLASH128 MBPNX8543LVDS-2CVBSSPDIFL,RAudio AmplifierDVB-C ChannelDecoderTDA10024TunerTDA18272SPDIFPCMCIANXPTFA981032 bitDDR2-666TSLow-IFAnalog IF IPTDA8296CVBS/SIFEthernetMACDVB-T ChannelDecoderTDA10048Silicon TunerSwitchTDA9996CI+HDMISwitchHD 1080p100/120Hz50/60HzNXPPNX5120Frame RateConversionRGB, HVL/RPNX8550032 bitDDR2-666DDR2128MBNXPPNX85500
  • 7. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge7TV550 – FRC 120Hz FULL HDDVB-T, CI+, PAL/SECAM, IPTV550HDMI DIGITALAUDIO OUTDIGITALAUDIO INHDMITFA9810HDMIHDMIPNX8550xDDR2128 MBFLASH64 MBCI+EthernetPHYTDA9996switchUSBDDR2128 MBTDA18272Si Tuner
  • 8. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge8TV550 – FRC 120Hz FULL HDDMB-T/ATSC/ISDB-T, PAL/SECAM/NTSC, IPTV550HDMI DIGITALAUDIO OUTDIGITALAUDIO INHDMITFA9810HDMIHDMIPNX8550xDDR2128 MBFLASH64 MBEthernetPHYTDA9996switchUSBTDA18272Si TunerDDR2128 MBChannelDemodOptional China CI+
  • 9. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge9LVDS_TXMIPS24KCAIMIPS24K–ControlNetworkVideo Scaler (1)VideoCompositionPipe (1)RWRWRWSPDIFGPIOAVDSP–ControlNetworkHDMI_RXAudio DecodingAudio ProcessorUSBRWAV-DSPRWI2CVideoInput ProcessorVideoCompositionPipe (2)RDENCInterruptsRWI2SRBRIDGER2D DrawingRWDigital VideoDecoderRWRWRWWTransportStream InputPC_AVIRWFrameRateConverterRWWETHERNETRWVideo Scaler (2)RWFLASH_CTRLWChannelDecodeMCU_DDR(32bit)RWMPEG DemuxRWPC_AVIRWAAR DMA ReadW DMA WriteKeyScatter/GatherDMARWPC_AVIMEM_ARBRTCGFX_SCALERRWSPIRWSD CardRWR/WControl NetworkRWPNX85500 Block DiagramUARTJTAGRESETCLOCKSInterruptsSYS_CTRLDMANetworkDMA NetworkGeneric Control and InterconnectDigital Broadcast / Transport StreamAudio ProcessingVideo Processing and Graphics
  • 10. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge10IntroductionSystem Integration– More TV System on a Chip– PNX85500 TV SolutionDesign Challenges– Architecture– Memory Bandwidth and Latency– Verification and EmulationHigh-lighted FeaturesConclusions
  • 11. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge11Organizational ComplexityWorld-wide multi-siteproject– UK, Netherlands,Germany, France,India, Israel, USANumber of IPs– Approx 100 IP blocks(85% NXP-internal)Compute infra metrics– 15 TBytes of diskspace– 3 TBytes of RAM forSoC IntegrationCaenSouthampton HamburgChicagoSan Jose Eindhoven Haifa Bangalore
  • 12. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge12Integrating many different functionsAnalogueStandardsDecoderMIPS24KDigital AudioDecoderAudioPost-ProcessingAudioPresentationConnectivityInterfacesAudio andVideoCaptureMPEGDemux &DescramblerMPEG/H.264Video DecoderFlexibleVideo DecoderGraphicsRenderingPicture QualityProcessingVideoPresentationAuto PictureControlFrame RateConversionFunction ExamplesEstablished HW functions Analogue audio/video decodingHigh performance HW functions Video scaling & compositionControl processing Generic operating systemFlexible DSP Audio & video feature processingHigh performance DSP Motion Accurate Picture Processing
  • 13. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge13Challenging Bandwidth and Latency NeedsAudioProcessorDigital VideoDecoderMIPS24KCriticalEmbeddedControl CPUCritical TolerantFRC Co-processorTolerantFRCProcessorCritical TolerantAVDSPProcessorCriticalMemory Subsystem with Arbitration and BufferingVideo Comp.Pipe(s)TolerantVideoScaler(s)TolorantCost pressure only allows 2 x 16 DDR2-1066• Limiting gross bandwidth to 4.2 Gbytes/sec• Originally the TV550 system was expected to need 64-bit DDR interfaceRequiring high-bandwidth and low-latency• Processors for flexible processing: requiring low-latency to minimise cache miss penalty• Hardware traffic mostly predictable: requiring high-bandwidthInnovative solutions• Processors supported by specific arbitration settings in infrastructure• Hardware units and VLIW pre-fetch memory accesses• Local caches/buffers• Video streaming between IP functions
  • 14. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge14Assuring fast Silicon Bring-UpExtensive suite of verification methodsVarious abstraction levels in simulation of– IP functionality and connectivity– SoC infrastructure performanceEmulation of representative Software andHardware– 300 million gates of IC emulation capacity– System tuning and performance sign-off– 300 - 400 k frames of HD video beforetape outAdvance system software developmentEmulationAll main use-cases had been brought up on the emulator before silicon– Software was ready when silicon arrived– Arbitration and tuning settings had been verified=> Very rapid silicon bring-up
  • 15. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge15PNX85500 Silicon• TSMCs 45nm Low Power (LP)process technology• 27 mm Flip Chip BGA Package• Power Consumption < 7 Watt• No active cooling required
  • 16. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge16IntroductionSystem Integration– More TV System on a Chip– PNX85500 TV SolutionDesign Challenges– Architecture– Memory Bandwidth and Latency– Verification and EmulationHigh-lighted FeaturesConclusions
  • 17. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge17Complex SoC made up by Complex IPsExample: Video ScalerVCARMPEG ArtefactReductionSTDIDe-interlacerTNRTemporal NoiseReductionPCORProjection datafor film detectorAHSCHorizontal scaler
  • 18. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge18Complex SoC made up by Complex IPsExample: Video Composition PipePCTIPeaking-basedColor TransientImprovementVSHRVideo SharpeningSKCRSkin-tone ControlBSKYBlue-SkyEnhancementDI2D2-DimensionalBacklight Dimming
  • 19. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge19Motion Accurate Picture ProcessingFilm Judder Cancellation + Motion Blur Reduction24 Hz filmA BOriginal Movie24 frames per secondA A A BBTypical TVat 50 or 60 framesper second(with ‘movie judder’)APNX85500 outputat 120 framesper second; aftermovie judder removal2 3 4 5 B 7 8 9 10High quality smooth, natural-looking motion- analysed and created- in real-time, for HD video content- at 120 frames per second
  • 20. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge20Improved Picture Quality at Reduced Power2D Local Dimming ProcessingVideoinputVideo outputBacklight output Perceived outputVideo on backlight+ =PNX85500HistogramFRC ProcessorImage AnalysisBacklightcalculationReduce LCD TV’sbacklight power byabout 50%Significant increaseof contrast and blacklevelHistogrammeasurement andpixel processingdone in HW-IPFlexible processingof VLIW processorfor image analysisand backlightcalculationVideoGain
  • 21. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge21IntroductionSystem Integration– More TV System on a Chip– PNX85500 TV SolutionDesign Challenges– Architecture– Memory Bandwidth and Latency– Verification and EmulationHigh-lighted FeaturesConclusions
  • 22. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge22ConclusionsPNX85500: the world’s first DTV SoC in 45nm•Very high level of integration•Award-winning 120 Hz processing in front-end TV SoC•Enabling global chassis, single platformPerformance critical•Iterative analysis and optimisation through design cycle•Solving challenging demands on memory latencyVerification challenge•Very high level of integration creates challenges in interdependency and complexity•Extensive use of prototyping using emulation and FPGAFirst silicon arrived in Q1 2009•Successful customer demonstrations within 2 weeks of first silicon!What’s next?•Higher integration levels, lower system cost•Improved picture quality, increased frame rates and resolution•New video features
  • 23. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge23Questions
  • 24. 25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge24