IP Re Engineering – Challenges<br />
Agenda <br />IP Re Engineering  Challenges <br /><ul><li>Introduction
IP Re Use and Challenges
IP Re-Engineering Activities
Internal IP Vs Third Party IP
 Challenges and solutions
Internal Vs External Team
Capabilities of the external Team
Solutions from MindTree
CSoC Initiative
Conclusion</li></ul>Slide 2<br />
Introduction<br />IP Reuse <br />Time to Market<br />Cost<br />Optimized area, performance<br />IP Re-engineering<br />Eng...
IP Re Engineering Activities<br />Design <br />Feature Enhancements, Functionality modifications (fixing bugs)<br />Optimi...
Internal IP Vs Third Party IP<br /> Internal IP <br />IP that were developed and used within the organization <br />Standa...
Challenges and Solutions<br />
Execution<br /><ul><li>Planning and Forecasting
 Resource optimization (activities Vs resources)
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Mind tree ip soc

  1. 1. IP Re Engineering – Challenges<br />
  2. 2. Agenda <br />IP Re Engineering Challenges <br /><ul><li>Introduction
  3. 3. IP Re Use and Challenges
  4. 4. IP Re-Engineering Activities
  5. 5. Internal IP Vs Third Party IP
  6. 6. Challenges and solutions
  7. 7. Challenges
  8. 8. Internal Vs External Team
  9. 9. Capabilities of the external Team
  10. 10. Solutions from MindTree
  11. 11. IP ReD
  12. 12. CSoC Initiative
  13. 13. Conclusion</li></ul>Slide 2<br />
  14. 14. Introduction<br />IP Reuse <br />Time to Market<br />Cost<br />Optimized area, performance<br />IP Re-engineering<br />Engineering activities that are aimed to customize, port and make the existing IP available for new designs<br />Challenges:<br /> Porting to different Technology libraries (Power, Performance)<br /> Verification/Validation/Proto type (Quality)<br /> Quality Documentation<br /> Support for different teams (internal/external)<br />Enablers: Standard processes/methodology/Framework for <br />Reusable IP Development<br />IP Qualification and Verification<br />Chip Integration<br />IP Distribution and support<br />Slide 3<br />
  15. 15. IP Re Engineering Activities<br />Design <br />Feature Enhancements, Functionality modifications (fixing bugs)<br />Optimizing the design for Power, Performance, Area<br />Interface/Bus modifications<br />Making the design more DFT/implementation friendly<br />Verification/Validation<br />Verification Environment optimization for coverage improvement <br />Modifications to reflect and test the DUT enhancements<br />Methodology migration (e – SV; Legacy – HVL)<br />Integration/Physical Implementation/Maintenance<br />Validating the IP for Integration <br />Flow validation <br />Release / Version Control<br />User Documentation/update<br />Slide 4<br />
  16. 16. Internal IP Vs Third Party IP<br /> Internal IP <br />IP that were developed and used within the organization <br />Standard based, proprietary<br />More visibility to the different designs in which the IP was used<br />Access to the design team and details of the design, environment <br /> Legacy environment, custom tool flow and proprietary design components<br />Integration issues due to insufficient documentation and validation<br />Support from the IP owner to re-engineer the IP is possible<br /> Third Party IP<br />Independent vendor developed IP <br />Mostly Standard based <br />Lesser visibility to the different design scenarios in which the IP was used <br />Better user documentation possible as the IP is to be shared with different users<br />Good qualification process to be in place before the reuse <br />Support for customization from the vendor is key for success<br />Slide 5<br />
  17. 17. Challenges and Solutions<br />
  18. 18. Execution<br /><ul><li>Planning and Forecasting
  19. 19. Resource optimization (activities Vs resources)
  20. 20. Legacy and third party IP
  21. 21. Team Preparation (training)</li></ul>Reuse Targets<br /><ul><li> Optimization (power, area, Performance)
  22. 22. Multiple SoC Platforms
  23. 23. Bus interfaces, Processors</li></ul>Quality/Process<br /><ul><li>Process adherence
  24. 24. Different flow qualification (CAD)
  25. 25. Metrics collection and analysis
  26. 26. Benchmarking & Certification
  27. 27. Training</li></ul>Challenges<br />Engagement Models<br /><ul><li>Flexi Pool
  28. 28. Support for global teams and local centers
  29. 29. Issue based support
  30. 30. Support for external customers</li></ul>Scalability & Maintenance<br /><ul><li> Peak requirements handling
  31. 31. Support for existing IP
  32. 32. Multiple Target Platforms (Proc, Bus, OS..)</li></ul>Key Challenges<br />
  33. 33. Internal Team Vs Design Services Team..<br />More often the re-engineering or customization tasks are centered around <br />Technology Migration, Bus interface modification<br /> Targeting different SoC platforms, resolving integration issues<br /> Improving the quality of the IP (Performance, Power, Area)<br /> Optimization of the design and verification environment (coverage improvement for functionality, manufacturing etc.,)<br />Engaging a third party team for effective use of the resources and focused IP re engineering will result in<br />Cost savings due to the effective utilization of the team that manages the IP enhancements and improvements<br />Enables the customer team to focus on the domain specific activities<br />Becomes a central team that supports different design teams <br />Serves as a common knowledge platform where the project experiences are fed back and made available for different teams<br />Slide 8<br />
  34. 34. Capabilities of the Partner<br />Slide 9<br />
  35. 35. IP ReD<br />
  36. 36. Slide 11<br />Design/Verification IP Re-Engineering Life Cycle<br />
  37. 37. Slide 12<br />Design/Verification IP Re-Engineering - Auditing<br />Existing DIP<br />Database<br />                                                                                                                                                                                                                                                <br /> Data Base Analysis                                                                      Env Analysis<br />Methodology <br />Compliance <br />Tool-Specific<br />Tool Used<br />Design <br />Documentation<br />RTL Checks (Lint)<br />Limitation on <br />Existing Synthesis <br />Logs & QoR Report<br />Integration Compatibility at System level<br />Verification Reports<br />Feasibility analysis<br />Re-engineering requirements<br />No<br />Customer<br />Approval<br />Customer’s estimation on time and resources<br />Approved by customer<br />Yes<br />SOW / WBS<br />Execution Phase starts<br /><ul><li>Auditing:
  38. 38. IP Re-eng schedule and schedule confidence
  39. 39. IP Re-eng effort estimate – leading to WBS
  40. 40. Clearly defined Customers & MindTree role in re-eng activity, Receivable and Deliverable
  41. 41. Quality of deliverables
  42. 42. Entry:
  43. 43. Customer Requirements
  44. 44. Latest Data Base of the IP
  45. 45. Standard Specification (Optional)
  46. 46. Exit:  
  47. 47. Approved Feasibility Report - Effort, Scope, Schedule, Current Status
  48. 48. IP Auditing Checklist</li></li></ul><li>Slide 13<br />Design/Verification IP Re-Engineering - Execution<br />Re-Engineering Requirements <br />Design Document availability?<br />No<br />Yes<br />Code Understanding<br />Understanding the Design <br />Creating / Enhancing Design Document<br /> Re-engineering Scenario Specific Activities<br />Review & Customer approved?<br />No<br />Yes<br />Packaging<br /><ul><li>Execution:
  49. 49. Follow the guidelines for different scenarios for re-eng and ensure less execution
  50. 50. Different phases of execution - Design change, RTL Modification, Verification, Synthesis, DFT, STA, P&R
  51. 51. Each phase is followed by an internal review and tracking
  52. 52. Entry:
  53. 53. RTL Data Base
  54. 54. Feasibility Report and Guidelines
  55. 55. Customer Requirement Specification
  56. 56. Exit Criteria:
  57. 57. Re-Engineered IP Database
  58. 58. Updated design doc</li></li></ul><li>Slide 14<br />Design/Verification IP Re-Engineering - Packaging<br /><ul><li>Packaging:
  59. 59. Supported by a well defined check-list for each activity
  60. 60. Check IP Quality and Use version control to track all the releases
  61. 61. Systematic bug tracking
  62. 62. Reviews and Sign-off at each stage
  63. 63. Package into MindTree or Customer format
  64. 64. Post delivery support
  65. 65. Entry:
  66. 66. Modified IP Database
  67. 67. Quality check metrics
  68. 68. Exit Criteria:
  69. 69. Quality Passed IP packaged into a MindTree or Customer format</li></li></ul><li>Slide 15<br />CSoC Infrastructure<br />
  70. 70. Slide 16<br />Advantages<br />Rapid Prototyping of SoC’s<br />Unified Platform from Architecture Exploration to System Development<br />Architecture Exploration<br />Virtual Prototyping<br />SoC Development & Verification<br />IP / SoC Validation<br />Seamless Software (Low Level Firmware, Middleware, Application) Development<br />GUI based Automation Framework<br />CSoC Uniqueness<br />Seamless Migration from AE, VPP, SoC Development to Prototyping<br />No Processor Dependencies<br />Adaptive Verification Environment<br />
  71. 71. Slide 17<br />Adaptive Verification Environment <br />
  72. 72. Slide 18<br />Validation Prototype <br />
  73. 73. Slide 19<br />Successful Customers<br />Happy People<br />Innovative Solutions<br />Our Mission<br />Rajagopalan_venktesan@mindtree.com<br />www.mindtree.com<br />© 2010 MindTree Limited<br />CONFIDENTIAL: For limited circulation only<br />
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