• Share
  • Email
  • Embed
  • Like
  • Save
  • Private Content
Mind tree ip soc
 

Mind tree ip soc

on

  • 2,100 views

 

Statistics

Views

Total Views
2,100
Views on SlideShare
2,086
Embed Views
14

Actions

Likes
0
Downloads
19
Comments
0

1 Embed 14

http://www.design-reuse.com 14

Accessibility

Categories

Upload Details

Uploaded via as Microsoft PowerPoint

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Mind tree ip soc Mind tree ip soc Presentation Transcript

    • IP Re Engineering – Challenges
    • Agenda
      IP Re Engineering Challenges
      • Introduction
      • IP Re Use and Challenges
      • IP Re-Engineering Activities
      • Internal IP Vs Third Party IP
      • Challenges and solutions
      • Challenges
      • Internal Vs External Team
      • Capabilities of the external Team
      • Solutions from MindTree
      • IP ReD
      • CSoC Initiative
      • Conclusion
      Slide 2
    • Introduction
      IP Reuse
      Time to Market
      Cost
      Optimized area, performance
      IP Re-engineering
      Engineering activities that are aimed to customize, port and make the existing IP available for new designs
      Challenges:
      Porting to different Technology libraries (Power, Performance)
      Verification/Validation/Proto type (Quality)
      Quality Documentation
      Support for different teams (internal/external)
      Enablers: Standard processes/methodology/Framework for
      Reusable IP Development
      IP Qualification and Verification
      Chip Integration
      IP Distribution and support
      Slide 3
    • IP Re Engineering Activities
      Design
      Feature Enhancements, Functionality modifications (fixing bugs)
      Optimizing the design for Power, Performance, Area
      Interface/Bus modifications
      Making the design more DFT/implementation friendly
      Verification/Validation
      Verification Environment optimization for coverage improvement
      Modifications to reflect and test the DUT enhancements
      Methodology migration (e – SV; Legacy – HVL)
      Integration/Physical Implementation/Maintenance
      Validating the IP for Integration
      Flow validation
      Release / Version Control
      User Documentation/update
      Slide 4
    • Internal IP Vs Third Party IP
      Internal IP
      IP that were developed and used within the organization
      Standard based, proprietary
      More visibility to the different designs in which the IP was used
      Access to the design team and details of the design, environment
      Legacy environment, custom tool flow and proprietary design components
      Integration issues due to insufficient documentation and validation
      Support from the IP owner to re-engineer the IP is possible
      Third Party IP
      Independent vendor developed IP
      Mostly Standard based
      Lesser visibility to the different design scenarios in which the IP was used
      Better user documentation possible as the IP is to be shared with different users
      Good qualification process to be in place before the reuse
      Support for customization from the vendor is key for success
      Slide 5
    • Challenges and Solutions
    • Execution
      • Planning and Forecasting
      • Resource optimization (activities Vs resources)
      • Legacy and third party IP
      • Team Preparation (training)
      Reuse Targets
      • Optimization (power, area, Performance)
      • Multiple SoC Platforms
      • Bus interfaces, Processors
      Quality/Process
      • Process adherence
      • Different flow qualification (CAD)
      • Metrics collection and analysis
      • Benchmarking & Certification
      • Training
      Challenges
      Engagement Models
      • Flexi Pool
      • Support for global teams and local centers
      • Issue based support
      • Support for external customers
      Scalability & Maintenance
      • Peak requirements handling
      • Support for existing IP
      • Multiple Target Platforms (Proc, Bus, OS..)
      Key Challenges
    • Internal Team Vs Design Services Team..
      More often the re-engineering or customization tasks are centered around
      Technology Migration, Bus interface modification
      Targeting different SoC platforms, resolving integration issues
      Improving the quality of the IP (Performance, Power, Area)
      Optimization of the design and verification environment (coverage improvement for functionality, manufacturing etc.,)
      Engaging a third party team for effective use of the resources and focused IP re engineering will result in
      Cost savings due to the effective utilization of the team that manages the IP enhancements and improvements
      Enables the customer team to focus on the domain specific activities
      Becomes a central team that supports different design teams
      Serves as a common knowledge platform where the project experiences are fed back and made available for different teams
      Slide 8
    • Capabilities of the Partner
      Slide 9
    • IP ReD
    • Slide 11
      Design/Verification IP Re-Engineering Life Cycle
    • Slide 12
      Design/Verification IP Re-Engineering - Auditing
      Existing DIP
      Database
                                                                                                                                                                                                                                                      
      Data Base Analysis                                                                      Env Analysis
      Methodology
      Compliance
      Tool-Specific
      Tool Used
      Design
      Documentation
      RTL Checks (Lint)
      Limitation on
      Existing Synthesis
      Logs & QoR Report
      Integration Compatibility at System level
      Verification Reports
      Feasibility analysis
      Re-engineering requirements
      No
      Customer
      Approval
      Customer’s estimation on time and resources
      Approved by customer
      Yes
      SOW / WBS
      Execution Phase starts
      • Auditing:
      • IP Re-eng schedule and schedule confidence
      • IP Re-eng effort estimate – leading to WBS
      • Clearly defined Customers & MindTree role in re-eng activity, Receivable and Deliverable
      • Quality of deliverables
      • Entry:
      • Customer Requirements
      • Latest Data Base of the IP
      • Standard Specification (Optional)
      • Exit:  
      • Approved Feasibility Report - Effort, Scope, Schedule, Current Status
      • IP Auditing Checklist
    • Slide 13
      Design/Verification IP Re-Engineering - Execution
      Re-Engineering Requirements
      Design Document availability?
      No
      Yes
      Code Understanding
      Understanding the Design
      Creating / Enhancing Design Document
      Re-engineering Scenario Specific Activities
      Review & Customer approved?
      No
      Yes
      Packaging
      • Execution:
      • Follow the guidelines for different scenarios for re-eng and ensure less execution
      • Different phases of execution - Design change, RTL Modification, Verification, Synthesis, DFT, STA, P&R
      • Each phase is followed by an internal review and tracking
      • Entry:
      • RTL Data Base
      • Feasibility Report and Guidelines
      • Customer Requirement Specification
      • Exit Criteria:
      • Re-Engineered IP Database
      • Updated design doc
    • Slide 14
      Design/Verification IP Re-Engineering - Packaging
      • Packaging:
      • Supported by a well defined check-list for each activity
      • Check IP Quality and Use version control to track all the releases
      • Systematic bug tracking
      • Reviews and Sign-off at each stage
      • Package into MindTree or Customer format
      • Post delivery support
      • Entry:
      • Modified IP Database
      • Quality check metrics
      • Exit Criteria:
      • Quality Passed IP packaged into a MindTree or Customer format
    • Slide 15
      CSoC Infrastructure
    • Slide 16
      Advantages
      Rapid Prototyping of SoC’s
      Unified Platform from Architecture Exploration to System Development
      Architecture Exploration
      Virtual Prototyping
      SoC Development & Verification
      IP / SoC Validation
      Seamless Software (Low Level Firmware, Middleware, Application) Development
      GUI based Automation Framework
      CSoC Uniqueness
      Seamless Migration from AE, VPP, SoC Development to Prototyping
      No Processor Dependencies
      Adaptive Verification Environment
    • Slide 17
      Adaptive Verification Environment
    • Slide 18
      Validation Prototype
    • Slide 19
      Successful Customers
      Happy People
      Innovative Solutions
      Our Mission
      Rajagopalan_venktesan@mindtree.com
      www.mindtree.com
      © 2010 MindTree Limited
      CONFIDENTIAL: For limited circulation only