Ip so c-30sept2010


Published on

Published in: Education
1 Like
  • Be the first to comment

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

Ip so c-30sept2010

  1. 1. Challenges in Designing a Low Power Speech Processing SoC -a designer’s perspective S. Krishnakumar Rao C-DAC
  2. 2. Agenda <ul><li>About C-DAC </li></ul><ul><li>Why low power? </li></ul><ul><li>Technology and Process selection </li></ul><ul><li>Low Power Design techniques </li></ul><ul><li>Speech processor SoC </li></ul><ul><li>ASTRA portfolio of IP </li></ul>
  3. 3. About C-DAC <ul><li>Scientific Society under DIT, Govt. of India </li></ul><ul><li>Application oriented R&D in Electronics and IT </li></ul><ul><li>Eleven development centres across India </li></ul><ul><li>Technologies </li></ul><ul><ul><li>High Performance Computing </li></ul></ul><ul><ul><li>Professional Electronics </li></ul></ul><ul><ul><li>Health Informatics </li></ul></ul><ul><ul><li>Ubiquitous Computing </li></ul></ul><ul><ul><li>Education and Training </li></ul></ul>
  4. 4. C-DAC, Thiruvananthapuram <ul><ul><ul><li>VLSI Design </li></ul></ul></ul><ul><ul><ul><li>Broadcast and Communication </li></ul></ul></ul><ul><ul><ul><li>Power Electronics </li></ul></ul></ul><ul><ul><ul><li>Control and Instrumentation </li></ul></ul></ul><ul><ul><ul><li>Strategic Electronics </li></ul></ul></ul><ul><ul><ul><li>Cyber Security </li></ul></ul></ul><ul><ul><ul><li>Language Technologies </li></ul></ul></ul>
  5. 5. VLSI Design Group at C-DAC(T) <ul><li>Professional design services with a well developed infrastructure for customers to realize their ideas from concept-to-silicon and to product; competitively </li></ul><ul><li>Design & development of IP cores for semiconductors, in the processor, serial communication and bus interfacing area under the brand name ASTRA </li></ul>
  6. 6. Why Low Power? <ul><li>Limited Battery Capacity </li></ul><ul><li>For Minimal Heat Dissipation </li></ul><ul><ul><ul><li>Heat Sink, System Size/Weight/Cost </li></ul></ul></ul><ul><li>For Chip/System reliability </li></ul><ul><li>Save Energy </li></ul>
  7. 7. Low Power Design - Application areas <ul><li>Bio-Medical </li></ul><ul><li>Mobile </li></ul><ul><li>Military </li></ul><ul><li>Space </li></ul>
  8. 8. Constraints in ASIC design <ul><li>The main constraints are </li></ul><ul><li>Speed/Performance </li></ul><ul><li>Power </li></ul><ul><li>Area </li></ul><ul><li>Cost (EDA, IP, NRE, Manpower..) </li></ul><ul><li>Primary constraints should be identified and prioritized for </li></ul><ul><ul><li>Technology & Process selection </li></ul></ul><ul><ul><li>IP selection </li></ul></ul><ul><ul><li>Design methodology </li></ul></ul>
  9. 9. Technology & Process selection <ul><li>Criteria for selection </li></ul><ul><ul><ul><li>Operating voltage </li></ul></ul></ul><ul><ul><ul><li>Operating frequency </li></ul></ul></ul><ul><ul><ul><li>Power dissipation </li></ul></ul></ul><ul><ul><ul><li>Chip area </li></ul></ul></ul><ul><ul><ul><li>Cost of production </li></ul></ul></ul><ul><ul><ul><li>Yield </li></ul></ul></ul>
  10. 10. Technology & Process: for Low Power <ul><li>Operating Voltage </li></ul><ul><ul><li>Choose the technology based on operating voltage </li></ul></ul><ul><ul><li>Minimise power converters </li></ul></ul><ul><li>Power consumption </li></ul><ul><ul><li>Choose low leakage (HVT) cells for low frequency application </li></ul></ul><ul><ul><li>When frequency of operation increases LVT cells can be used to optimize critical paths </li></ul></ul>
  11. 11. Technology & Process: for Low Power <ul><li>Dynamic power reduces with technology scaling, but leakage power increases </li></ul><ul><li>Development and fabrication cost increases with technology scaling </li></ul><ul><li>Availability of low power IP such as RAM, ROM & NVM </li></ul>
  12. 12. Selection of Hard IP: RAM & ROM <ul><li>Power consumption </li></ul><ul><ul><li>Macros with low standby current </li></ul></ul><ul><ul><li>Power consumption can be reduced by efficient usage </li></ul></ul><ul><li>Cost </li></ul><ul><ul><li>Free IP available from vendors, if cost is of prime concern </li></ul></ul>
  13. 13. Selection of Hard IP: NVM <ul><li>Require multiple voltage for operation </li></ul><ul><li>Design techniques can be adopted to reduce the power consumption of NVM </li></ul><ul><ul><li>The NVM content can be copied and executed from the RAM and enabling the standby mode for NVM thereafter. </li></ul></ul>
  14. 14. Selection of Hard IP : NVM <ul><li>Cost perspective: </li></ul><ul><ul><li>License fee </li></ul></ul><ul><ul><li>Use available memory IP and avoid cost escalation for customisation </li></ul></ul><ul><ul><li>Evaluate options depending on IP availability and cost </li></ul></ul><ul><ul><ul><li>An MTP can be replaced with an OTP using an efficient Memory management algorithm. </li></ul></ul></ul>
  15. 15. Selection of Hard IP: Clock management <ul><li>PLL </li></ul><ul><ul><li>Advantages </li></ul></ul><ul><ul><ul><li>Variable clock frequency </li></ul></ul></ul><ul><ul><ul><li>Highly stable clock with low jitter </li></ul></ul></ul><ul><ul><li>Disadvantage </li></ul></ul><ul><ul><ul><li>Power consumption </li></ul></ul></ul><ul><li>Oscillator Pad </li></ul><ul><ul><li>Advantage </li></ul></ul><ul><ul><ul><li>Less power consumption </li></ul></ul></ul><ul><ul><li>Disadvantage </li></ul></ul><ul><ul><ul><li>Single frequency </li></ul></ul></ul>
  16. 16. Low Power Design techniques <ul><li>Industry has a bunch of low power design techniques. But are they all required for my design? </li></ul><ul><li>Select the design techniques wisely? </li></ul>
  17. 17. Low Power Design techniques <ul><ul><ul><li>Clock gating </li></ul></ul></ul><ul><ul><ul><li>Data gating </li></ul></ul></ul><ul><ul><ul><li>Power gating </li></ul></ul></ul><ul><ul><ul><li>Frequency scaling </li></ul></ul></ul><ul><ul><ul><li>Voltage scaling </li></ul></ul></ul><ul><ul><ul><li>Variable device threshold </li></ul></ul></ul>
  18. 18. Clock gating CLK EN EN1 GCLK EN D Q
  19. 19. Clock gating <ul><li>Dynamic power reduction </li></ul><ul><li>Define the Active mode of the chip </li></ul><ul><li>Identify switching activity of various modules </li></ul><ul><li>Apply clock gating efficiently </li></ul><ul><li>Disadvantages </li></ul><ul><ul><li>Area overhead </li></ul></ul><ul><ul><li>CG without proper analysis may result in higher power consumption for certain modules </li></ul></ul>
  20. 20. Data Gating
  21. 21. Data Gating <ul><li>Dynamic power reduction </li></ul><ul><li>If not used efficiently Data gating will cause </li></ul><ul><ul><li>More power consumption </li></ul></ul><ul><ul><li>Area overhead </li></ul></ul><ul><ul><li>Critical path violation </li></ul></ul><ul><li>Switching activity of candidates to be analyzed prior to gating </li></ul><ul><li>Usually more effective for power reduction in bus-structures </li></ul>
  22. 22. Power gating Courtesy: Cadence Design Systems
  23. 23. Power gating <ul><li>Advantage </li></ul><ul><ul><li>Leakage power reduction </li></ul></ul><ul><li>Disadvantages </li></ul><ul><ul><li>Design complexity </li></ul></ul><ul><ul><li>Verification complexity increases </li></ul></ul>
  24. 24. Voltage and Frequency scaling <ul><li>Voltage & frequency scaling are done in tandem </li></ul>Courtesy: Cadence Design Systems
  25. 25. Speech Processor Application
  26. 26. NAADA - Speech processor <ul><li>SoC for low power speech processing applications </li></ul><ul><li>Integrates in-house IP </li></ul><ul><li>Features </li></ul><ul><ul><ul><ul><li>1.2V single supply operation </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Low power consumption < 5mW </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Frequency of operation - 20MHz </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Integrated 1Mbit NVM </li></ul></ul></ul></ul><ul><ul><ul><ul><li>64KB RAM </li></ul></ul></ul></ul><ul><ul><ul><ul><li>32KB ROM </li></ul></ul></ul></ul>
  27. 27. “ NAADA ” integrates <ul><li>In-house IPs Integrated </li></ul><ul><li>32-bit RISC processor </li></ul><ul><li>DSP IPs </li></ul><ul><ul><li>FFT & IFFT </li></ul></ul><ul><ul><li>MAC </li></ul></ul><ul><li>UART </li></ul><ul><li>SPI </li></ul>OTP 128KB 1.2V ROM 32KB 1.2V SRAM 64KB 1.2V DSP Engine CPU Glue Logic Standard Cells ( 1.2V , 130nm,LL) DSP Engine Volt. Doubler
  28. 28. ASTRA – IP Portfolio <ul><li>Processor </li></ul><ul><ul><li>ER8051: 8-bit microcontroller compatible with Intel 8051 </li></ul></ul><ul><ul><li>ER8085: 8-bit microprocessor compatible with Intel 8085 </li></ul></ul><ul><ul><li>ER9101: 16-bit Bit Slice ALU </li></ul></ul><ul><ul><li>ER902: 32-bit RISC Processor </li></ul></ul><ul><ul><li>ERASP8051: Asynchronous 8-bit microcontroller </li></ul></ul><ul><li>Peripheral </li></ul><ul><ul><li>ERRTC: Real Time Clock </li></ul></ul><ul><ul><li>ERTIMER: 32-bit configurable timer </li></ul></ul><ul><ul><li>ERDMA: 8237 compatible DMA controller </li></ul></ul><ul><ul><li>ER15530: Manchester Encoder Decoder </li></ul></ul>
  29. 29. ASTRA – IP Portfolio <ul><li>Communication </li></ul><ul><ul><li>ER16450: UART compatible with NS16450 </li></ul></ul><ul><ul><li>ERUSB2: USB 2.0 Device Controller </li></ul></ul><ul><ul><li>ERMAC: IEEE802.3 compliant 100Mbps Media Access Controller </li></ul></ul><ul><ul><li>ERGMAC: IEEE802.3 compliant 1Gbps Media Access Controller </li></ul></ul><ul><ul><li>EROTG: USB2.0 On-The-Go Controller </li></ul></ul><ul><ul><li>ERUSB2: USB2.0 Device Controller </li></ul></ul><ul><ul><li>ERUSBHC: USB2.0 Host Controller </li></ul></ul><ul><ul><li>ERSATAII: SATAII Host Controller </li></ul></ul><ul><ul><li>ERPCIe: PCIe endpoint </li></ul></ul><ul><li>Sigma-Delta ADC Mixed Signal IP </li></ul>
  30. 30. Thank You