How can we keep our FPGAs from falling into the Productivity Gap

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Phil Dworsky is a veteran of more than 25 years in EDA and IP. With Synopsys since 1993, he is currently director, strategic alliances as well as publisher of Synopsys Press, an imprint of Synopsys …

Phil Dworsky is a veteran of more than 25 years in EDA and IP. With Synopsys since 1993, he is currently director, strategic alliances as well as publisher of Synopsys Press, an imprint of Synopsys creating and delivering technical and business publications. Prior to his current positions, Phil held management positions in marketing, technical marketing and corporate applications at Synopsys, most recently as director, marketing and applications for DesignWare IP.

Phil was a co-founder and principal engineer at Performance Processors, a parallel processing company, and was also a co-founder of Silicon Solutions/Zycad, an early provider of simulation acceleration technology. He started his career at Hewlett-Packard as a hardware and software designer. Phil holds a Bachelor of Science degree with high honors in electrical engineering and computer science (EECS) from Princeton University.

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  • In 1999, the Semiconductor Industry Association published this International Technology Roadmap for Semiconductors (ITRS).They identified that extrapolating the trends in tool and silicon development, then there will be an ever increasing gap between the number of transistors that might be fabricated and the number that can be designed. The scary numbers here were a doomsday warning that semiconductor design productivity needed to improve more quickly.
  • Productivity gap didn’t happen. Why not? IP and tools. It wasn’t easy and it wasn’t free.R&D dollars (and euro, pounds, yen, etc.)Basically, that’s why people pay for EDA
  • If we look at the basic steps in an ASIC/SoC flow switch to the world of ASIC/SoC (hence the nice Synopsys purple) we see that more time is spent on specification and verificationWith an even greater emphasis on verification.
  • We can run the same exercise in FPGA.FPGA design once upon a time was an iterative process. Enter something (perhaps in schematic, perhaps in an HDL) then run the tools and then program/download the design into the chip in the system. If it didnt work then plul out some testpoints, do a bit of debug, and go around the loop a few times, then a few time more , then . . .you get the idea.If we still designed FPGAs like we did in the early years then we wouldn’t be having this panel and FPGA business would be a small fraction of its current levels. Some of us may even be out of business. We’re not; so what happened?.
  • Basically, FPGA front-end has become much like the ASIC/SoC front end.First of all, we design FPGA using the same HDLs that we use to design ASIC, with SystemVerilog become dominant. We can also adopt higher-level design techniques to help us specify at least part of the design. Our own Synphony C and model based tools are a good example of a common design specification flow for both FPGA and ASIC/SoC.We also find much greater usage of advanced verification methodology for FPGAs. Those powerful methods like VMM and UVM are equally applicable to FPGA RTL, and their use is growing albeit slowly. Why? Perhaps because the cost of under-verification in FPGA is not so high (although it is far from zero). Perhaps also because it takes an investment in training and tools that FPGA teams have yet to embrace. Is this a kind of denial?In addition, studies show that the development and validation of the embedded software in SoC designs dominates the effort. Considering the software tools and methods, the effort will be the same for the growing number of FPGA designs which include CPU IP. Are FPGA teams prepared for that?In summary, when we boil it down, the flow necessary for today’s FPGAs is the same as for ASIC/SoC (although some of the tools will be different).
  • IP and tools will lead the way. Can vendors be expected to provide leading edge tools and IP for stupidly low bucks?Will some FPGA designers leave QoR on the bench because the best tools and IP are “too expensive”?Will the productivity gap apply really only to FPGA, while ASIC/SoC teams sail happily into the sunset?

Transcript

  • 1. How can we keep our FPGAs from falling into the Productivity Gap? Phil Dworsky Synopsys© Synopsys 2011 1
  • 2. The view from 1997 . . .© Synopsys 2011 2
  • 3. How did we survive? • The Productivity Gap didn’t happen – Well, not yet anyway • Why? – More IP, Bigger IP – Better Tools – R&D Investment© Synopsys 2011 3
  • 4. ASIC/SoC design flow today (simplified) IP Specify Enter Verify Build Proto & Silicon Debug Debug© Synopsys 2011 4
  • 5. FPGA Design In The Beginning Enter Proto & Debug© Synopsys 2011 5
  • 6. FPGA Design Today (as it needs to be) NOTE: Embedded Software development and debug is a dominant effort in chip design. It is exactly the same for FPGA and ASIC/SoC. Specify Enter Verify Proto & Debug© Synopsys 2011 6
  • 7. One More Thing . . . DesignWare IP Design RTL FPGA Synthesis SoC Implementation Certify/ DW Implementation Galaxy DW Implementation Synplify Premier Common IP and Source Code for FPGA, for Prototype, for ASIC/SoC© Synopsys 2011 7
  • 8. The View in 2011 . . . • Front-end design for FPGAs is already as complex as it is for ASIC/SoC but some FPGA designers are still in denial • There will be an FPGA Productivity Gap • It can be solved . . . Should we expect the FPGA vendors to do this “for free?” – More IP, bigger IP Will FPGA designers (and verifiers) – Better Tools make the investment? – R&D Investment Will FPGA companies freely open access to third-party tool & IP vendors?© Synopsys 2011 8