Memory Barriers

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Memory barriers, or fences, are a set of processor instructions used to apply ordering limitations on memory operations.

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Memory Barriers

  1. 1. Dennis Byrne [email_address] <ul><li>Memory Barriers </li></ul>
  2. 2. Defining the Problem Object connection = null; boolean initialized = false; // thread 1 writes twice // thread 2 reads twice connection = new Connection(); if(initialized) initialized = true; connection.use(); NullPointerException ?
  3. 3. Root Cause: Memory Latency <ul><li>Processors work hard to avoid memory latency </li></ul><ul><ul><li>memory operations (reads & writes) are re-ordered </li></ul></ul><ul><li>This is not a problem when … </li></ul><ul><ul><li>data is local and/or immutable </li></ul></ul><ul><ul><li>there is only single processor </li></ul></ul><ul><li>People do this also … </li></ul>
  4. 4. Introduction Memory barriers, or fences, are a set of processor instructions used to apply ordering limitations on read and write operations .
  5. 5. Visibility is “kind of” important <ul><ul><li>The Java Memory Model </li></ul></ul><ul><ul><li>Erlang send operators </li></ul></ul><ul><ul><li>Retlang and Jetlang Channels </li></ul></ul><ul><ul><li>C++ atomics </li></ul></ul><ul><ul><li>Scala Actors </li></ul></ul><ul><ul><li>Every semaphore, mutex, or atomic operation </li></ul></ul>
  6. 6. Classifying Memory Barriers <ul><li>Which memory operations does this membar sit between? </li></ul><ul><ul><li>LoadLoad </li></ul></ul><ul><ul><li>LoadWrite </li></ul></ul><ul><ul><li>WriteWrite </li></ul></ul><ul><ul><li>WriteLoad </li></ul></ul><ul><li>Which memory operations are we serializing? </li></ul><ul><ul><li>Unidirectional </li></ul></ul><ul><ul><li>Bidirectional </li></ul></ul>
  7. 7. Dekker’s Algorithm <ul><li>// 1st thread </li></ul><ul><li>intentFirst = true; </li></ul><ul><li>while (intentSecond) </li></ul><ul><li>if (turn != 0) { </li></ul><ul><li>intentFirst = false; </li></ul><ul><li>while (turn != 0) {} </li></ul><ul><li>intentFirst = true; </li></ul><ul><li>} </li></ul><ul><li>criticalSection(); </li></ul><ul><li>turn = 1; </li></ul><ul><li>intentFirst = false; </li></ul>// 2nd thread intentSecond = true; while (intentFirst) if (turn != 1) { intentSecond = false; while (turn != 1) {} intentSecond = true; } criticalSection(); turn = 0; intentSecond = false;
  8. 8. Consecutive Volatile Writes on Itanium 2 <ul><li>1 adds r37=592,r36;; ;...0b284149 0421 </li></ul><ul><li>st4.rel [r37]=r39 ;...00389560 2380 </li></ul><ul><li>adds r36=596,r36;; ;...84112544 </li></ul><ul><li>4 st1.rel [r36]=r0 ;...09000048 a011 </li></ul><ul><li>5 mf ;...00000044 0000 </li></ul><ul><li>6 nop.i 0x0;; ;...00040000 </li></ul><ul><li>7 mov r12=r33 ;...00600042 0021 </li></ul><ul><li>8 mov.ret b0=r35,0x2000000001de81e0 </li></ul>The other side of the protocol ….
  9. 9. Consecutive Volatile Reads on Itanium 2 <ul><li>1 adds r37=597,r36;; ;...84112554 </li></ul><ul><li>2 ld1.acq r38=[r37];; ;...0b30014a a010 </li></ul><ul><li>3 nop.m 0x0 ;...00000002 00c0 </li></ul><ul><li>4 sxt1 r38=r38;; ;...00513004 </li></ul><ul><li>5 cmp4.eq p0,p6=0,r38 ;...1100004c 8639 </li></ul><ul><li>6 nop.i 0x0 ;...00000002 0003 </li></ul><ul><li>7 br.cond.dpnt.many 0x2000000001de8220;; </li></ul>One side of the protocol ….
  10. 10. Implicit Memory Barriers <ul><li>mov 0x160(%edi),%edi ;...8bbf6001 0000 </li></ul><ul><li>mov %ecx,%edi ;...8bf9 </li></ul><ul><li>add $0x8,%edi ;...83c708 </li></ul><ul><li>lock cmpxchg %esi,(%edi) ;...f00fb137 </li></ul><ul><li>mov $0x1,%eax ;...b8010000 00 </li></ul>Atomic CAS operation on x86 lock cmpxchg serializes pending memory operations
  11. 11. Avoiding Memory Barriers <ul><li>Atomic CAS on a VMWare image with one processor: </li></ul><ul><ul><li>add $0x8,%edi ;...83c708 </li></ul></ul><ul><ul><li>cmpxchg %esi,(%edi) ;...0fb137 </li></ul></ul><ul><ul><li>mov $0x1,%eax ;...b8010000 00 </li></ul></ul><ul><li>Consecutive volatile reads in Java on SPARC: </li></ul><ul><ul><li>ld [ %l1 + 0x150 ], %i0 ;...f0046150 </li></ul></ul><ul><ul><li>sethi %hi(0xff3fc000), %l0 ;...213fcff0 </li></ul></ul><ul><ul><li>ld [ %l0 ], %g0 ;...c0042000 </li></ul></ul><ul><ul><li>ret ;...81c7e008 </li></ul></ul>
  12. 12. Memory Barriers <ul><li>Thanks </li></ul><ul><li>Dennis Byrne – DRW Trading </li></ul><ul><li>[email_address] </li></ul>

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