Seminar Placement and Routing options in Full Custom Shankardas Deepti Bharath CGB0911002 VSD528 M. Sc. [Engg.] in VLSI System Design Module Title: Full Custom Physical Design Module Leader: Mr. Chandramohan P.
Macro and Pad cell locations are defined during the Floorplanning stage, before P&R.
Standard cells are placed in “placement rows” during placement.
Placement rows are commonly abutted to reduce core area. Cell orientations in abutted rows are normally flipped.
Cells in a timing-critical path are placed close together to reduce routing-related delays.
The circuit delay, power dissipation and area are the main objective of placement.
Rout-ability (or congestion) is a function of the number of available tracks in a given area
compared to the number of signals that need to be routed through that area.
Routing along the timing-critical path is given priority: Creates shorter, faster connections therby reducing parasitics.
References  Jon Wateresian (2002) Fabricating Printed Circuit Boards. Massachusetts: Newnes  Linfu Xiao, et al. , ‘ Practical Placement and Routing Techniques for Analog Circuit Designs’ , IEEE, Dept. of CSE, Chinese Univ. of Hong Kong, Shatin, China, Dec 2010.  Chandramohan P., Digital circuit design and layout, Full custom physical design (VSD 528), session-2 MSRSAS, Bangalore  Shawki Areibi and Zhen Yang (2003), ‘Congestion Driven Placement for VLSI Standard Cell, Design’ , School of Engineering, University of Guelph, Ontario, Canada, Dec 2003.