Real-time Embedded Systems Lecture 5 Understanding targets- 8086 based systems Prof. Dr. Amitava Gupta Department of Power Engineering Jadavpur University, India Real-time Embedded Systems- Lecture 05
Real-time Embedded Systems- Lecture 05 Embedded System? Application Operating System Hardware + What have we learnt? Interface with application
Real-time Embedded Systems- Lecture 05 We start with a survey of 8086 based systems AH BH CH DH AL BL CL DL SP BP SI DI IP CS SS DS ES Instruction queue Control Logic ALU PSW 20 16 Address Data Control
Real-time Embedded Systems- Lecture 05 Pipelined Architecture The fetching and execution activities overlap. Instructions are pre-fetched and kept in instructions queue. While one instruction is being executed, the next one is fetched. This is because of the fact that fetch and execution units are separate. When processors have more than one execution unit, they are said to have a superscalar architecture. The Pentium is an example of such processors.
Real-time Embedded Systems- Lecture 05 Bus Organized Computers A set of conductors used for communicating information between the components of a computer is called a bus. External bus- connects two major components e.g. CPU and memory.This is the system bus. Internal bus- connects two minor components within a major component e.g. set of working registers and the control unit. Components which control the Bus are called bus masters, e.g. CPU,DMA controller etc.
Real-time Embedded Systems- Lecture 05 System Bus Timing contd.. T 1 T 2 T 3 T w T 4 T 4 T i T i Bus Cycle : Activity involved in transferring a byte or word over system bus is called bus cycle. The execution of an instruction may require more than one bus cycle. The timing of signals within the CPU and bus control logic is controlled by a clock. The bus cycles and CPU activity are controlled by groups of clock pulses. The exact number of clock pulses or cycles within a bus cycle varies
Real-time Embedded Systems- Lecture 05 T 1 T 2 T 3 T 4 Read timing for 8086 without wait states Address out Data in ALE RD Device sends a Ready signal here else wait states are introduced between T 3 and T 4 T w
Real-time Embedded Systems- Lecture 05 Physical memory organization o e + D 15 -D 8 D 7 -D 0 512 KB each Selectable by bit A 0 OA = EA + 1 So, for an even address the next odd address can be obtained by using A 0 = 1 keeping all other bits same Address Address + 1
Real-time Embedded Systems- Lecture 05 Basic addressing scheme uses two 16 bit registers to compute a 20 bit address The memory is ‘logically’ organized into segments 1M 64K 16 bit segment register 16 bit pointer register offset 4 Bits base
Real-time Embedded Systems- Lecture 06 Excercise If the physical address is 5A230 when [CS] = 5200, what will it be [CS] becomes 7800? Solution:
Real-time Embedded Systems- Lecture 05 Interrupts (Hardware Interrupts) Each interrupt is associated with an Interrupt Service Routine (ISR) that is executed when an interrupt occurs Interrupt table IP type 0 CS type 0 00000 00002 00004
Real-time Embedded Systems- Lecture 05 Interfacing External Interrupts CPU PIC 8259 INTR T 1 T 2 T 3 T 4 ALE T 4 INTA AD7-AD0 INTA
Real-time Embedded Systems- Lecture 05 <ul><li>Establishing the type N </li></ul><ul><li>Pushing the contents of PSW, CS </li></ul><ul><li>and IP into the stack </li></ul><ul><li>Clearing the IF and TF flags </li></ul><ul><li>Loading content of 4*N into IP </li></ul><ul><li>and 4*N + 2 into CS </li></ul>Interrupt Sequence
ICW 1(Chip Control) ICW 2(Type) ICW 3(Slave Control) ICW 4(Mode Control) OCW 1(IMR) OCW 2 OCW 3 In Service Register Priority Resolver IRR & ML 20 20 20 21 21 21 21 Real-time Embedded Systems- Lecture 05 0 7 0 1 I 0 1 INT 0 Pending INTA
Real-time Embedded Systems- Lecture 05 1 ADI SNGL LTIM IC 4 0 0 0 SFNM M/S AEOI BUF µPM ICW4- Mode Control ICW1- Chip Control
Real-time Embedded Systems- Lecture 05 Requests arrive simultaneously on IRQ2 and IRQ4, & while IR2 routine is being executed, IRQ1 arrives! Main Program IRQ2 IRQ4 D2 in ISR set IR2 ----------- Reset IF (STI) . . . IRET IRQ1 IR1 ----------- Reset IF (STI) . . . IRET D1 in ISR set IR4 ----------- Reset IF (STI) . . . IRET D1 in ISR reset D2 in ISR reset D4 in ISR set