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SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
SNUG 2011 paper
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SNUG 2011 paper

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  • 1. Power Gating Design Implementation With Tapless Cells – What You Need To Know Kaijian Shi Synopsys Professional Services Dallas, USA kaijian@synopsys.com David Tester Structured Custom Cambridge, UK david.tester@structured-custom.com ABSTRACT65nm and beyond CMOS designs are commonly implemented with tapless library cells which donot have built-in well taps. To maintain proper transistor back biasing and prevent latch-up,special tap cells need to be inserted at intervals satisfying the tap rules. In power-gating designs,the tap cell insertion becomes complicated due to not only co-existence of always-on and power-gated domains but also different supply voltages applied to different domains. This paperdescribes a domain-based tap insertion methodology and implementation techniques to ease thecomplicity and minimize risks of incorrect tap insertions in power gating designs.
  • 2. Table of Contents1. Introduction ........................................................................................................................... 32. Tapless design and conventional tap insertion method......................................................... 33. Tap insertion requirements in power-gating designs ............................................................ 5 1. ALWAYS-ON TAP CELL........................................................................................................ 5 2. ALWAYS-ON WELL TAP POWER CONNECTIONS .................................................................... 64. Challenges in tap insertions in power-gating designs ........................................................... 6 1. DOMAIN-BASED TAP TYPE SELECTION ................................................................................ 6 2. DOMAIN-BASED TAP POWER LOGIC CONNECTIONS.............................................................. 6 3. DOMAIN-BASED TAP POWER PHYSICAL CONNECTIONS ........................................................ 7 4. OFF-GRID TAP INSERTION AND POWER CONNECTIONS ......................................................... 85. Domain-based tap type selection method ............................................................................. 86. Domain-based tap cell logic PG connection method ............................................................ 97. Domain-based tap cell physical PG connection method..................................................... 108. Off-grid tap insertion and power connections .................................................................... 129. Results ................................................................................................................................. 1310. Summary ............................................................................................................................. 1411. References ........................................................................................................................... 1512. Author biographies.............................................................................................................. 15SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 3. 1. Introduction65nm and beyond CMOS designs are commonly implemented with tapless library cells for lowcost in silicon area. The tapless cells do not have built-in taps that connect n-well and p-substrateto the power and ground rails. To prevent latch-up and maintain proper transistor back biasing,special tap cells are inserted in the layout at the required interval to connect n-wells to VDD andp-substrate to VSS based on tap rules defined in the technology DRC file.In a traditional single voltage domain design standard cells are all connected to VDD and VSSrails that are always active when the chip is powered on. As the result, the tap insertion intraditional design was relatively easy and could be done reliably by the ICC tap insertion flow.However, the tap cell insertion becomes complicated in power-gating designs which oftencontain both always-on and shutdown blocks where power can be turned off. For a power-gatingblock, special taps (always-on taps) are required to prevent latch-up and maintain propertransistor back biasing when power supplies to the standard cells in the block are turned off,while Power-Management (PM) cells in the block are active. Also, the tap cells need to belogically and physically connected to the correct power supplies to ensure power integrity. Asthe result, a domain-based PM tap insertion flow becomes both necessary and critical in a taplesspower-gating design until such an automated flow is implemented in ICC in the future. Thispaper describes the domain-based tap insertion method and implementation techniques whichhave been integrated in our low-power design flow and have been used successfully in a numberof production low-power designs.In the rest of the paper, the normal tap design and tap insertion method are outlined first. Then,special requirements for tap insertion in power-gating designs are outlined. Design of always-ontaps and challenges in the PM tap insertion are explained. Next, the domain-based PM tapinsertion method is described in detail with supporting scripts and an example is provided todemonstrate the method.2. Tapless design and conventional tap insertion methodIn conventional CMOS designs, the n-wells of PMOS transistors are connected to the VDDsupply and the p-substrate of NMOS transistors is connected to the VSS supply to implement thenecessary transistor back bias connectivity and prevent potential latch-up problems. Until sub-65nm, such well connections were often implemented by well taps contained within logic cells instandard cell libraries. This simplified the DRC aspect of design closure since well and substrateconnections were taken care of in the standard cells and hence transparent to front-end chipdesigners.In 65nm and beyond, the well and substrate taps in the standard cells become a considerable areaoverhead. To reduce area and silicon cost, library vendors remove taps from the standard cells.Consequently “tapless” standard cells are commonly used in sub-65nm production designs.SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 4. To maintain required transistor back bias and prevent latch-up, n-well in a standard cell isextended at cell boundary to form continuing wells when the standard cells (including filler cells)are abutted in the design. The wells are connected to VDD and VSS supplies by tap cells insertedat interval based on the tap rule defined by the technology to get well bias and prevent latch-up.The tap cell is a simple standard cell which has an n-well tap connected to VDD rail and a p-substrate tap connected to VSS rail as shown in Fig. 1. Figure 1 – Typical Standard Cell Library Tap CellWhen integrated in the design, the tap cell VDD and VSS rails are aligned with the rails of thedesign, as shown in Fig. 2, to connect VDD and VSS power supplies along the standard cell row.Substrate and n-well connections are provided by taps within the tap cells. Tap insertion innormal SOC design is not complicated since EDA tools usually provide a facility to insert the tapcells and guarantee meeting tap rules defined in the technology DRC runset. In ICC, this is doneby the command add_tap_cell_array. Power connections of the taps are automatically providedthrough the cell row VDD and VSS rails. Figure 2 – Standard Tap Cell Implementation ExampleSNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 5. 3. Tap insertion requirements in power-gating designsPower-gating design has become popular in sub-65nm designs to combat the increasingly largeleakage power from arising from technology scaling as transistor oxide thickness has decreased.In the power-gating design, a power domain (usually containing several functional blocks) canbe shut down while other domains within the device are active.In the power-gated block, VDD rails are controlled by switch cells and these power rails will befloating when the switch cells are turned off. In the conventional tap insertion method, the n-well connectivity is obtained through the tap cell VDD rail connections as shown in Fig. 1. Sincethe power gated VDD rail is floating, the bias voltage for the n-well is not controlled (since thelocal VDD voltage will decrease over time) and will lead to back-bias problems such as leakageand latch-up for the transistors in the power-gated domain. Consequently, the conventional tapinsertion method is no longer appropriate in the power-gating design. To maintain n-well bias inthe power-gated block, we need a different tap cell (always-on tap cell), always-on powersupplies to the taps and a modified tap methodology. 1. Always-on tap cellSince the local VDD power supply are not available in shutdown mode for the power-gatedblock, we need an always-on tap cell that has a global, dedicated always active VDD powersupply connected to the n-wells. This is done by creating always-on well tap pins that can beconnected to chip always-on VDD and VSS supplies. In the VDD gated power-gating design,only n-well tap pin is needed. The p-substrate can still connected to VSS rail to maintain wellbias as the VSS rail remains connected in the shutdown mode for the power-gated block. Anexample of such an always-on tap cell for VDD gated design is shown in Fig. 3. where the n-welltap is no long connected to the VDD rail in the cell. It becomes a pin that connects to the chippower supply. Figure 3 – Always-On Tap CellSNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 6. 2. Always-on well tap power connectionsHaving the always-on tap cells inserted within the shutdown blocks, the next task is to connecttheir well tap pins to always-on power supplies. The power and ground rails that provide thepower supplies to standard cells in the power-gated domain can no longer be used for tap powersupply because they would be turned off in the shutdown mode. Consequently, an always-on tapgrid needs to be created to acomplish the required tap power connections. Moreover, the tap cellsare often inserted at irregular grid pattern in complex design to satisfy the tap rules. This resultsin challenges in the always-on tap power connections to ensure that all the tap cells areconnected to the always-on power supplis. The details of the challenges are described in thefollowing sections.4. Challenges in tap insertions in power-gating designsThe special tap insertion requirements for power-gated blocks and the co-existence of active andpowered-down blocks in a same design impose a number of challenges in the tapless power-gating design. These challenges are outlined below. 1. Domain-based tap type selectionNormal taps (as shown in Fig 1) should be inserted in always-on power domains since tapconnections to n-well and substrate are implemented through the local VDD and VSS power railconnections. For power-gated domains, always-on tap cells (as shown in Fig 2) must be used tomaintain n-well bias when the domain is in the shutdown mode and the local VDD net is notconnected to the global VDD net. Currently, P&R layout tools rely on the user to define andimplement such domain-based tap insertion. It is desirable to automate the tap selection based onthe domain types. 2. Domain-based tap power “logic“ connectionsIn physical synthesis, tap power connections need to be defined in terms of “logic“ connectionsand physical connections. The physical connections are in the form of metal connections thatsupply electric current to the devices while the “logic“ connections are used to define powerconnection information with device pins. Such information, imclunding VDD and VSS supplynames, voltage levels and association, is needed for domain-based physical synthesis and powernetwork generations. The power “logic“ connections are defined by specifying device pin namesand connected power net names. In the always-on domains, the tap power pins are connected tothe domain power nets. In the power-gated domains, the VDD pin of the always-on tap cells isconnected to the domain switched VDD which is mapped to the power rails in the domain powergrid. The n-well tap pin (VDDC) of the tap cells must be connected to the always-on power net.This multi-PG connection requirement imposes a challenge in ICC due to the power connectionlimitation in add_tap_cell_array and the physical only cells power hookup inderive_pg_connection as outlined below.SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 7. Case 1: Use connection_power_name option in add_tap_cell_array to define PGconnections (pre-2010.12) add_tap_cell_array -master_cell_name $tap_cell -distance $tap_pitch -ignore_soft_blockage true -pattern every_other_row -voltage_area $va -tap_cell_identifier $pd -offset $offset -skip_fixed_cells false -fill_boundary_row false -fill_macro_blockage_row true -connect_power_name vddICC hooks up both VDD and VDDC pins of the always-on taps to the global power supply netVDD. This is due to command limitation that only one power connection option is available inthe command while the always-on tap needs two power connnections.Case 2: Do not connect power in add_tap_cell_array and then use derive_pg_connection todo logic connections add_tap_cell_array … (without -connect_power_name option) derive_pg_connectionIn this case, the tap insertion did not hook up tap power pins as instructed. The hook up is doneby the following command derive_pg_connection. Unfortunately, derive_pg_connectionconnects power pins of the physical only cells to domain primary power net which is theswitched vdd in the power-gated domain. Consequently, both VDD and VDDC pins of thealways-on taps are connected to switched supply vdd. This is incorrect.The issue is getting worse in ICC2010.12 where add_tap_cell_array automatically connects allpower pins to domain primary power even if the always-on supply net VDD is defined in option"-connect_power_name" due to a tool bug.It is worth noting that the tap cells are physical cells which do not have signal pins nor a logicalfunction.Consequently, they are not compiled into standard cell libraries like other power-management cells for physical synthesis. 3. Domain-based tap power physical connections The always-on tap power physical connections are also challenge. Since always-on power gridmay not close to the always-on taps, the power routes from the always-on taps to the always-ongrid could result in considerable impact on signal routing. Good planning considering both thetap insertions and tap power connections is needed to address the issue.SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 8. 4. Off-grid tap insertion and power connectionsOff-grid taps are often inserted in designs containing macros in order to satisfy the n-well andsubstrate tap spacing rules in the DRC deck. In the example shown in Fig. 4 containing RAMmacros those taps inserted in the RAM channel and right side of the RAM block boundary are ata half of the tap pitch to properly connect to the n-well tap and substrate tap connectivity of thestandard cells in the regions. The off-grid taps do not have an always-on power supply, becausethey are not covered by the always-on tap grid which is commonly built alinged with taps at thetap pitch. Consequently, we need facilities to detect the off-grid taps and provide always-onpower routes to connect their power pins correctly. Currently, ICC does not provide suchfacilities. Figure 4 – Off Grid Tap Cells and Power Connections5. Domain-based tap type selection methodA tcl script was written to implement a method to select correct type of tap cells for every powerdomain based on the domain type. Due to customer flow proprietary constraints, the method isoutlined by the pseudo-code below. Theproc select_tap {domain} { if { [sizeof_collection [get_power_switch –of $domain]] > 0 } { if 9 track standard_cell domain { return 9 track always-on tap cell } else { return 11 track always-on tap cell } } else { # non-pm domain if 9 track standard_cell domain {SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 9. return 9 track normal tap cell } else { return 11 track normal tap cell } }}foreach domain $domain-list { set tap_cell [select_tap $domain] insert_tap_cells $tap_cell $domain}6. Domain-based tap cell logic PG connection methodThe logic PG connections of normal taps in non-shutdown domains can be done correctly byderive_pg_connection. However, the logic PG connections of always-on taps in power gateddomains are problematic due to the co-existence of switched and always-on VDD pins, asdescribed in section 4. Two methods have been developed to solve the problems.In the first method, we do not specify any logic connection option in add_tap_cell_array.Consequently, all tap cell power and ground pins remain unconnected after the tap insertion.Then, we perform a multiple pass derive_pg_connection to resolve the issue described above inderive_pg_connection and complete the tap cell logic PG connections. The first pass connectsthe tap always-on VDD pins (VDDC) to the always-on supply net (vdd). The second passconnects taps’ switched VDD pins (VDD) to the domain switched-vdd net. The remaining PGpins are connected by the final derive_pg_connection. For the taps cells that have back biaspins (VNW, VPW), the pins are connected to vdd and vss supply nets respectively.proc always_on_tap_pg_connect {domain} { add_tap_cell_array -voltage_area $domain.voltage_area … more options … (without -connect_power_name option) derive_pg_connection -cells $always_on_tap_cells -power_net vdd -power_pin VDDC -ground_net vss -ground_pin VSS derive_pg_connection -cells $always_on_tap_cells -power_net vdd -power_pin VNW -ground_net vss -ground_pin VPW derive_pg_connection -cells $always_on_tap_cells -power_net $domain.switched_vdd -power_pin VDD derive_pg_connection -cells $always_on_tap_cells}foreach domain $domain-list { if it is a shutdown domain { always_on_tap_pg_connect $domain }}SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 10. In the second method, we define tap power connection by the ”-connect_power_name vdd” optionin add_tap_cell_array to get logic PG connections in the tap insertion. To resolve the issue thatboth always-on and switched VDD pins are connected to the switched-vdd net due to thecommand limitation that only one power connection is allowed, we disconnect the always-on pinconnections and reconnect them to the always-on power supply.proc always_on_tap_pg_connect {domain} { add_tap_cell_array -voltage_area $domain.voltage_area -connect_power_name $domain.switched_vdd … more options … disconnect_net $domain.switched_vdd $always_on_tap_VDDC_pins derive_pg_connection -cells $always_on_tap_cells -power_net vdd -power_pin VDDC}The first method decouples the logic PG connection from tap insertion. The issue of logic PGconnection due to the derive_pg_connection limitation is resolved by the multi-passworkaround. However, this method does not work in ICC 2010.12 release whereadd_tap_cell_array will perform logic connection regardless if the connect_power_nameoption is defined or not. Unfortunately, the connections are incorrect as both VDD and VDDCpins are connected to switched-vdd. The second method still works in ICC 2010.12 release, as itwill reconnect the incorrectly connected pin.7. Domain-based tap cell physical PG connection methodHaving resolved the issues in “logic” PG connections, we need to create the metal connections tothe tap cells for routing the power supplies. For a non-shutdown domain, this is not an issue, asthe PG pins of the normal taps are aligned with PG rails. The physical PG connections are donethrough rail connections at tap insertion. For the shutdown domains, always-on taps’ p-substratetap connection is still connected via rail connection. However, the always-on power physicalconnection to the taps’ VDDC pins requires custom power routes, because the VDDC pins arenot aligned to rails. Two methods are described below each has advantages and shortcomings.The first method leverages ICC feature of net mode PG routing using preroute_standard_cells. preroute_standard_cells -mode net -nets -port_filter_mode select -port_filter VDDC -cell_master_filter_mode select -cell_master_filter $always_on_tap_master_cell -h_width $tap_route_h_width -do_not_route_over_macrosIn the method, the VDDC pins of the always-on taps are routed to the always-on vertical strapsclose to the taps, as shown by the green horizontal routes in Fig. 5., by the net modepreroute_standard_cell.SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 11. Figure 5 – always-on tap pg routing method 1The default width of the route is the minimum metal width defined in the technology file. Sincetaps consume little current, the minimum width should be fine to satisfy IR-drop and EMconstraints provided no other cells were connected to the routes. If needed, the route width canbe change by the h_width option in preroute_standard_cell.The advantage of the method is that it is simple to implement. However, the net mode routesresult in noticeable routing resource usage due to metal routes of every tap pins to the verticalalways-on power straps, especially when the vertical straps are not close by. This shortcoming isovercome by the second method.In the second method, a custom always-on tap grid is built to leverage the always-on powerconnection at switch cell VDDC pins that are available next to the tap cells. The objective of themethod is to minimize power routing impact on signal routing. Taps VDDC pins are viaconnected to the lower layer vertical straps which connect at 6 rows internval to the switch cellVDDC pins to get always-on VDD supply. The pseudo-code of the method is described below.proc always_on_tap_pg_route {domain} { create vertical lower layer straps within domain voltage area attap pitch and aligned with the tap array columns foreach tap_array_column { foreach switch cell close to the tap_array_column { create a horizontal lower layer stub to connect the switchalways-on pin and vertical tap strap } }}SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 12. The clip in Fig. 6 illustrates the custom always-on tap physical connections of the method. Figure 6 – always-on tap pg routing method 2The advantage of the method is the low utilization of lower layer horizontal routing resourceswhich are valuable to signal routing. However, the method relies on the ability to leverageexisting always-on power routes at switch cells close-by. Therefore, it is not such a flexibleapproach as the first method. Moreover, the tap pitch might have to be adjusted to make the tapsaligned with the switch horizontal pitch to ensure short stub connections between the taps andthe switches.8. Off-grid tap insertion and power connectionsThe always-on tap physical PG connection methods described above take care of the tapsinserted in the regular tap grid. However, they do not handle well the off-grid taps such as thoseinserted in the narrow channels between macros. This issue has been resolved by the developedmethod that detects the off-grid always-on taps and creates additional custom physicalconnections to those taps.We detect the off-grid taps by checking the metal connections of taps’ VDDC pins, after tap gridcreation. Then, we sort the off-grid taps into column bins. For each column of the off-grid taps, avertical always-on power strap is added next to the column and the VDDC pins of the taps in thecolumn are connected to the strap by either the net mode preroute_standard_cell method orthe custom stub method described in the previous section. The method is outlined below.SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 13. proc detect_off_grid_always_on_taps { foreach tap $always_on_taps { if no metal strap at next layer over the VDDC pin of the tap { append the tap to collection off_grid_always_on_taps } } return $off_grid_always_on_taps}proc fix_off_grid_always_on_taps { set off_grid_taps [detect_off_grid_always_on_taps] set sorted_off_grid_taps [sort_collection $off_grid_tapsbbox_llx bbox_lly] foreach tap_column in $sorted_off_grid_taps { create vertical always-on strap next to the column } preroute_standard_cells -mode net -nets -port_filter_mode select -port_filter VDDC -cell_master_filter_mode select -cell_master_filter $always_on_tap_master_cell -h_width $tap_route_h_width -do_not_route_over_macros}9. ResultsThe methods described in the paper have been implemented in a UPF DC/ICC flow forproduction low-power design. Three chips have been successfully taped out using the UPF flow.To illustrate the methods, a small design was created which has an always-on domain at bottom-left corner and a shutdown domain which takes the rest of the design and in rectilinear shape.The domain-based tap insertion and PG grid generation methods were applied to the designtransparently as it has been integrated into the UPF flow and fully automated. The results areshown in Fig. 7. In the always-on domain, normal taps were selected and inserted. Simple cellrail connections completed the task of physical PG connections of the taps. In the shutdowndomain, the always-on taps were inserted at 60um pitch defined by the tap rule. A column of off-grid taps were inserted at a half tap pitch in the middle of the domain to satisfy the taprequirement in the standard cell region from right side of the always-on domain. The customalways-on tap grid method was used in this case to leverage existing always-on grids on theswitch cells. The vertical straps were correctly created over the all taps including the off-gridtaps. The horizontal stubs were also inserted connecting the vertical straps to the switch always-on power pins to get power supply to the taps.SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 14. Figure 7 – An example of domain based tap insertion and PG connection10. SummaryMost sub-65nm production SOC designs are implemented with tapless library cells for siliconarea efficiency. The tap cell insertion flow becomes complicated and risk-prone in power-gatingdesigns where always-on and shutdown blocks co-exist and different types of tap cells need to beimplemented in different domains accordingly. Furthermore, the logic and physical PGconnections of these tap cells becomes no longer straight forward and could result in chip failureif not implemented correctly. This paper addresses these challenges in the tapless power-gatingdesign by a domain-based tap insertion method and implementation techniques includingdomain-based tap type selection, always-on tap logic PG connection and PG grid generation, andoff-grid tap detection and fix. The method and implementation techniques have been integratedinto a UPF DC/ICC flow and have been used successfully in a number of production low-powerdesigns.SNUG 2011 Power Gating Design Implementation With Tapless Cells
  • 15. 11. ReferencesIC Compiler user manual.12. Author biographiesKaijian Shi is Principal Consultant in Synopsys Professional Services Group, specializing inlow-power design methodology and implementation. He has successfully completed more than14 commercial low-power designs. Dr. Shi co-authored the book “Low Power MethodologyManual for System-on-Chip Design”. He has published 53 papers in journals and internationalconferences. He also gave a number of talks and tutorials on low-power design methodologies.Dr. Shi holds a Ph.D. degree from University of Kent at Canterbury, UK since 1994. He wasChairman of IEEE Dallas Section in 2006 and Chairman of IEEE Circuits and System SocietyDallas Chapter in 2004. He was workshop chair and then publicity chair of IEEE SoCConference 2008-2011, program committee members of IEEE ISVLSI (2006-2008) andtechnical program track chair of DesignCon (2004-2008).David Tester has 15+ years of complex SOC, PMIC and RFIC experience in various hands-onsemiconductor development and executive management positions with Air, Symbionics,Conexant, LSI Logic and Dialog based both in the UK and US. He founded his first start-up Airin 2006 and delivered the first LBS optimized GPS receiver to market in 2009, having raised$10M of VC investment from Pond Ventures and built a world-class systems, silicon andsoftware team. His high volume, standard product, consumer IC background spans both digitaland analog silicon development – ranging from system level through semi-custom digital to full-custom analog and digital transistor level design. He has participated in the development of over20 semiconductor products for the location, wireless voice, wireless data, digital TV and PCgraphics markets. He holds a degree in Engineering from the University of Hull, UK. He is aFellow of the IET, a Senior Member of the IEEE and holds fifteen granted system, silicon andsoftware patents.SNUG 2011 Power Gating Design Implementation With Tapless Cells

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