NMI 2008 foils
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Air presentation at NMI verification workshop

Air presentation at NMI verification workshop

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NMI 2008 foils Presentation Transcript

  • 1. Low-Power Verification, the Way Functional + Physical Low-Power Silicon Verification David Tester, Founder & CTO 26 February 2009
  • 2. What are the Low-Power Verification Questions? How can you prove low-power silicon implementation of a system? Disruptive products demand system-level optimizations - Low-Power is no exception and requires … - Example: airwave1 and low-power GPS optimization - Today we will not discuss GPS or system verification! Let‟s consider an alternative question: “How did you prove (verify) the silicon implementation of that low power architecture? What are the challenges?” Here are five … not in order and not an exhaustive list … Q1. Lazy is OK. How do you know when you‟re done? Q2. Did you survive (or avoid) the pain a PMK can offer? Q3. How did you verify clock tree power consumption? Q4. Multi-DVDD chips – Where EDA meets reality … Q5. Is timing-optimized and power-optimized the same? … but first let‟s have an advert for
  • 3. GPS 101 Received Power is -130dBm (Maximum) … 20dB below Thermal Noise Floor! Earth radius 6 km 3578 6378 km m 0 0k Geo-stationary 191 Regional geo-stationary augmentation satellites km 20200 WAAS Wide Area Augmentation System – USA EGNOS 23222 km European Geostationary Navigation Overlay System – Europe GPS 6 orbital planes; 55° to equator Galileo Orbit 14 hours (approx) Moon Galileo 13300 km/h Approx. 400000 km 3 orbital planes; 56° to equator GLONASS GPS 3 orbital planes; 65° to equator Orbit 11 hours 58 minutes 13900 km/h GLONASS Orbit 11 hours 15 mins 14200 km/h
  • 4. GPS with airwave1 silicon
  • 5. The A Development Team Air Headcount: 23 people 10x Employee Development 9x Contract Development Hugh Thomas 4x Non-Development Staff CEO David Tester Andy Heaton Stephen Graham Co-Founder & CTO VP Operations & Development Co-Founder & VP Marketing RFIC Design System Design ASIC Design Software Design Staff Staff Staff Staff Employee #1 (20 years experience) Employee #3 (20 years experience) Employee #4 (10 years experience) Employee #7 (20 years experience) Employee #2 (20 years experience) Employee #1 (20 years experience) Employee #5 (15 years experience) Employee #8 (15 years experience) Employee #6 (15 years experience) Contract Contract Contract Contract #1 (15 years experience) Contract #3 (20 years experience) Contract #8 (20 years experience) Contract #2 (15 years experience) Contract #4 (20 years experience) Contract #9 (15 years experience) Contract #5 (20 years experience) 2x Synopsys IC layout contractors Board of Directors Support Staff Hugh Thomas CEO ex-CEO TapRoot 1x General Admin 1x Finance Manager David Tester CTO ex-CEO Andromedia (acquired Macromedia ‘99) Kent Godfrey Pond Ventures ex-CEO Frictionless Commerce (acquired SAP ‘06) Michael Gera Pond Ventures ex-CEO PortalPlayer (NASDAQ: PLAY) Gary Johnson Independent ex-CEO S3 (NASDAQ: SIII)
  • 6. History – Design, Verification, Schedule conflict Hugh Thomas CEO David Tester Andy Heaton Stephen Graham Co-Founder & CTO VP Operations & Development Co-Founder & VP Marketing RFIC Design System Design ASIC Design Software Design Staff Staff Staff Staff Employee #1 (20 years experience) Employee #3 (20 years experience) Employee #4 (10 years experience) Employee #7 (20 years experience) Employee #2 (20 years experience) Employee #1 (20 years experience) Employee #5 (15 years experience) Employee #8 (15 years experience) Employee #6 (15 years experience) Contract Contract Contract Contract #1 (15 years experience) Contract #3 (20 years experience) Contract #8 (20 years experience) Contract #2 (15 years experience) Contract #4 (20 years experience) Contract #9 (15 years experience) Contract #5 (20 years experience) Air tracks GPS satellites with RFIC 2x Synopsys IC layout contractors March „08 RFIC + FGPA platform May „08 Air tracks GPS satellites with RFIC + FPGA A1225 RFIC (v1) June „08 April „07 Air first PVT, confirms lab in Swindon June „08 A1225 RFIC (v2) A1250 single die GPS receiver February „08 January „09 J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D 2006 2007 2008 2009 J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D Electra Start-Up of the Year 2008 November „08 Gary Johnson joins Board of Directors 2x NASDAQ CEO (PortalPlayer & S3) IET Start-Up of the Year 2008 May „07 November '08 Prof Izzet Kale joins Technical Advisory Board October „08 Engage with TSMC for silicon Sept „06 Demonstrate GPS technology July „08 Development starts! June „06 Recruit external CEO May „08 Air Inc + Ltd incorporated May „06 Red Herring 100 Europe 2008 April „08 Series-A Termsheet April „06 Exit stealth mode Announce 1st product January „08
  • 7. Optimize for Power Everywhere, But Earlier is Better Low power algorithms more efficient (for hitting targets) than optimized circuits
  • 8. Quick Review on Where that Power is Consumed Dynamic (switching) and static (leakage) power from DVDD to DVSS Example circuit taken from: http://www.dti.unimi.it/~liberali/papers/c63.pdf
  • 9. When is “Low-Power” low enough? When to Stop? Products need to get to market … Stop when you‟ve verified it‟s good enough Can you spot the conflict between the following two statements? “I‟d like the lowest possible power consumption, please” “I‟d also like to get that product to market on time, please” Do you have a power budget? When should verification STOP ? Track and predict power performance at all levels of abstraction: - Architecture / Algorithm / System Partitioning - Pre-Synthesis RTL and Post-Synthesis Gates - Pre-Layout and Post-Layout “… but verification is never really complete…” True … what is the milestone for sufficient confidence that power meets budget?
  • 10. Less Complexity + Less Transitions = Lowest Power Reduce depth of logic between flip-flops and switching activity to minimise power How to verify switching activity level on budget? How to verify the original complexity assumptions?
  • 11. Routing Capacitance is the Enemy Parasitic capacitance (from routing) significantly alters switching power of logic How can you verify post-layout parasitic routing capacitance is acceptable?
  • 12. Power Management Kit ... Handle with Care! … rather like a chainsaw with all the safety features removed … - Standard cell library assumes single DVDD supply voltage - Power management library enables multiple voltage domains - Voltage domain control cells – DVDD and DVSS switch - P&R “optimisation” can pull cells from PMK library by mistake! - Can simulation identify these problems?… - Signal isolation cells (for crossing voltage domains) - Must verify P&R didn‟t “optimise” these! - PMK also adds more back-end DRC and LVS verification issues simulation can‟t solve…
  • 13. Multi-DVDD Silicon: Where EDA meets Reality … Circuit level functionality that needs to be verified at RTL level - DVDD functionality in “HEAD” and “FOOT” cells … but DVDD not represented in logic simulation! - How, and when, are cells instanced in the design? - Manually by logic designer or layout team? - Automatically by EDA tool? Do you trust it? - Yet another task to verify before tape-out !!! - Control signal active sense depends on cell used: - Active low for PMOS but active high for NMOS - Are control signal wired correctly? - How many cells for each domain? - “Power Aware” design flows try to plug the hole! Example: airwave1: 44x digital, 8x analog voltage domains
  • 14. “Custom” Cells rather than “Standard” Cells? „Optimized for Power‟ and „Optimized for Timing‟ are not always compatible - Knowledge of “use” offer options for power optimized gates - Power optimized and timing optimized are not always the same Example - Custom flip-flop used in airwave1 datapath - Relaxed timing enabled >40% power improvement!
  • 15. What‟s Your Methodology to Verify the Clock Tree? Not all clock tree‟s are low power … - Power depends on conflicting constraints: skew, rise time, load, etc - CTS tools build functional but over-designed, high-power clock trees - Can‟t verify power until P&R started ... but is that too late for market? - Clock tree can pass functional verification but fail power verification! Example: airwave1: 400+ clock domains More a clock forest than a clock tree ...
  • 16. Post-Placement Optimization? Roll the Dice Again! Development on-schedule and on-budget? P&R “optimization” can solve that… “Here‟s the final netlist, it meets the power spec‟s and just needs to go through P&R” - Pre-Layout gate level power estimates are estimates - Routing capacitance impacts both timing and power - P&R optimization resizes gates to close timing … almost certainly ignoring circuit power … so power estimates on pre-P&R netlist are exactly that - estimates Verification Issue: How to verify post-layout power still hits the target specification … … and hit your schedule
  • 17. Validation of Software Power against Power Budget After the HW / SW partitioning is done, does the software hit it‟s power budget? How to Estimate Software Power ?... (… since hardware power is under control) - CPU power consumed with vendor „example‟ code - Actual power with real code in real environment? Example Issues: Cache RAM v Main RAM power executing code Does any firmware exist yet that can be profiled?
  • 18. “Blind Faith and Ignorance” or “Informed Decision”? Don‟t forget to be paranoid about power, if you care about power Low-Power can be broken anywhere: - Architecture - Hardware (RTL) or Software - Logic Synthesis - P&R and CTS - Cell library and macros choices - Process technology Each step demands differing levels of verification activity, but verification of power needs more than just logic simulation and must include power budgets, circuit simulation and … application of brain power …