IEEE SOCC 2011 paper
by David Tester, VP Silicon Engineering at Structured Custom on Sep 29, 2011
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65nm and beyond CMOS designs are commonly...
65nm and beyond CMOS designs are commonly
implemented with “tapless” library cells which do not
provide built-in n-well or substrate taps, improving cell
density. This cell efficiency results in additional layout
complexity for power-gating designs. Three well
tapping methods are described for production powergating
designs considering design schedule, leakage
power, chip area and complexity.
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