Time Borrowing And Clock Skew


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Time Borrowing And Clock Skew

  1. 1. SUBMITTED BY:-Sarbjeet SinghECE Regular 2011Roll No. 616NITTTR CHD5/10/2013 3:59 AM 1PRESENTED BY Sarbjeet Singh
  2. 2. ObjectiveTime BorrowingClock SkewIEEE PAPERResultsConclusions5/10/2013 3:59 AM 2Sarbjeet Singh
  3. 3. Time Borrowing• In a flop-based system:Data launches on one rising edgeMust setup before next rising edgeIf it arrives late, system failsIf it arrives early, time is wastedFlops have hard edges• In a latch-based systemData can pass through latch while transparentLong cycle of logic can borrow time into nextAs long as each loop completes in one cycle5/10/2013 3:59 AM 3PRESENTED BY Sarbjeet Singh
  4. 4. Time Borrowing ExampleLatchLatchLatchCombinational LogicCombinationalLogicBorrowing time acrosshalf-cycle boundaryBorrowing time acrosspipeline stage boundary(a)(b)LatchLatchCombinational LogicCombinationalLogicLoops may borrow time internally but must complete within the cycle121 11225/10/2013 3:59 AM 4PRESENTED BY Sarbjeet Singh
  5. 5. How Much Borrowing?Q1L112L21 2Combinational Logic 1Q2D1 D2D2TcTc/2Nominal Half-Cycle 1 Delaytborrowtnonoverlaptsetupborrow setup nonoverlap2cTt t t2-Phase Latchesborrow setuppwt t tPulsed Latches5/10/2013 3:59 AM 5PRESENTED BY Sarbjeet Singh
  6. 6. Clock DistributionClockCannot really distributeclock instantaneouslywith a perfectly regularperiod5/10/2013 3:59 AM 6PRESENTED BY Sarbjeet Singh
  7. 7. Clock Skew: Spatial Clock VariationClock SkewDifference in clockarrival time at twospatially distinctpointsABABSkewCompressed timingpath5/10/2013 3:59 AM 7PRESENTED BY Sarbjeet Singh
  8. 8. Clock SkewWe have assumed zero clock skewClocks really have uncertainty in arrival timeo Decreases maximum propagation delayo Increases minimum contamination delayo Decreases time borrowing5/10/2013 3:59 AM 8PRESENTED BY Sarbjeet Singh
  9. 9. Review: Skew ImpactF1F2clkclk clkCombinational LogicTcQ1 D2Q1D2tskewCLQ1D2F1clkQ1F2clkD2clktskewtsetuptpcqtpdqtcdtholdtccqsetup skewsequencing overheadhold skewpd c pcqcd ccqt T t t tt t t t• Ideally full cycle isavailable for work• Skew adds sequencingoverhead• Increases hold time too5/10/2013 3:59 AM 9PRESENTED BY Sarbjeet Singh
  10. 10. Skew: LatchesQ1L112L2L31 12CombinationalLogic 1CombinationalLogic 2Q2 Q3D1 D2 D3sequencing overhead1 2 hold nonoverlap skewborrow setup nonoverlap skew2,2pd c pdqcd cd ccqct T tt t t t t tTt t t t2-Phase Latchessetup skewsequencing overheadhold skewborrow setup skewmax ,pd c pdq pcq pwcd pw ccqpwt T t t t t tt t t t tt t t tPulsed Latches5/10/2013 3:59 AM 10PRESENTED BY Sarbjeet Singh
  11. 11. 11Skew ToleranceFlip-flops are sensitive to skew because ofhard edgesData launches at latest rising edge of clockMust setup before earliest next rising edge ofclockOverhead would shrink if we can soften edgeLatches tolerate moderate amounts of skewData can arrive anytime latch is transparent5/10/2013 3:59 AM PRESENTED BY Sarbjeet Singh
  12. 12. 12Solutions• Reduce clock skew– Careful clock distribution network design– Plenty of metal wiring resources• Analyze clock skew– Only budget actual, not worst case skews– Local vs. global skew budgets• Tolerate clock skew– Choose circuit structures insensitive to skew• Post-fabrication adjustment– Intel, IBM, etc5/10/2013 3:59 AM PRESENTED BY Sarbjeet Singh
  13. 13. Quan Yuan , Hai-gang Yang , Fang-yuanDong , Tao Yin, “Time BorrowingTechnique for Design of Low-PowerHigh-Speed Multi-Modulus Prescalerin Frequency Synthesizer” ,IEEEInternational Symposium on Digital ObjectIdentifier, pp. 1004 - 1007, 18-21 May 2008.5/10/2013 3:59 AM 13PRESENTED BY Sarbjeet SinghIEEE PAPER
  14. 14. Abstract A low power continuous phase-switching multimodulusprescaler is proposed, based on a “time-borrowing” method. In this phase-switching control strategy significantly reducesthe delay of the phase-switching control loop so the multi-modulus prescaler can work with higher input frequencies andobtain the maximum modulus for a lower power supply. Such a multi-modulus prescaler fabricated in a 0.35μm CMOSprocess divides the 2.4GHz input frequency by 48 up to 64 fora minimum power supply voltage of 2.5V. Its maximum power dissipation is only 4.85mW.5/10/2013 3:59 AM 14PRESENTED BY Sarbjeet Singh
  15. 15. Existing Prescaler ModelFirst5/10/2013 3:59 AM 15PRESENTED BY Sarbjeet Singh
  16. 16. • The problem with this prescaler is that ,the VCO of a frequencysynthesizer is estimated to typically consume more than 50% of thetotal PLL power. Second• The asynchronous prescaler is based on the phase-switchingtechnique.5/10/2013 3:59 AM 16PRESENTED BY Sarbjeet Singh
  17. 17. • It has two divide-by-2 stages in cascade and onlythe first divide-by-2 flip-flop operates at thehighest input frequency.• But , it may suffer from unwanted glitches.5/10/2013 3:59 AM 17PRESENTED BY GURPARTAP SINGH
  18. 18. • To remove the glitches, a re-timer circuit is addedto properly synchronize the input signals of thephase switching block, which unfortunatelyincreases the circuit complexity and henceconsumes more power and area.5/10/2013 3:59 AM 18PRESENTED BY Sarbjeet Singh
  19. 19. Proposed Multi-Modulus Prescaler• The proposed continuous phase-switching multi-modulus prescaler with the“time borrowing” method• The idea is to prepare some intermediate signals in advance before the nextphase is selected.• The delay of the whole phase switching control loop TLOOP = TAND +TCON + TSEL .• The pulse-generator and the four divide-by-2 stages are parts of the phase-switching control loop, but their delay do not appear in the TLOOP.• This is done through use of the low-level part of the current phase in thephase-switching output signal (F4).• Thus, the delay time over the phase-switching control loop can beminimized so the control signals (CON) would quickly become available.5/10/2013 3:59 AM 19PRESENTED BY Sarbjeet Singh
  20. 20. 5/10/2013 3:59 AM 20PRESENTED BY Sarbjeet Singh
  21. 21. 5/10/2013 3:59 AM 21PRESENTED BY Sarbjeet Singh
  22. 22. 5/10/2013 3:59 AM 22PRESENTED BY Sarbjeet Singh
  23. 23. Divide-By-25/10/2013 3:59 AM 23PRESENTED BY Sarbjeet Singh
  24. 24. Phase Controller5/10/2013 3:59 AM 24PRESENTED BY Sarbjeet Singh
  25. 25. Phase selector5/10/2013 3:59 AM 25PRESENTED BY Sarbjeet Singh
  26. 26. Pulse Generator5/10/2013 3:59 AM 26PRESENTED BY Sarbjeet Singh
  27. 27. 5/10/2013 3:59 AM 27PRESENTED BY Sarbjeet Singh
  28. 28. 5/10/2013 3:59 AM 28PRESENTED BY Sarbjeet Singh
  29. 29. 5/10/2013 3:59 AM 29PRESENTED BY Sarbjeet Singh
  30. 30. 5/10/2013 3:59 AM 30PRESENTED BY Sarbjeet Singh
  31. 31. Layout5/10/2013 3:59 AM 31PRESENTED BY Sarbjeet Singh
  32. 32. 5/10/2013 3:59 AM 32PRESENTED BY Sarbjeet Singh
  33. 33. Results5/10/2013 3:59 AM 33PRESENTED BY Sarbjeet Singh
  34. 34. 5/10/2013 3:59 AM 34PRESENTED BY Sarbjeet Singh
  35. 35. ConclusionsThe delay of the phaseswitching control loopcan be reduced significantly.Prescaler works at a frequency up to 2.4GHz ata 2.5V supply with the division range of 48-64and its maximum power dissipation is only4.85mW. Our design has demonstrated a considerableimprovement in terms of the power-to-speedratio.5/10/2013 3:59 AM 35PRESENTED BY Sarbjeet Singh
  36. 36. Refferences A. Wafa and A. Ahmed, “High-Speed RF Multi-ModulusPrescaler Architecture for Fractional-N PLL FrequencySynthesizers,” 2004 IEEE International Symposium onCircuits and Systems (ISCAS 2004), pp. 241-244, May2004. Quan Yuan , Hai-gang Yang , Fang-yuan Dong , Tao Yin,“Time Borrowing Technique for Design of Low-PowerHigh-Speed Multi-Modulus Prescaler in FrequencySynthesizer ” ,IEEE International Symposium on DigitalObject Identifier, pp. 1004 - 1007, 18-21 May 2008. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=13293475/10/2013 3:59 AM 36PRESENTED BY Sarbjeet Singh
  37. 37. ???Qus5/10/2013 3:59 AM 37PRESENTED BY Sarbjeet Singh
  38. 38. Thankyou5/10/2013 3:59 AM 38PRESENTED BY Sarbjeet Singh