1
2
3
4
5
6
7
8
9
DC/DC 1--1------'
PCB
Level
Obstacle
System
Reset
IC1
1- - - BOUNDARY REGISTER - - - 1
I I - - INIT-DATA REGISTER I
I I
...
10
11
12
13
Boundory - scon r eg i s t er~--~
Device 1dent1 f ico tlon
r a 1star
D ~sig n spec ifl c
test do t o r e isler
Design s...
14
setTDI u1.mbist-csr start
setTDI u1.alg walk1
drscan
runtest 10000
set result [getTDO status]
If {$result != pass}
puts...
15
Core1 Core2
Core3Core4
POD
# vendor supplied reg to temp conversion
proc Reg2Temp { $regval $CorF } {
…
}
# this proc r...
16
HDL
EMS
17
18
• ICGS&A
• IC Design
• IC Package
• IC Test
• EcoSystem Test
System Design
Assem, Purch,
etc
19
•Changing temp
• Std. FR4, multi-IC signals
•Commodity LDOs, DC/DC
• Tin Can Osc, System origin clocks
•JTAG assisted F...
20
TEST
DEBUG
CONFIGURATION
With 1149.1/JTAG
1 11 11111 1 , , t
········-·-'Hi;;;;~::;;=;.......,_,_
---.
21
IP
Block
TDR
22
23
24
25
26
27
28
29
IP
Block
TDR
30
31
BIST
TAP
TDR Register
Logic
block
IC
IC
32
P1
PRBS
TAP
33
HSIO
Test
IP
BLOCK
IC2
Far
End
Loopback
34
IP
BLOCKIC2
IC1
TAP
TAP
35
HDL
EMS
36
37
2.5V
INPUT ( Open0)
INPUT (Open1)
OUTPUT2
Bidir with Pull0
Bidir with Pull0
A
B
C
D
Control
Bidir with Pull0 Obstacle
I...
38
D
+
-
MODE=1
VDD
HSIO
GND
39
BER
XMIT
BER
RCVR
40
IC1
A
B
C
D
POWER_POS
DC/DC
Converter
3.3V
POWER_0
IC2
LINKAGE_IN
LINKAGE_IN
LINKAGE_IN
LINKAGE_IN
VREF_IN
DC/DC
Conver...
41
linkage_in
Linkage_huffer
linkage_mechanical
vref in
Tef out
power_O
power_pos
power_neg
A non-houncl11J1 scan analog i...
42
43
BSDL for Internal JTAG TDR registers
- for BIST/PLLs/SERDES IP blocks
MNEMONICS for JTAG registers
- Easy to remember w...
44
IC_RESET
45
IC_RESET Objectives
Cause an on-chip reset to occur via TAP
- emulate functionality of system reset pin
Isolate on-chip...
46
TRST* (if present)
TAP POR* (if present)
RESET* •,--<>~~..-­
0
(from TAP) Update stages
Domain 'N' Domain 1
ShifUCaptur...
47
48
49
PCB
Level
Obstacle
Logic
BIST
Memory
BIST
System
Reset
Voltage
Monitor
SysReset
PCB
Level
Obstacle
IC1
BOUNDARY REGISTE...
50
Mode ._-------------~
(From TAP)
Reset*
(from TAP)
>--- -e CH-Mode
(to B-reg)
>----------. CH-Reset*
I Test Mode Persis...
51
G1
G1
0
1
1D
C1
1D
C1
To next cell Mode
ClockDR UpdateDR
ShiftDR
1
0 To System
Logic
52
INIT_SETUP/INIT_RUN
53
INIT_SETUP & INIT_RUN
54
New standard INIT_DATA
55
Descriptions of I/O can be built into hierarchical blocks
56
TypeC.BSDLTypeC.BSDL
U1
PCIe
U2
SRIO
U3 U4
iProc init_setup {} {
iWrite IO1 PCIe
iApply
}
iProc init_setup {} {
iWrite ...
57
58
TOR bit I
I
.---~~-,__._________s_o"1?' To next bit
Shift_<TOR>
ShiftTdrBit
I
ClR Q
Capture_<TOR>
captureTdrBit
ClR Q
U...
59
1-------- - -- I
I I
1---1 D SET Q ~-s_o_;l. To next bit
tdr_cap I
PI
Shift <TOR> ~-__J
ShiftTdrBit
Capture_<TOR> ..___...
60
Sl
From last bit
r------------------------.1TORb1t I
I o
I I so
To next bitI
I '--tiiJ-- - - - - - ' '-----:-!• Pulse1 ...
61
Values associated with register bit
CAPTURES | DEFAULT | SAFE | RESETVAL
Type of cell:
NOPI | NOPO | NOUPD | MON
| PULS...
62
1- - - BOUNDARY REGISTER - - - 1
I I - - INIT·DATA REGISTER - -, I
I I
1 I Register Segmentation and
L Power domain con...
63
"Ready to scan"
TPI
~ s1 c .......s_o__.....
(Pou
Segment-
selector
Excludable Segment - f
Cell
TOR>~.-----------~
Shif...
64
TPI
~ s1 c so s1 C t-so___-1
Excludable Segment -~
~~--~--~-----
(POU (POU
Domain- .,, Segment-
control selector
Cell C...
65
BSDL keywords allow one to describe DOMAIN, or if externally powered,
DOMAIN_EXTERNAL and SEGSEL (SEGSTART) and SEGMUX ...
66

 Mission mode
1149.1
Gating
Logic
HOMI
Power
Controller
USB OTG
67
attribute REGISTER_ASSEMBLY of PwrDomStruc : entity IS
"Reg1 ( "&
"(hdmi_pwr IS DomCtrl Domain(D1) CHReset), "&
"(micro...
68
"Reg2 ( "&
"(hdmi_sel IS SegSel Domain(D1) CHReset), "&
"(hdmi IS hdmi_seg), "&
"(hdmi_mux IS SegMux), "&
"(usb_otg_sel...
69
TYPEA and TYPES BSDL
...
use STD_1149_1_2012.all
use MEMB.all
BSDL Package LIB
STD_1149_1_2012.pac
MEMB.pac
POL LIB
MEM...
70
71
Basic Register Fields
attribute REGISTER_FIELDS of INIT_Example :
entity is
"init_data ( "&
"(Clock[5] IS (504 DOWNTO 5...
72
REGISTER_MNEMONICS
attribute REGISTER_MNEMONICS of SERDES :
package is
" Protocol ( “ &
" OFF (0b000) <I/Os powered dow...
73
Basic Register Fields with Mnemonics
attribute REGISTER_FIELDS of INIT_Example : entity is
"init_data ( "&
"(Clock[5] I...
74
PROTOCOL1 (10) OFF 0000000000 0000000000
PROTOCOL2 (10) OFF ii oooo1ooooQI 0000100000......
SRIOSlJING(2) 00 00
POE~
PL...
75
Device PDL (Procedure Definition Language) - Board specific
Proc init_setup {} {
iWrite Clock F125Mhz # use of mnemonic...
76
Some PDL Commands
iWrite <reg> <value> | mnemonic
iRead <reg> <expected> | mnemonic
iApply # perform DR scan RTI-RTI
iP...
77
iPrefix U1 # U1.LBIST
# run some basic tests on registers
iWrite LBIST RUN # bit-position independent regs
iApply
iRunL...
78
3 SERDES with init_data Registers
Common PLL
BSDL with package files allows
Hierachical access to pre-defined
Registers...
79
PACKAGE XYZ_IO IS
USE Std_1149_1_2012.all;
attribute REGISTER_MNEMONICS of XYZ_IO : package IS
"SerDes_Protocol (off (0...
80
attribute REGISTER_FIELDS of XYZ_IO : package IS
"Channel [5] ( "&
"Protocol[3] (2, 0, 1) IS DEFAULT (SerDes_Protocol (...
81
Register assembly – bits predefined defined – length calculated by BSDL reader
Use XYZ_IO.all;
Use XYZ_PLL.all;
-- stuf...
82
attribute REGISTER_PORT_ASSOCIATION ("&
"SerDes00_PRBS (SD_RX(0), SD_RX_B(0), SD_TX(0), SD_TX_B(0)),"&
"SerDes01 (SD_RX...
83
84
85
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IEEE 1149.1-2013 Addresses Challenges in Test Re-Use from IP to IC to Systems

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IEEE 1149.1-2013 Addresses Challenges in Test Re-Use from IP to IC to Systems by C.J. Clark at the the IEEE VLSI Test Symposium 2012.

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IEEE 1149.1-2013 Addresses Challenges in Test Re-Use from IP to IC to Systems

  1. 1. 1
  2. 2. 2
  3. 3. 3
  4. 4. 4
  5. 5. 5
  6. 6. 6
  7. 7. 7
  8. 8. 8
  9. 9. 9 DC/DC 1--1------' PCB Level Obstacle System Reset IC1 1- - - BOUNDARY REGISTER - - - 1 I I - - INIT-DATA REGISTER I I I 1 Register Segmentation and L I _ ~ower domain control I t:. - - - - - -=..-=..-=..-=..-=.. I I I I I r - 1 1 r--- I I I I I I I I I I I I I BIST
  10. 10. 10
  11. 11. 11
  12. 12. 12
  13. 13. 13 Boundory - scon r eg i s t er~--~ Device 1dent1 f ico tlon r a 1star D ~sig n spec ifl c test do t o r e isler Design s pecific test do l o r e i sler N iClock ond control sfgno ls froM i ns truc tion reg ister , TAP controller . etc . Figure 9·1- An implementation of the group of test data registers 0 0 ......
  14. 14. 14 setTDI u1.mbist-csr start setTDI u1.alg walk1 drscan runtest 10000 set result [getTDO status] If {$result != pass} puts “memorybist failed”
  15. 15. 15 Core1 Core2 Core3Core4 POD # vendor supplied reg to temp conversion proc Reg2Temp { $regval $CorF } { … } # this proc returns a temperature and # high level warnings could be specified iProc -export init-setup-temp-check { } { iRead tempreg iApply set val [iGet tempreg] # convert reg value to temperature in Celsius set temp [Reg2Temp $val CEL] if {$temp > 70} { puts "Temperature is excessive $temp" } return $temp }
  16. 16. 16 HDL EMS
  17. 17. 17
  18. 18. 18 • ICGS&A • IC Design • IC Package • IC Test • EcoSystem Test System Design Assem, Purch, etc
  19. 19. 19 •Changing temp • Std. FR4, multi-IC signals •Commodity LDOs, DC/DC • Tin Can Osc, System origin clocks •JTAG assisted Functional/BIST •Stable temperature •50ohm ZT DUT card design, dedicated • Low noise Power, DC/DC converters • Perfect Low jitter, 50/50 duty clocks • BIST/Compression vectors, delay test On-Chip test via IEEE 1149.1 - the lowest common denominator
  20. 20. 20 TEST DEBUG CONFIGURATION With 1149.1/JTAG 1 11 11111 1 , , t ········-·-'Hi;;;;~::;;=;.......,_,_ ---.
  21. 21. 21 IP Block TDR
  22. 22. 22
  23. 23. 23
  24. 24. 24
  25. 25. 25
  26. 26. 26
  27. 27. 27
  28. 28. 28
  29. 29. 29 IP Block TDR
  30. 30. 30
  31. 31. 31 BIST TAP TDR Register Logic block IC IC
  32. 32. 32 P1 PRBS TAP
  33. 33. 33 HSIO Test IP BLOCK IC2 Far End Loopback
  34. 34. 34 IP BLOCKIC2 IC1 TAP TAP
  35. 35. 35 HDL EMS
  36. 36. 36
  37. 37. 37 2.5V INPUT ( Open0) INPUT (Open1) OUTPUT2 Bidir with Pull0 Bidir with Pull0 A B C D Control Bidir with Pull0 Obstacle INPUT ( PULL1) POWER_POS1.8V
  38. 38. 38 D + - MODE=1 VDD HSIO GND
  39. 39. 39 BER XMIT BER RCVR
  40. 40. 40 IC1 A B C D POWER_POS DC/DC Converter 3.3V POWER_0 IC2 LINKAGE_IN LINKAGE_IN LINKAGE_IN LINKAGE_IN VREF_IN DC/DC Converter 2.5V VREF_OUT INPUT INPUT BIDIR BIDIR BIDIR BIDIR
  41. 41. 41 linkage_in Linkage_huffer linkage_mechanical vref in Tef out power_O power_pos power_neg A non-houncl11J1 scan analog input that does not source or sink A non-boundary scan analog port capable ofsourcing/sinking Slgnificant current"' but does. not have a disable method. A non-electrical port used for positioning, heat sinks or other non- electrica] use. Til.ere is no connection to the · silicon. A :non-boundary s.can wput reference voltage port A non-boundary s.ca:n output reference voltage port Zero volt Ports. These are ports which are nom1aUy associated 1i.tb GROUND. Ke)'~'ord GROUND or GIXD is notused here in order to leave these 'Of~ for signalnames. Power supply ports which receiYe a cons1ant potential with rec:,pect to 0 that i~ than zero Yobs. Power supply port~ which reoei·e a constant potential with res.Jlect to ower 0 that i~ less than zero volts.
  42. 42. 42
  43. 43. 43 BSDL for Internal JTAG TDR registers - for BIST/PLLs/SERDES IP blocks MNEMONICS for JTAG registers - Easy to remember words Package files for on-chip Infrastructure IP blocks - self-contained definitions for IIP PDL Script files for device initialization and IIP access - operates on registers, packages, Mnemonics
  44. 44. 44 IC_RESET
  45. 45. 45 IC_RESET Objectives Cause an on-chip reset to occur via TAP - emulate functionality of system reset pin Isolate on-chip logic from external system reset affects Enable control of on-chip POR resets in non-I/O domains Prevent loss of reset isolation/control when TAP enters Test-Logic-Reset State
  46. 46. 46 TRST* (if present) TAP POR* (if present) RESET* •,--<>~~..-­ 0 (from TAP) Update stages Domain 'N' Domain 1 ShifUCapture stages TDI - • • • I B A B A L _ _ _ j L _ _ _ _j L _ _ _ _j Additional domains for additional reset pins A) Reset-enable bit Reset-Hold Bit B) Reset-control bit Update is reset separately from the rest of the register
  47. 47. 47
  48. 48. 48
  49. 49. 49 PCB Level Obstacle Logic BIST Memory BIST System Reset Voltage Monitor SysReset PCB Level Obstacle IC1 BOUNDARY REGISTER TAP INIT-DATA REGISTER IR & Decode & Muxing BIST Failure Data For ATE User Defined Chain(s) DACADC 0 1 PLL 0 1 On-chip Reset via TAP PRBS Protocol Swing CMMV ECID Unique ID AC/DC
  50. 50. 50 Mode ._-------------~ (From TAP) Reset* (from TAP) >--- -e CH-Mode (to B-reg) >----------. CH-Reset* I Test Mode Persistence Controller I Clamp_Hold_Decodea------1 J---1 D SET Q Clamp_Release_Decode a-----1 TCK a----------- CLR Q
  51. 51. 51 G1 G1 0 1 1D C1 1D C1 To next cell Mode ClockDR UpdateDR ShiftDR 1 0 To System Logic
  52. 52. 52 INIT_SETUP/INIT_RUN
  53. 53. 53 INIT_SETUP & INIT_RUN
  54. 54. 54 New standard INIT_DATA
  55. 55. 55 Descriptions of I/O can be built into hierarchical blocks
  56. 56. 56 TypeC.BSDLTypeC.BSDL U1 PCIe U2 SRIO U3 U4 iProc init_setup {} { iWrite IO1 PCIe iApply } iProc init_setup {} { iWrite IO1 SRIO iApply } IO1 IO1 U3.PDL U4.PDL Board.PDL iCall U3.init_setup iCall U4.init_setup Board Test Engineer Developed via Software or from Templates from IC Vendor Board Test Engineer Developed via Board Test Software, Automatically, assisted or manually Why can’t I/O settings be delivered in BSDL?
  57. 57. 57
  58. 58. 58 TOR bit I I .---~~-,__._________s_o"1?' To next bit Shift_<TOR> ShiftTdrBit I ClR Q Capture_<TOR> captureTdrBit ClR Q Update_<TOR> UpdateTdrBit I I TCK ~---------..~-~ I I I I II --------------- IReset*_<TOR> T -------- _____ ------- ------
  59. 59. 59 1-------- - -- I I I 1---1 D SET Q ~-s_o_;l. To next bit tdr_cap I PI Shift <TOR> ~-__J ShiftTdrBit Capture_<TOR> ..________J CaptureTdrBit TCK ~--------___J I CLR Q : I I I 1 -- ~ PO I I I TOR bit I
  60. 60. 60 Sl From last bit r------------------------.1TORb1t I I o I I so To next bitI I '--tiiJ-- - - - - - ' '-----:-!• Pulse1 PO Shift <TOR> ....._-=S.,.....,hift=TdrBit CLR Q Capture_<TOR> -.+---=c==-a-p,-tu-re-=T,...,.dr-=B~it CLR Q Update- <TOR> ...,__,.U..,....p--:d---=at,......,eT=-d..,..,rB"""'i,....t ----J ' - - - - - - -- - -- - - - - - - - ' - - - - - - - - ' CLR Q TCK ~----------.----------------------J'---------' ~------ Reset* ......____________________________________.________________,~ I I I I I I I I TCK ---fl-n--- ---fl-n--- Update_<TOR> ~I ~I SO (scan data) - -1- 4 - t - ~ - - - 1- -1 - t - 1- - PO - - 1- ~- +- ~- ~I ~ I : : 7 I Monitor I I No Pulse (SO=O) Pulse (80 =1)
  61. 61. 61 Values associated with register bit CAPTURES | DEFAULT | SAFE | RESETVAL Type of cell: NOPI | NOPO | NOUPD | MON | PULSE0 | PULSE1 | SHARED Reset (if present) : PORRESET | TRSTRESET | TAPRESET | CHRESET
  62. 62. 62 1- - - BOUNDARY REGISTER - - - 1 I I - - INIT·DATA REGISTER - -, I I I 1 I Register Segmentation and L Power domain control - - - - - - - DC/DC 1-1----l I ~ ----===~~~~ .._____;_,.............~-~ mp_Hold instruction keeps 1/0 static during. • I tests PCB level Obstacle __I • • • .. I I I I I I ----1I :.---- 1 I I I L l-r.,.......~ •I I ••••••I I l----------- : On-chip : 1 ---r- Reset via 1 1.------ •• • . ... • : I .. II ··~-~- TAP : : Memory I I BIST .---- .........~...+IIIII.......~ I I System Reset SysReset IC1 •• • I t--r-.,.......~-1 ••••••••• I I 11111 IR& Decode & Muxing TAP I I I =...-=...-.:.. J PCB level Obstacle ur1 U:)D
  63. 63. 63 "Ready to scan" TPI ~ s1 c .......s_o__..... (Pou Segment- selector Excludable Segment - f Cell TOR>~.-----------~ Shift <TOR> ~a------------' TOR>~.-----------~ ....,..
  64. 64. 64 TPI ~ s1 c so s1 C t-so___-1 Excludable Segment -~ ~~--~--~----- (POU (POU Domain- .,, Segment- control selector Cell Cell Capture_<TOR> ~.,...._________. Shift_<TOR> ~.,....__________, date <TOR> ~....,______________, "",
  65. 65. 65 BSDL keywords allow one to describe DOMAIN, or if externally powered, DOMAIN_EXTERNAL and SEGSEL (SEGSTART) and SEGMUX (SEGEND) <association type>::= DOMAIN | DOMAIN_EXTERNAL | SEGSEL | SEGMUX <association name>::= <VHDL identifier>
  66. 66. 66 Mission mode 1149.1 Gating Logic HOMI Power Controller USB OTG
  67. 67. 67 attribute REGISTER_ASSEMBLY of PwrDomStruc : entity IS "Reg1 ( "& "(hdmi_pwr IS DomCtrl Domain(D1) CHReset), "& "(micro_sd_pwr IS DomCtrl Domain(D2) CHReset), "& "(usbotg_pwr IS DomCtrl Domain(D3) CHReset), "& "(micro_sd_sel IS SegSel Domain(D2) Segment(S2) CHReset)), "&
  68. 68. 68 "Reg2 ( "& "(hdmi_sel IS SegSel Domain(D1) CHReset), "& "(hdmi IS hdmi_seg), "& "(hdmi_mux IS SegMux), "& "(usb_otg_sel IS SegSel Domain(D3) CHReset), "& "(usb_otg IS usb_otg_seg), "& "(usb_otg_mux IS SegMux), "& "(SerDes_sel IS SegSel Domain_External(D4) CHReset), "& "(SerDes IS SerDes_seg), "& "(SerDes_mux IS SegMux), "& "(micro_sd_start IS SegStart Segment(S2)), "& "(micro_sd IS microsd_seg), "& "(micro_sd_mux IS SegMux) )"; Attribute Register_Port_Association of PwrDomStruc : entity is "SerDes sel : (Ext Pwr pin) "; -- See next clause.
  69. 69. 69 TYPEA and TYPES BSDL ... use STD_1149_1_2012.all use MEMB.all BSDL Package LIB STD_1149_1_2012.pac MEMB.pac POL LIB MEMB.PDL SERDBIST.PDL
  70. 70. 70
  71. 71. 71 Basic Register Fields attribute REGISTER_FIELDS of INIT_Example : entity is "init_data ( "& "(Clock[5] IS (504 DOWNTO 500) ), "& "(Voltage[2] IS ( 101 DOWNTO 100) ) "& ");" BSDL syntax for “INIT_DATA” and For Clause 9 user defined TDRs
  72. 72. 72 REGISTER_MNEMONICS attribute REGISTER_MNEMONICS of SERDES : package is " Protocol ( “ & " OFF (0b000) <I/Os powered down>, "& " PCIe (0b001) <PCI Express>, "& " SATA (0b010) <SATA>, "& " SRIO (0b011) <Serial RapidIO>, "& " XAUI (0b100) <XAUI>, "& " Rsvd1 (0b101) <Undefined, do not use>"& )," & "Voltage ( " & " 500MV (b00), "& " 800MV (b01), "& "1400MV (b10) <Do not use!>)";
  73. 73. 73 Basic Register Fields with Mnemonics attribute REGISTER_FIELDS of INIT_Example : entity is "init_data ( "& "(Clock[5] IS (504 DOWNTO 500) Default(Clockset(100Mhz) ), "& "(Protocol[3] IS (302 DOWNTO 300) Default(Protocol (off) ), "& "(Voltage[2] IS ( 101 DOWNTO 100) RESETVAL(11) ), "& "(Reserved [20] IS ( 19 DOWNTO 0))"& ")" & “myTDR ( "& "(Addr[64] IS (163 DOWNTO 100) ), "& “(Data[64] IS (227 DOWNTO 164) ), "& “(WE[1] IS (228) RESETVAL(1) ), "& “(TempMON[7] IS (236 DOWNTO 229)) "& );” Sparse definitions compared to register length User Defined TDR
  74. 74. 74 PROTOCOL1 (10) OFF 0000000000 0000000000 PROTOCOL2 (10) OFF ii oooo1ooooQI 0000100000...... SRIOSlJING(2) 00 00 POE~ PLL(2) X6.UI 1.0 101· ~ CAl·IB IST (2) STOP 00 00 CKMSTATUS(2) 00 10 10 1 LBIST(2) RUN 00 00 LBISTSTATUS ( 1) 0 PASS PASS II HODESTATUS(1) 0 0 ST.ATUS 1 ( 1) 0 PASS
  75. 75. 75 Device PDL (Procedure Definition Language) - Board specific Proc init_setup {} { iWrite Clock F125Mhz # use of mnemonics iWrite Voltage 800MV iWrite Protocol PCIe iApply } Proc init_status {} { iRead Status(1) Pass # use of mnemonics iApply }
  76. 76. 76 Some PDL Commands iWrite <reg> <value> | mnemonic iRead <reg> <expected> | mnemonic iApply # perform DR scan RTI-RTI iPrefix <dotted path> # iPrefix bank0.serdes iReset # Test Logic Reset iEndState RTI | PDR # set end state iRunloop <TCK-Count> # Loop in RTI iCall <iproc name>
  77. 77. 77 iPrefix U1 # U1.LBIST # run some basic tests on registers iWrite LBIST RUN # bit-position independent regs iApply iRunLoop 300000 iRead LBISTSTATUS PASS # check that LBIST passed iApply iWrite SWING S400MV # set differential Swing to 400mv iWrite PROTOCOL1 SRIO # set protocol to SRIO iApply iWrite CAMBIST RUN # execute CAM BIST iApply iRead CAMSTATUS DONE
  78. 78. 78 3 SERDES with init_data Registers Common PLL BSDL with package files allows Hierachical access to pre-defined RegistersExtra Bit
  79. 79. 79 PACKAGE XYZ_IO IS USE Std_1149_1_2012.all; attribute REGISTER_MNEMONICS of XYZ_IO : package IS "SerDes_Protocol (off (000) <Powered down>, "& " PCIe (001) <PCIExpress>, "& " SATA (010) <SATA>, "& " SRIO (011) <Serial RapidIO>, "& " XAUI (101) <XAUI>, "& " Resvd1 (11X) <Undefined - Do Not Use>), "& "SerDes_TX_Outputs (off (00) <Powered down>, "& -- Output driver swing level " Full_Swing (01) <100% Swing>, "& " Swing_p75 (10) <75% Swing>, "& " Swing_p527 (11) <52.7% Swing Not legal if XAUI is protocol>), "&
  80. 80. 80 attribute REGISTER_FIELDS of XYZ_IO : package IS "Channel [5] ( "& "Protocol[3] (2, 0, 1) IS DEFAULT (SerDes_Protocol (PCIe)) "& “ RESETVAL(SerDes_Protocol (off)), "& "TX_Swing [2] (3, 4) IS DEFAULT (SerDes_TX_Outputs (off)) "& "), "& END XYZ_IO; ----------------------------------------------------------------------------- --- PACKAGE BODY XYZ_IO IS USE Std_1149_1_2012.all; END XYZ_IO; Package File Cont’d
  81. 81. 81 Register assembly – bits predefined defined – length calculated by BSDL reader Use XYZ_IO.all; Use XYZ_PLL.all; -- stuff removed for brevity attribute REGISTER_ASSEMBLY of INIT_Example : entity is "init_data ( "& “ (USING XYZ_PLL), “ & “ ( P1 is Settings), “ & “ ( USING XYZ_IO ), “ & “( Array SerDes(1 TO 2) is Channel), “ & “( dummy[1] ), “ & “( SerDes( 0) is Channel ), “ & “( reserved[105] )“ & ");“ SERDES SERDESSERDESRsrvdTDI TDOPLL
  82. 82. 82 attribute REGISTER_PORT_ASSOCIATION ("& "SerDes00_PRBS (SD_RX(0), SD_RX_B(0), SD_TX(0), SD_TX_B(0)),"& "SerDes01 (SD_RX(1), SD_RX_B(1), SD_TX(1), SD_TX_B(1)) “;
  83. 83. 83
  84. 84. 84
  85. 85. 85

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