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Snug2007 Presentation
 

Snug2007 Presentation

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User experience of DesignWare Virtual Platforms

User experience of DesignWare Virtual Platforms

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    Snug2007 Presentation Snug2007 Presentation Presentation Transcript

    • System Level Verification - A case analysis with Virtio (DesignWare ™ Virtual Platforms) Kal yan Chakravadhanula ASIC Design Engineer Texas Instruments, San Diego Platform Validation Engineer
    • Purpose
      • Avoid a potential re-spin of silicon (~ $1Mil)
      • Design validation of Software Development Platforms (SDP)
      • Accelerate software development cycle
      • Reduce the post-silicon bench time
    • Outline
      • Introduction
      • Where do we fit?
      • DesignWare ™ Virtual Platforms
      • Software Development Flow
      • Results
    • Introduction
      • Chip today
        • No! Yesterday
      • Focus on Chip Design
      • Customer requirements changing
        • Prove System Level Functionality
        • Using chassis (hardware board)
        • Software / Firmware Drivers that run on the chip
      • How about validation of this hardware board and Software / Firmware drivers?
        • DesignWare ™ Virtual Platform
    • Where do we fit?
      • Pre-silicon Development
        • Existing development platforms
        • FPGA Platforms
        • DesignWare ™ Virtual Platforms
      Software team Hardware team
    • OMAPV2230
      • Multi-core (two ARMs, & two DSPs )
      • Security (M-Shield)
      • Complex On-Chip OCP
      • USB
      • I2C
      • Mobile DDR
      • Flash
      • SD/MMC Slot
      • USIM
      • LCD
      • Keypad
      • Bluetooth
      • WLAN
      • Software Model of a complete embedded platform
        • Mirror the functionality of an embedded system
      • Combine high-speed processor instruction set and fully functional TLM of hardware building block
        • Provide high level hardware model to software developer
      • Created using two specification languages
        • Magic-C : semi-visual language which creates peripherals as FSMs in graphical form
        • Virtual platform Runtime Environment (VRE) C/C++ is used to model components that require high simulation speed and have no FSM
      DesignWare ™ Virtual Platforms Background
    • DesignWare ™ Virtual Platforms Background Board-level System IO Mem Simulation Infrastructure Fast Instruction-set Simulators Transaction-level Interfaces High-speed C++ Models Graphical Magic-C FSM Models User Interface Emulation Virtual I/O System-on-Chip Func Peripherals Virtual I/O & User Interface CPU Instruction -accurate ISS Func TLM Bus Func TLM Bus
    • DesignWare ™ Virtual Platforms Compelling Features
      • Integration with third party software development tools
        • Code Composer Studio (CCS), TI tool, also available externally
          • Strong debug capabilities for ARM & DSP
          • Build & download code onto mDDR (hardware board)
      • Multi-core support & synchronous debugging
        • A halt on one processor halts other processors
      • Virtual I/O Support
        • UART (COM port), Ethernet & USB
      • Fast access to components / parameters / properties
    • DesignWare ™ Virtual Platforms VPOM-V2230 Virtual Platform VPOM-V2230 (Virtual Platform) Cockpit (Virtual Platform) Code Composer Studio (Multi-core Debugger)
    • DesignWare ™ Virtual Platforms Software Development Tasks
      • Boot code of ARM11 and ARM9 cores
      • UART device drivers
      • Flash burning
      • Boot from flash
      • I2C device drivers
    • DesignWare ™ Virtual Platforms Benefits
      • Accelerated quality chip design
        • Feedback from software engineers on hardware architecture
      • Concurrent software development
      • Continuous HW/SW integration
      • Extra level of Visibility & Controllability
        • 2-5x improvement in software development productivity (compared to that over hardware boards)
    • DesignWare ™ Virtual Platforms Requirements & Learning Period
      • Requirements for DesignWare Virtual Platform & CCStudio
        • High-end Personal Computer
          • 3 GHz processor, 2GB RAM
      • Learning Period
        • Initial Apprehensiveness
        • Included the functional specification of the chip and the DW VP
        • One month
      • Software Installation
        • Uninstall the existing release prior to installing a new version
        • Windows based
          • Fixed now: selective availability on Linux
      • Discouraged installation of multiple platforms on a single PC
        • Fixed now
      DesignWare ™ Virtual Platforms Problems & Minor Issues Resolved Resolved
    • Software Development Flow Chip Design Prototype Silicon Manufacturing Development Board Design Board Mounting time Virtual Platform Development Firmware Develop. Firmware Debug Device Driver Development Firmware Debug Device Driver Development Software Development & Debug Start (traditional approach) Software Development & Debug Start (VP Approach) Time-to-Market Gain
      • Highlight different CPUs in different background colors
        • Easy to get confused between Platform and CPUs
      • Provide Options to End User
        • Switch between Functional to Cycle accurate simulator
        • Stop processing the script if there is an error
        • Not save virtual hardware breakpoints in Magic-C graphical hardware description
      • Provide software models of modem test equipment
        • Ability to make phone call using software base-station
      DesignWare Virtual Platforms Recommended Improvements
    • Results
      • Firmware Development
        • Four months ahead of silicon availability!
      • Early Validation of Software Drivers
        • Reduction of post-silicon bench time by two months
        • Earlier time-to-market
      • Bug detection in Library Code
      • Software changes from Virtual Platform to Hardware board
        • NONE!
      • Avoid a potential silicon respin
        • ~ $1 million
    • Acknowledgements
      • James Turnbull (Texas Instruments)
      • Filip Thoen, Kevin Smart (Synopsys)
      • SNUG
      • You’ll