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Presentation Impact2009

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My works on advanced semiconductor packaging.

My works on advanced semiconductor packaging.

Published in: Technology, Business

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  • 1. A Novel High Performance Substrate and the Processes Thereof Chih Kuang Yang chihkuang.yang@gmail.com All right reserved.
  • 2. Agenda  Technology Trend and Target  Review of Substrate Technology  Novel Process of Substrate  Performance of Substrate  Summary All right reserved.
  • 3. Technology Roadmap  ITRS-2009 target  Bump pitch to 110um  Via diameter to 50um  Line/Spece to 15um  Dielectric layer thickness to 35um All right reserved.
  • 4. Technology Roadmap  Jisso Technology Roadmap  Via land diameter to 60um  Line/Spece to 7um All right reserved.
  • 5. Routing Density- Requirement  SCP vs. SiP Mother Board Substrate Die Substrate Die All right reserved.
  • 6. Routing Density- Requirement  A complete system in a packaging  Side by side SiP  Less limitation on the source of chips  Easy to realize SiP for every company All right reserved.
  • 7. Routing Density- Requirement  For SCP  Fanning out centrifugally  High density area focus on the areas of bump grid array  Less categories of power  Ordinary requirement of routing density All right reserved.
  • 8. Routing Density- Requirement  For SiP  Minimum routing length between chips  High density routing required among all areas of chips  Various categories of power  Harsh requirement of routing density All right reserved.
  • 9. Routing Density- Surface Layer  Substrate bond pad layer  The size of metal traces is the key point of routing density  Areas of bond pads occupies routing areas, limits routing density All right reserved.
  • 10. Routing Density- Inner Layer  Substrate inner layer  Via land has large influence to routing density  For less than 110um Bump pitch, Via land occupied too much routing areas in present technology  We target on 30um Via land All right reserved.
  • 11. Routing Density- Requirement  We challenge technology limitation for a new era of SiP  Via land for less than 60um, metal trace for less than 10um  For higher integration of SiP, present roadmap can not meet the requirements  Wholly new process is necessary! All right reserved.
  • 12. Evolution- Via Drilling  Mechanical  Limited to 100um Via  CO2 Laser  Limited to 50um Via  UV Laser  Limited to 20um Via All right reserved.
  • 13. Evolution- Via Land  +/-50 um overlay accuracy with 20um Via =120 um Via land  +/-30 um overlay accuracy with 20um Via =80 um Via land  +/-20 um overlay accuracy with 20um Via =60 um Via land  Next? All right reserved.
  • 14. Novel Process- Temporary Carrier  Temporary carrier for a process tool  Easy for extremely precise alignment and ultra-thin substrate process  Up to +/-5um overlay accuracy!  Temporary carrier can be recycled All right reserved.
  • 15. Benefit of ultra small Via land  For +/-5um with 20um Via =30um Via land  Fanning out 3 rows bump grid array in 16um-line  Fanning out 8 rows bump grid array in 5um-line  For 60um Via land, Fanning out only 5 rows bump grid array in 5um- line  Small Via land fanning out finer pitch area grid array All right reserved.
  • 16. Metal trace- novel process  Metal lift-off process  Simple process, only Photoresist patterning 3 steps  Precise  Fine line Metal deposition  Low roughness of metal line Photoresist All right reserved. removing
  • 17. Metal trace- achievement  5um/5um line/space  Up to 7 um thickness  Aspect ratio 1.4:1 All right reserved.
  • 18. Dielectric layer thickness – Cross talk  Cross talk of 2 microstrip line  Shorter space, larger crosstalk  Thinner dielectric layer, less crosstalk  Higher routing density requires thinner dielectric layer All right reserved.
  • 19. Dielectric layer thickness – Impedance  Z0  Control constant impedance  Smaller line width, larger impedance  Thinner dielectric layer, less impedance  Higher routing density requires thinner dielectric layer All right reserved.
  • 20. Dielectric layer-thickness and flexibility  By temporary carrier process, ultra-thin dielectric layer can be done!  1 dielectric layer is just 8 um-thick  8-layer substrate is just 90um-thick All right reserved.
  • 21. Flexibility- 1-Layer Trace  3-Layer Test Pattern in 40μm Thick  30μm Trace  MIT Bending Tester  ±90 Degrees Bending  1 mm Radius of Curvature >100,000 Times All right reserved.
  • 22. Flexibility- 2-Layer VIA Series  3-Layer Test Pattern in 40μm Thick  20μm VIA Series  MIT Bending Tester  ±90 Degrees Bending  1 mm Radius of Curvature >100,000 Times All right reserved.
  • 23. Reliability  85℃/85﹪ RH, 1000 Hour  Electro-migration Test>1 GΩ  30 μm /30 μm Line & Space Interdigital Pattern  Series of VIA No Obvious Change All right reserved.
  • 24. System demonstration  System in one packaging  Android platform  Video & Audio  Touch panel  Ethernet All right reserved.
  • 25. System in one packaging  ARM-926EJS CPU  DRAM 128Mb *4  NOR flash 64Mb  Audio codec  Touch Panel controller  RS232 tranceiver  Ethernet PHY All right reserved.
  • 26. System in one packaging  39mm*39mm  5 flip chips  Total 18 IC  4 connectors  278 SMD passives  Totally 2042 bond pads.  8-layer substrate All right reserved.
  • 27. Summary  Substrate technology roadmap need to be renewed for future SiP  A novel technology of substrate was introduced  SiOP(System in one packaging) was realized by a novel substrate technology  Side by side SiP has wide chip sources, easily realized for every companies  SiP technology should not limit the source of chips All right reserved.