Jeda Hls Hlv Success Story V4

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Jeda Hls Hlv Success Story V4

  1. 1. Accelerate Your HLS Flow with High Level Verification (HLV) Tool Suite<br />The Next Level of RTL Verification<br />
  2. 2. 2<br />HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc <br />Why HLV ?<br />You are using High Level synthesis <br />To achieve faster time to RTL<br />But still verify HLS block at RTL?<br />Move verification automation to high level also<br />To achieve true faster time to market<br />
  3. 3. 3<br />HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc <br />A SoC Design with HLS BlocksVideo Example<br />CPU<br />(Video Configuration)<br />External <br />Memory<br />Blocks from HLS<br />
  4. 4. Customer’s Old Verification Flow<br />SystemC/ANSI-C Model<br />Enter Verification Process at RTL:<br />1. Task: Identify not tested RTL code<br /><ul><li> User Task: Improve testbench</li></ul>2. Task: Identify dead (not used) code in RTL<br />Sometimes inserted by Synthesis tool? <br /><ul><li>User Task: Change synthesis script or improve synthesis tool</li></ul>Often inserted by user in SystemC/ANSI-C code<br /><ul><li>User Task: Trace back RTL to SystemC/ANSI-C code and remove code from SystemC/ANSI-C model</li></ul>testbench<br />Enter <br />verification <br />process here<br />Synthesize<br />RTL Model<br />Re-use testbench<br />Problem: Fast time to RTL but slow <br />RTL Verification<br />Measure code<br />and functional <br />data coverage<br />
  5. 5. New Verification Flow with JEDA<br />Enter <br />verification <br />process here<br />Enter Verification Process at SystemC/ANSI-C<br />1. Task: Identify not tested SystemC/ANSI-C code<br />Benefit: <br /><ul><li>Improve C-testbench earlier with C model
  6. 6. Improve C-testbench faster with 10-100x faster C-models
  7. 7. Re-use C-testbench</li></ul>2. Task: Identify dead (not used) Code in SystemC/ANSI-C<br />Benefit: <br /><ul><li>Identify dead code in SystemC/ANSI-C code directly. Do not need to trace back dead code in RTL to dead code in SystemC</li></ul> Fast time to RTL and fast time to verified RTL<br />SystemC/ANSI-C Model<br />testbench<br />Measure code<br />and functional <br />data coverage<br />Synthesize<br />RTL Model<br />Re-use testbench<br />
  8. 8. C Source Code Coverage Tools<br />Approach:<br />Measure coverage in SystemC/ANSI-C model with C-Source code coverage tools<br />Customer results<br />85-90% not-hardware aware coverage in SystemC/ANSI-C model <br /> BUT<br />25-30% detailed coverage in RTL model<br /><ul><li>No reliable results at SystemC/ANSI-C level, because result does not carry into RTL code</li></li></ul><li>JEDA Hardware-Aware Coverage Tools <br />Approach:<br />Measure coverage with JEDA Tools <br /> More detailed analysis in the hardware-aware coverage measurement, predicting concurrent HW in the RTL<br />Customer results<br />85-90% Hardware-aware coverage in SystemC model<br />AND<br />85-90% coverage in RTL model<br /><ul><li>Reliable results, because coverage results carry into the RTL model
  9. 9. Fast way to RTL + efficient verification</li></li></ul><li>8<br />HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc <br />JEDA- Model Validation Solution<br />JEDA TLM 2.0 <br />Validation Suite<br />JEDA Validation <br />Tools Suite<br />JEDA OCP <br />Validation Suite<br />TLM2.0-ITG:<br />Traffic Generation<br />OCP-ITG:<br />Traffic Generation<br />ITG:<br />sequence generator, traffic templates<br />Generation<br />TLM2checker:<br />TLM2.0Compliance Checks<br />OCPchecker:<br />OCP Compliance Checks<br />NSCa:<br />Native SystemC Assertion <br />across TLM multiple levels<br />Self-checking<br />OCPcov: <br />Transaction Coverage<br />JEDADC: <br />Data/Functional Coverage<br />JEDACC: <br />Hardware-aware Code Coverage<br />Model <br />Validation IP<br />Measurement<br />

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