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Track h tools for improving design productivity - altera

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  • 1. Tools for Improving design productivity
    Elhanan Sharon
    Embedded Technology Specialist
    ALTERA Department
  • 2. Agenda
    FPGA Design challenges
    Improving Productivity – What it Means?
    Introduction to QSys – ALTERA System Integration tool
  • 3. System Design Challenges with FPGAs
    Number of
    system
    components
    in an FPGA
    • Increasing FPGA density
    • 4. Growing FPGA I/O capabilities
    • 5. FPGA becoming the heart of the system
    Time
    Time spent on system integration
    • The time spent integratingeach additional componentincreases exponentially
    Number of system components in an FPGA
  • 6. Productivity Challenge for FPGA Designers
    Spend significant amount of time on system integration
    Core competency is innovation and product differentiation
    System integration
    Innovation
    Product
    differentiation
  • 7. Improving Productivity- What It Means ?
    Do more with less—more complex products with same or less resources
    Reuse across projects—avoid obsolescence
    Reuse across locations
    Lower risk—avoid “throw-away”
    Reduce risk of design errors
    Reduce risk of market changes
    Reduce risk of schedule slips
    Allow customers to focus on their value-added core competencies
  • 8. Tools to Improve Customer Productivity
    As FPGAs move to the heart of the system, design software plays a key role in defining customer productivity
    ALTERA Design Suite software tools leads the industry in several important areas
    Compilation time
    Timing analysis and Timing closure
    Power optimization and Power closure
    Team-based design methodology
    System-level design tools
    System Integration tools
  • 9. Introduction to Qsys:System Integration Made Easy
  • 10. Why Use System Integration Tools like Qsys?
    Simplifies complex system development
    Provides a standard platform supporting many IP cores
    Enables design re-use
    Raises the level of abstraction
    Allows developers to focus on “value add” instead of glue logic and system interconnect
    Scales easily to meet the needs of the end product
    Reduces time to market
    Reduces design development time
    Less error-prone
    Eases verification
  • 11. Qsys Foundation: SOPC Builder
    SOPC Builder’s track record
    Enjoyed ~10 years of success
    Used by 10,000+ users worldwide
    • Trends in customer requirements:
    • 12. Higher system bandwidth and increasing usage of high-performance IP cores
    • 13. Growing system size requiring very scalable development tool
    • 14. Shorter time to market and limited resources demanding a system re-use flow
  • Qsys Raises the Level of Design Abstraction
    Higher Abstraction and Improved Productivity Level
    Low
    Medium
    High
    System
    Block
    IP
    System
    Block
    IP
    System
    Block
    Block
    IP
    IP
    System
    System
    Design Block Integration
    IP Integration
    • Design a system with IP cores
    • 15. IP re-use
    • 16. IP verification
    SoC Integration
    • Design a system with systems
    • 17. System re-use
    • 18. System verification
    Schematic Entry Tool
    SOPC Builder Tool
    Qsys System Integration Tool
  • 19. Qsys: Moving To The Next Level
    Based on Network-on-chip Architecture
    High Performance Interconnect
    Hierarchy
    IP Management
    Package as IP
    Add toLibrary
    (Design Reuse)
    Design
    System
    Real-time System Debug
    • High performance interconnect
    • 20. Hierarchy
    • 21. Industry-standard interfaces
    • 22. IP management capabilities
    • 23. Real-time system debug
    SOPCBuilder
    +
    =
    Industry-standard Interfaces
  • 24. Qsys Features
    High performance: New interconnect based on network-on-chip architecture
    Scalable systems: Hierarchical system design
    Industry-standard interfaces: Connect IP cores of different interfaces together (Avalon, AXI, AHB, etc.)
    Design re-use: IP management capabilities
    Faster board bring-up: Real-time system debug
  • 25. Easy-to-Use System Integration UI
    Library of
    available IP
    Connect IP and systems
    IP 1
    IP 2
    IP 3
    System 1
    System 2
    Design at a Higher Level of Abstraction by
    Integrating IPs and Systems
  • 32. med
    low
    high
    off
    High Performance Interconnect
    SOPC Builder
    Qsys
    Manual Pipelining
    Manual Pipelining
    System Interconnect Fabric
    Higher Performance
    QsysInterconnect
    (Based on Network-on-chip
    Architecture)
  • 33. High Efficiency Interconnect
    25% Efficiency at Slave
    Width Adaptor
    Burst Adaptor
    Master
    Slave
    32
    128
    Burst count = 8
    Burst Count = 1
    100% Efficiency at Slave
    Width Adaptor
    Burst Adaptor
    Master
    Slave
    32
    128
    Burst Count = 8
    Burst Count = 1
    Bandwidth Available for Other Masters
    Higher Efficiency = Higher Throughput
  • 35. Network-on-Chip (NoC) Architecture
    Packet transactions and transport
    Each command encapsulated in a packet to be sent to a slave
    Each response encapsulated in a packet to be sent back to a master
    Avalon-ST
    Avalon-MM
    Avalon-MM
    Master
    Network
    Interface
    Slave
    Network
    Interface
    Avalon ST
    Network
    (Command)
    Slave
    Interface
    Master
    Interface
    Master
    Network
    Interface
    Avalon ST
    Network
    (Response)
    Slave
    Network
    Interface
    Slave
    Interface
    Master
    Interface
    Transport Layer
    Transaction Layer
    Transaction Layer
  • 36. Scalable System Design: Hierarchy
    SOPC Builder
    Qsys
    Sub-system 1
    Sub-system 2
    Sub-system 3
    Qsys advantage: hierarchy support
    • Fewer components = fast GUI
    • 37. Fewer components = manageable
    • 38. Enables system to scale
    Impacts on large systems:
    • GUI response
    • 39. System management
  • Industry-standard Interfaces
    Mix industry-standard interfaces together
    Master
    1
    Slave
    1
    AXI
    OCP
    Master
    2
    Slave
    2
    OCP
    AXI
    Master
    3
    Slave
    3
    Avalon
    Avalon
    Qsys Interconnect
    P
    P
    P
    P
    P
    P
    A
    A
    A
    A
    A
    A
    C
    C
    C
    C
    C
    C
    K
    K
    K
    K
    K
    K
    E
    E
    E
    E
    E
    E
    AMBA
    T
    T
    T
    T
    T
    T
    OCP
    OC
    Qsys: Avalon (10.1), AXI (2011)
  • 40. Design Re-use
    Project A
    Project B
    Project C
    Top
    Top
    Top
    Qsys enables re-use of IP and systems with IP management capabilities
    Top
    Top
    Add to Library
    Package as IP
    • IP GUI wizard
    • 41. System Top
    Qsys
  • 42. Faster Board Bring-up
    Access the system in real time by sending read/write transactions through a bridge IP
    FPGA Design
    View Data
    in Real Time
    A
    Bridge
    IP
    • JTAG Bridge IP
    • 43. SPI Bridge IP
    • 44. TCP/IP Bridge IP
    C
    B
    D
    Read/Write Transactions
    Faster Board Bring-up with Real-TimeSystem Debug
  • 45. Vision: Target Qsys Applications
    Qsys can be used in every FPGA design
    Control plane
    Reading and writing to control status registers
    Data plane
    Data switching (muxing, demuxing), aggregation, bridges
  • 46. Summary
    Qsys increases design productivity through automated interconnect generation
    Faster design cycles
    Less design errors
    Easier verification
    Shorter time to market
    Qsys new features include:
    High performance interconnect with pipelinedNetwork-On-Chip architecture
    Scalable system design with hierarchy support
    Broad IP portfolio availability with industry-standard interfaces
    Design re-use with IP management capabilites
    Faster board bring-up with real-time debug capabilities

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