ASIC PROTOYPING ON FPGA<br />Zvi Goldenberg  	<br />Engineer at Intel <br />Senior Lecturer at Logtel <br />May 4, 2011<br />
Methodology and Challenges<br />Very few code modifications<br />Compromise readiness <br />Identifying our customer ! (sw...
Methodology and Challenges<br />Lower system clocks (flow control may be used)<br />Reduce design & synthesis cycle times<...
Clock tree modification<br />
Simplifying clock tree<br /> Use FPGA PLL/MMCM by coregen<br /> Instantiate BUFG/BUFGCE/BUFGMUX <br /> Delete test mode cl...
System partitioning<br />Try to locate FF  at I/O pads <br />    (otherwise, in/out pad delay will reduce  <br />    drama...
System partitioning<br />Inter-connection pins : <br />ddr/qdr/serdes may be added between  units to save pins <br />Tip :...
Reviewing reports<br />Do I have slacks ?<br />Are all pins located ?<br />Are all pins got drive level + correct standard...
Reviewing reports<br /> Do I have local clocks with large skew ?   <br /> Did the tool understand my timing   exceptions ?...
Reviewing reports<br />I changed only version number  <br />  and design stopped working !!! <br />Possible reasons :<br />
FPGA editor usage<br />Invert input signal<br />DCM /PLL Phase shift adjustment(manual calibration)<br />Add pullup/down t...
Synthesis warning example<br />case 0<br />case 1 …<br />case 9    <br />case 0<br />case 11..<br />case 19<br />Warning :...
BUG example<br />
TX RACE<br />Inactive state must be ‘1’ (held by pull-up)<br />when oen ↓ (close tx buffer) , input 1 of AND gate is drive...
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Track h asic prototyping - logtel

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Track h asic prototyping - logtel

  1. 1. ASIC PROTOYPING ON FPGA<br />Zvi Goldenberg <br />Engineer at Intel <br />Senior Lecturer at Logtel <br />May 4, 2011<br />
  2. 2. Methodology and Challenges<br />Very few code modifications<br />Compromise readiness <br />Identifying our customer ! (sw, design, be )<br />Define priorities – what is covered well by verification team ?<br />Should I verify external IP’s ?<br />Good system partition<br />
  3. 3. Methodology and Challenges<br />Lower system clocks (flow control may be used)<br />Reduce design & synthesis cycle times<br /> (use compile point, FPGA editor etc.)<br />
  4. 4. Clock tree modification<br />
  5. 5. Simplifying clock tree<br /> Use FPGA PLL/MMCM by coregen<br /> Instantiate BUFG/BUFGCE/BUFGMUX <br /> Delete test mode clocking <br /> Use “fix gated clock” carefully <br /> Consider bypass clock gaters<br /> Refer to “gated clock” warning <br />
  6. 6. System partitioning<br />Try to locate FF at I/O pads <br /> (otherwise, in/out pad delay will reduce <br /> dramatically system performance)<br />To save pin count: connect DDR/QDR/serdes between units (Adds latency , check if possible)<br />Usually , phase of 2 FPGA’s must be equal Use PLL carefully to adjust Assign clk_FPGA_1_to_FPGA_2 = sys_clk_FPGA_1 won’t work – why ? Cont…<br />
  7. 7. System partitioning<br />Inter-connection pins : <br />ddr/qdr/serdes may be added between units to save pins <br />Tip : consider GTX serdes connection between 2 <br /> FPGA’s . This will enable system expansion.<br />Tip : connect _gc pins from FPGA-1 to FPGA_2 to eliminate parasitic input delay on clock pins.<br />
  8. 8. Reviewing reports<br />Do I have slacks ?<br />Are all pins located ?<br />Are all pins got drive level + correct standard ? <br />Did I constraint all clocks ? Answer: Run trce with –u<br />Did I constrained all I/O’s offset ? - Same<br />Do I understand all clock tree ? Search for derived clocks Cont…<br />
  9. 9. Reviewing reports<br /> Do I have local clocks with large skew ? <br /> Did the tool understand my timing exceptions ?<br /> What is sampling window of main interfaces ?<br />Answers can be found in .twr + .par + .csv reports<br />Cont…<br />
  10. 10. Reviewing reports<br />I changed only version number <br /> and design stopped working !!! <br />Possible reasons :<br />
  11. 11. FPGA editor usage<br />Invert input signal<br />DCM /PLL Phase shift adjustment(manual calibration)<br />Add pullup/down to pad<br />Change drive level <br />Change init value of FF/RAM<br />Change logic equation of LUT<br />add probes <br />
  12. 12. Synthesis warning example<br />case 0<br />case 1 …<br />case 9 <br />case 0<br />case 11..<br />case 19<br />Warning : case repetition <br />
  13. 13. BUG example<br />
  14. 14. TX RACE<br />Inactive state must be ‘1’ (held by pull-up)<br />when oen ↓ (close tx buffer) , input 1 of AND gate is driven to 0 >> data out_pad ==0<br />300 ps later buffer is closed >> data ↑ by <br />pull-up (very slowly)<br />Result : glitch detected by RX logic !!!!!!!!<br />Found in Customer site <br />

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