May 1, 2013IP Content Growing Rapidly• IP: Represents 60% -70%+ oftoday’s SoC content• 90%+ in the near future?• SoC differentiated by value-added content
May 1, 2013It’s the System That Counts• Performance and low power are key metrics … but,• System reliability and robustness is critical!• Poor reliability leads to– Poor sales / no profits/ doomed product line
May 1, 2013Variation – 2 Flavors• Static variations– Due to imperfect manufacturing– No two devices exactly alike• Dynamic variations– Due to fluctuations in system environment and operatingconditions• Temp / Voltage / Application
May 1, 2013System Design Challenges• No two components behave exactly alike– SoC– Package– PCB– Discretes• System operating environmentsmay vary widelySystem variation is difficult or impossible to predict in advance!
May 1, 2013Other Considerations• The SoC may be targeted for multiple systemsand applicationsSystemCompany 1SystemCompany 2SystemCompany n
May 1, 2013Adaptive IP• Concept of adaptive IP– Each system is unique– IP adapts itself for optimal performance andstability in context of the system• Requirements– Must improve system stability and yield– Must be self-contained and automatic– Cannot degrade system performance
May 1, 2013Adaptive IP Example• DDR subsystem– Often highest speedinterface in system– Failure or instability =inoperative system• SoC spends majority oftime accessing DDRDDRxSDRAMSoCPCBStorage70% - 80%~ 20%Other Peripherals~ 10%
May 1, 2013DDR Challenge• Clock domain crossing problem on reads is toughestproblem– Latency (from read cmd to read data)– Phase relationship (between DQS and System Clk)• Typical solution is to bench test many parts and find asolution that works– Time consuming / cannot predict all possible behaviors
May 1, 2013Applying Adaptive IP• Adaptive “self-calibrating logic” added to DDR PHY• Precisely measures round-trip read timing “in-situ”– Adjusts DDR timing interface– At power-on and during system operationRound Trip Timing Solved!
May 1, 2013Key Benefits – Adaptive IP• Better system reliability– Mitigates both static and dynamic variations• Increases system performance• Improves device yield• Drastically reduces system bring up time