May 1, 2013 10FPGA prototyping challengesMay 1, 2013• Design Size• FPGA partitioning• Logic trimming• Si to FPGA conversion• Frequency• Clock tree (gates, switches)• Development cycle• Long synthesis time• Poor visibility• FPGA set of tools
May 1, 2013 11Big Box Emulator prototypingchallengesMay 1, 2013• Cost : ~ 10X [FPGA cost per gate]• Speed: usually slower than FPGAs• Mobility: Heavy and require vast labinfrastructure.
May 1, 2013 12Leveraging both techniquesMay 1, 2013
May 1, 2013 13The ramp-up vehicleMay 1, 2013• FPGA prototype initial ramp up takesmuch time: compilation, synthesis, timingconvergence, debugUse the Emulator to bring up the FPGA modelRamp-up ~3-5X faster
May 1, 2013 15The satellite conceptMay 1, 2013• FPGA prototypes areaffordable. they arepart of SW/FW/SVdevelopment platformSVSVSW SWSWFWFWFWEMEMSWSWRTLRTLSWSWBig boxemulatorSW,SV,FWDevelopmentDebugOnce bugs are found, debug with EmulatorOnce reproduced – 5x faster debug
May 1, 2013 16Complete Full Chip prototypingMay 1, 2013• FPGAs prototypes provide most of the logicbut not all of it.• Main reasons are their limited capacity;difficulty in imitating clock tree and limitedconnectivity between FPGAs use Emulator to prototype the entire ASIC.
May 1, 2013 17RTL ModelsMay 1, 2013Silicon RTLFPGA RTL for FPGAboxFPGA RTL forEmulatorSilicon RTL forEmulator
May 1, 2013 18ResultsMay 1, 2013• Initial ramp up took 10 days• Emulator speed = 0.25X FPGA-box speed• Emulator compilation of FC = 0.2X of FPGA• Visibility = entire design for ~400K cycles• 80% of bugs found over FPGA were successfullyreproduced, debugged and solved over the Emulator• Average time invested in solving issues over Emulatoris ~5X shorter than over FPGA estimate
May 1, 2013 19SummaryMay 1, 2013• The combination provides apowerful solution which leveragesboth Emulator and FPGA strengths• Automation in moving from onemodel type to the other is a key tothis technique
May 1, 2013 20For additional questions:May 1, 2013• Emulation: Ilan Harel(email@example.com)• Emulation: Leonid Yuhananov(firstname.lastname@example.org)• Acceleration: Stas Cherkassky(email@example.com)
May 1, 2013 22Special forces development vehicleMay 1, 2013• BIST pattern development• GLS• PHY emulation
May 1, 2013 23Intel Confidential- Internal Use OnlyDifferentiation: 3 types of emulators•Commercial “black box” Emulators:•Can accommodate large designs (currently ~5M100M+ gates)•Low-level details of emulator HW design (FPGA/routing) is hidden from users: “Black box”•All required tools/flow provided by the single emulator vendor•Speed: 100Khz-1Mhz ; platform cost: 0.5-2M$•Commercial “white box” Emulators:•Realistically, best for mid-sized designs (Currently ~<250M gates)•User must deal with lower level/FPGA HW details internal to the emulator However usually wrappedwith SW: “white box”•Often, HW/SW from several vendors make up the complete solution.•Speed: <10Mhz ; platform cost: 100-200K$•Custom Designed FPGA PrototypeBoards:•Best for smaller designs (currently ~< 20M gates)•User owns designing the emulation platform and manages all details.•The fastest emulation technology with lowest cost/system.•Speed: ~60Mhz ; platform cost: ~7-14K$