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May 1, 2013 1FPGA Prototypes and Emulators– a Symbiotic ApproachMay 1, 2013Ilan HarelNetworking DivisionIntel
May 1, 2013 2FPGA Prototypes and Emulators– a Symbiotic ApproachMay 1, 2013Presented by Stas Cherkassky,Leonid Yuhananov
May 1, 2013 3AgendaMay 1, 2013• Intel’s Networking Division• The World of ASIC Prototyping• Big Box Emulation• Leveraging ...
May 1, 2013 4Intel’s Networking DivisionMay 1, 2013• ND creates high speedEthernet Controllers• ASIC is a pipe:• PCIE on o...
May 1, 2013 5Prototyping in development flowMay 1, 2013RTL Coding &VerificationFAB Post-SiRTL drop toemulationTape OutProt...
May 1, 2013 6Photo’s of HW examplesCommercial “Black Box”Commercial “White Box”Custom FPGA prototypes
May 1, 2013 7FPGA Box SetupMay 1, 2013HostPCIe LANLink PartnerDUT @ FPGATest ControllingSystem
May 1, 2013 8BBE In-Circuit Emulation setupMay 1, 2013HostPCIe LANLink PartnerDUT @ EmulatorTest ControllingSystem
May 1, 2013 9BBE Acceleration setupMay 1, 2013Co-simHostSWlinkDUT @ Emulator
May 1, 2013 10FPGA prototyping challengesMay 1, 2013• Design Size• FPGA partitioning• Logic trimming• Si to FPGA conversio...
May 1, 2013 11Big Box Emulator prototypingchallengesMay 1, 2013• Cost : ~ 10X [FPGA cost per gate]• Speed: usually slower ...
May 1, 2013 12Leveraging both techniquesMay 1, 2013
May 1, 2013 13The ramp-up vehicleMay 1, 2013• FPGA prototype initial ramp up takesmuch time: compilation, synthesis, timin...
May 1, 2013 14The satellite conceptMay 1, 2013SVSV SWSWSWFWFWFWEMEMSWSWRTLRTLSWSWBig boxemulatorSW,SV,FWDevelopmentDebug
May 1, 2013 15The satellite conceptMay 1, 2013• FPGA prototypes areaffordable. they arepart of SW/FW/SVdevelopment platfor...
May 1, 2013 16Complete Full Chip prototypingMay 1, 2013• FPGAs prototypes provide most of the logicbut not all of it.• Mai...
May 1, 2013 17RTL ModelsMay 1, 2013Silicon RTLFPGA RTL for FPGAboxFPGA RTL forEmulatorSilicon RTL forEmulator
May 1, 2013 18ResultsMay 1, 2013• Initial ramp up took 10 days• Emulator speed = 0.25X FPGA-box speed• Emulator compilatio...
May 1, 2013 19SummaryMay 1, 2013• The combination provides apowerful solution which leveragesboth Emulator and FPGA streng...
May 1, 2013 20For additional questions:May 1, 2013• Emulation: Ilan Harel(ilan.harel@intel.com)• Emulation: Leonid Yuhanan...
May 1, 2013 21Q&AMay 1, 2013
May 1, 2013 22Special forces development vehicleMay 1, 2013• BIST pattern development• GLS• PHY emulation
May 1, 2013 23Intel Confidential- Internal Use OnlyDifferentiation: 3 types of emulators•Commercial “black box” Emulators:...
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TRACK F: FPGA Prototypes and Emulators – a Symbiotic Approach/ Ilan Harel

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Transcript of "TRACK F: FPGA Prototypes and Emulators – a Symbiotic Approach/ Ilan Harel"

  1. 1. May 1, 2013 1FPGA Prototypes and Emulators– a Symbiotic ApproachMay 1, 2013Ilan HarelNetworking DivisionIntel
  2. 2. May 1, 2013 2FPGA Prototypes and Emulators– a Symbiotic ApproachMay 1, 2013Presented by Stas Cherkassky,Leonid Yuhananov
  3. 3. May 1, 2013 3AgendaMay 1, 2013• Intel’s Networking Division• The World of ASIC Prototyping• Big Box Emulation• Leveraging both techniques• Summary• Q/A
  4. 4. May 1, 2013 4Intel’s Networking DivisionMay 1, 2013• ND creates high speedEthernet Controllers• ASIC is a pipe:• PCIE on one side, EthernetLAN on the other• Transfer packets from sideto side
  5. 5. May 1, 2013 5Prototyping in development flowMay 1, 2013RTL Coding &VerificationFAB Post-SiRTL drop toemulationTape OutPrototypeSilicon
  6. 6. May 1, 2013 6Photo’s of HW examplesCommercial “Black Box”Commercial “White Box”Custom FPGA prototypes
  7. 7. May 1, 2013 7FPGA Box SetupMay 1, 2013HostPCIe LANLink PartnerDUT @ FPGATest ControllingSystem
  8. 8. May 1, 2013 8BBE In-Circuit Emulation setupMay 1, 2013HostPCIe LANLink PartnerDUT @ EmulatorTest ControllingSystem
  9. 9. May 1, 2013 9BBE Acceleration setupMay 1, 2013Co-simHostSWlinkDUT @ Emulator
  10. 10. May 1, 2013 10FPGA prototyping challengesMay 1, 2013• Design Size• FPGA partitioning• Logic trimming• Si to FPGA conversion• Frequency• Clock tree (gates, switches)• Development cycle• Long synthesis time• Poor visibility• FPGA set of tools
  11. 11. May 1, 2013 11Big Box Emulator prototypingchallengesMay 1, 2013• Cost : ~ 10X [FPGA cost per gate]• Speed: usually slower than FPGAs• Mobility: Heavy and require vast labinfrastructure.
  12. 12. May 1, 2013 12Leveraging both techniquesMay 1, 2013
  13. 13. May 1, 2013 13The ramp-up vehicleMay 1, 2013• FPGA prototype initial ramp up takesmuch time: compilation, synthesis, timingconvergence, debugUse the Emulator to bring up the FPGA modelRamp-up ~3-5X faster
  14. 14. May 1, 2013 14The satellite conceptMay 1, 2013SVSV SWSWSWFWFWFWEMEMSWSWRTLRTLSWSWBig boxemulatorSW,SV,FWDevelopmentDebug
  15. 15. May 1, 2013 15The satellite conceptMay 1, 2013• FPGA prototypes areaffordable. they arepart of SW/FW/SVdevelopment platformSVSVSW SWSWFWFWFWEMEMSWSWRTLRTLSWSWBig boxemulatorSW,SV,FWDevelopmentDebugOnce bugs are found, debug with EmulatorOnce reproduced – 5x faster debug
  16. 16. May 1, 2013 16Complete Full Chip prototypingMay 1, 2013• FPGAs prototypes provide most of the logicbut not all of it.• Main reasons are their limited capacity;difficulty in imitating clock tree and limitedconnectivity between FPGAs use Emulator to prototype the entire ASIC.
  17. 17. May 1, 2013 17RTL ModelsMay 1, 2013Silicon RTLFPGA RTL for FPGAboxFPGA RTL forEmulatorSilicon RTL forEmulator
  18. 18. May 1, 2013 18ResultsMay 1, 2013• Initial ramp up took 10 days• Emulator speed = 0.25X FPGA-box speed• Emulator compilation of FC = 0.2X of FPGA• Visibility = entire design for ~400K cycles• 80% of bugs found over FPGA were successfullyreproduced, debugged and solved over the Emulator• Average time invested in solving issues over Emulatoris ~5X shorter than over FPGA estimate
  19. 19. May 1, 2013 19SummaryMay 1, 2013• The combination provides apowerful solution which leveragesboth Emulator and FPGA strengths• Automation in moving from onemodel type to the other is a key tothis technique
  20. 20. May 1, 2013 20For additional questions:May 1, 2013• Emulation: Ilan Harel(ilan.harel@intel.com)• Emulation: Leonid Yuhananov(leonid.yuhananov@intel.com)• Acceleration: Stas Cherkassky(stas.cherkassky@intel.com)
  21. 21. May 1, 2013 21Q&AMay 1, 2013
  22. 22. May 1, 2013 22Special forces development vehicleMay 1, 2013• BIST pattern development• GLS• PHY emulation
  23. 23. May 1, 2013 23Intel Confidential- Internal Use OnlyDifferentiation: 3 types of emulators•Commercial “black box” Emulators:•Can accommodate large designs (currently ~5M100M+ gates)•Low-level details of emulator HW design (FPGA/routing) is hidden from users: “Black box”•All required tools/flow provided by the single emulator vendor•Speed: 100Khz-1Mhz ; platform cost: 0.5-2M$•Commercial “white box” Emulators:•Realistically, best for mid-sized designs (Currently ~<250M gates)•User must deal with lower level/FPGA HW details internal to the emulator However usually wrappedwith SW: “white box”•Often, HW/SW from several vendors make up the complete solution.•Speed: <10Mhz ; platform cost: 100-200K$•Custom Designed FPGA PrototypeBoards:•Best for smaller designs (currently ~< 20M gates)•User owns designing the emulation platform and manages all details.•The fastest emulation technology with lowest cost/system.•Speed: ~60Mhz ; platform cost: ~7-14K$
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