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Track F- Designing the kiler soc - sonics

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  • Our company started originally as an ASIC company – but the first challenge we saw was how to connect IP from so many different sources with differing bus interfaces etc. As we worked to solve this problem, we say the opportunity to be an IP company with solutions for these and other SoC design challenges. We are the only IP provider with a full range of on-chip communications network IP that addresses the complete range of SoC markets. We do this with a standard GUI (Graphical User Interface) that enables architect’s to define the system, obtaining both SystemC and RTL that is right be design. The resultant IP block is one of the most configurable IP products offered by any company, yet right be design. Over 100 of the most demanding design have been done by about 2 dozen of the most demanding customers in the world. This includes 6 of the top 10 semiconductor companies. And the complete solution means our customers have an infrastructure to take care of the requirements today and tomorrow with our ongoing R&D efforts sustained by our onging business. We are recognized as the #1 IP company providing interconnect IP for the on-chip communications network used to connect IP blocks on an SoC.

Track F- Designing the kiler soc - sonics Track F- Designing the kiler soc - sonics Presentation Transcript

  • Designing the Killer SoC:   Keeping Pace with Innovation Jack Browne, Senior VP, Sales & Marketing 4 May 2011 – ChipEx
  • Apple’s success impacts the market leaders May 2011 © Sonics, Inc., All rights reserved, May 2011 The battle of devices has now become a war of ecosystems . . . Stephen Elop, Nokia CEO, Feb 2011
  • Market Driver: Internet of Things May 2011 © Sonics, Inc., All rights reserved, May 2011 1960 1970 1980 1990 2000 2010 2020 Mainframe 1M+ units Minicomputer 10M+ units PC 100M+ units Desktop Internet 1B+ units Mobile Internet 10B+ units Smartphone E reader Tablet MP3 Cell Phone PDA Automotive - Telematics - GPS, ABS, AV Home CE Wireless Home Appliances M2M Source: Morgan Stanley, 2010, Sonics 100,000 10,000 1,000 100 10 1 M units Log scale 1,000,000
  • SoC Design Costs Growing May 2011 © Sonics, Inc., All rights reserved, May 2011 HW SW HW-independent SW HW-dependent SW HW IP Design Verification Implementation Team Size Architecture Integration SoC Volume (M#) 10 20 30 40 $26M 90nm $42M 65nm $69M 40nm $86M 28nm NRE Design Costs Expected SoC ASP SoC Unit Volumes Needed to Reach Breakeven Point Source: Semico Research, October 2010
  • Challenge: SoC Architecture Trends Distributed Heterogeneous Architectures May 2011 © Sonics, Inc., All rights reserved, May 2011 System On Chip
    • Massive feature integration
      • Driven by Moore’s Law (supply) and convergence (demand)
    • Distributed architectures
      • Higher scalability (and independence)
      • Sharing memory
    • Multiple processors
      • (Multicore) CPU
      • DSP
      • Special purpose (MPEG, GFX, …)
    • Distributed DMA
      • Removes centralized DMA bottleneck
      • Simplifies driver software integration
    • Increasing software complexity
      • Re-use with multiple platform SoCs
      • Broader end use market coverage per SoC with software programmability
    CAGR = 18.7%
  • Concurrency in Consumer SoCs
    • Consumer SoCs process data in parallel, but communicate…
    May 2011 © Sonics, Inc., All rights reserved, May 2011 H.264 Decode Audio Decode Video Out Transport demux
  • Concurrency in Consumer SoCs May 2011 © Sonics, Inc., All rights reserved, May 2011 H.264 Decode Audio Decode Video Out Transport demux DRAM alternatives: eDRAM, DDRx, LPDDRx, TSV/Wide I/O
  • Complex SoC Circa 2006: Ad Hoc & Fragile – Marority of designs with in-house solutions May 2011 © Sonics, Inc., All rights reserved, May 2011
    • Applications require massive feature sets
    • Cost, power and performance dictate many IP cores
    • Driving up integration complexity
    • SoC communications:
    • Complexity ~ (# IP Cores) 2
    Failure to Abstract Communications Causes High SoC Costs
  • Complex SoC Circa 2010: 4X More Complex – HELP!! May 2011 © Sonics, Inc., All rights reserved, May 2011 SoC Design and Verification Carry a High Price Tag
  • Semico’s View: Subsystems IP market May 2011 © Sonics, Inc., All rights reserved, May 2011 Source: Semico: IP Subsystems: The Next IP Market Paradigm, SC106-10 October 2010 IP Subsystem Market Estimated to Grow from $95.8M in 2010 to $880.6M by 2015 with a 55.8% CAGR Computing Subsystem CPU’s (multicore, coherent clusters), Memory resources, etc., Multi Media Subsystem Graphics & computing, multi-screen, 3D, etc Memory Subsystem Memory blocks, Memory i/f (xDDRy, TSV, Wide I/O), Memory Schedulers, Multi-channel, QoS, ECC, etc Video Subsystem Audio and video codecs Communications Subsystem Ethernet, WiFi, 3G, 4G, USB, SerDes, etc. Security Subsystem: Encryption / Decryption engine, Content Protection, Network Security, SoC Firewalls, Error handling System Resource Management Subsystem Virtualized system functionality (Apps and/or OS) e.g. Power management functions, security functions, fine-tuning of memory operations to reduce latency, management of software iterations
  • IP Providers Need to Deliver Subsystems May 2011 © Sonics, Inc., All rights reserved, May 2011 Complexity Drives Repartitioning Applications Operating System Host CPU IP Core Firmware IP Cores Device Drivers IP Core Delivery Subsystem Delivery IP Providers To Deliver Complete Subsystems, Reducing SoC Architecture, Verification and Software Costs Applications Operating System Device Drivers Host CPU IP Core Firmware IP Cores
    • SNAP
    • Sonics Network for AMBA Protocol
  • SNAP Product Overview
    • Built on proven Sonics Technology - 3rd generation, high volume production
      • Simple upgrade path as chip architecture evolves
      • Ultra-Low power
    • Supports all popular CPU’s
      • ARM7/ARM9
      • ARM11/CORTEX R3/A9
      • MIPS 24K/34K
      • MIPS 74K/1004K
    • Supports all popular DDR controllers
      • Sonics MemMax Controller II/III,
      • Sonics MemMax MultiPort Controller I/II/III
      • Synopsys – DDR2/3 controllers
      • Cadence - Denali - Databahn
      • Synopsys Virage Logic IntelliDDR
    • Fully verified IP module
      • Build from your specifications
      • Deliverables: documentation, RTL, test bench, synthesis scripts
    • Compelling business model
    May 2011 © Sonics, Inc., All rights reserved, May 2011
  • The problems… May 2011 © Sonics, Inc., All rights reserved, May 2011 DSP core L1 cache & SRAM Bus Matrix L2 SRAM DSPDMA SYSTEM RAM (L3) arbiter arbiter arbiter arbiter Bus Matrix Data cache Instr cache CPU EBC SOC FOC External Memeory FLASH NAND NOR SDRAM … Boot ROM PPI EBU32 SYSDMA APPDMA B SPORT Viterbi Cypher Cypher DSP IRQ FIFO TEP GSP GSP RTC USB OTG SD/ MMC weel buzz keyb Back light SIM WDT Timer MCU IRQ MCU Cipher A PORT C PORT GPIO MCUPBUS MCUSBUS MCURBUS MCUEBUS RBUS DSPBUS DABUS DPBUS SYSL2 APBUS APB DDBUS DMABUS ADABUS Need to combine buses and bus matrix with different protocols (AXI, AHB, APB). Components comes from various suppliers: difficult to design, validate Arbiters need to deal with uniform data width; need to insert data width converters when required Need to deal with multiple interfaces types: AHB, AXI, OCP, proprietary… (ARM, MIPS, Tensilica, ARC, etc.) Tired of the AHB low performances? (only 1 outstanding transaction)
  • SNAP is replacing… May 2011 © Sonics, Inc., All rights reserved, May 2011 Blackfin® DSP core L1 cache & SRAM Bus interface unit L2 SRAM DSPDMA SYSTEM RAM (L3) arbiter arbiter arbiter arbiter Bus interface unit Data cache Instr cache ARM926EJS EBC SOC FOC External Memeory FLASH NAND NOR SDRAM … Boot ROM PPI EBU32 SYSDMA APPDMA B SPORT Viterbi Cypher Cypher DSP IRQ FIFO TEP GSP GSP RTC USB OTG SD/ MMC weel buzz keyb Back light SIM WDT Timer MCU IRQ MCU Cipher A PORT C PORT GPIO MCUPBUS MCUSBUS MCURBUS MCUEBUS RBUS DSPBUS DABUS DPBUS SYSL2 APBUS PBUS DDBUS DMABUS ADABUS
    • Bus Matrixes
    • Protocol translation bridges
    • Clock division bridges
    • AHB buses
    • APB buses
  • SNAP Architecture overview
    • High performance Interconnect Matrix backbone
      • Improved Arbitration
      • QoS support
    • Master layers to connect up to 8 cores to a Matrix port
    • Slave branches to connect up to 16 slaves to a Matrix port
    • Interconnect Matrix can be split in 2 clusters
      • Easier timing closure
      • No change in connectivity
    • Optional pipeline registers in agents to support high frequency
      • Up to 266MHz in 90nm
      • > 300 MHz in 65nm
    May 2011 © Sonics, Inc., All rights reserved, May 2011 DSP core L1 cache & SRAM DSPDMA CPU Layer EBU32 DDRC GSP GSP RTC USB OTG SD/ MMC weel buzz keyb Back light SIM WDT MCU IRQ MCU Cipher A PORT C PORT GPIO CPU PERIPHERAL branch D cache I cache CPU SYSDMA Layer XB2 XB1 Viterbi Cypher Cypher DSP IRQ FIFO TEP B SPORT DSP PERIPHERAL branch SYSTEM RAM (L3) L2 SRAM Boot ROM PPI SYSDMA APPDMA
  • SNAP Development Environment May 2011 © Sonics, Inc., All rights reserved, May 2011 SNAP Capture SNAP Client SNAP Server Design.xls RTL Files + Scripts Performance Testbench Files Validation Testbench Files RTL Files + Scripts Performance Testbench Files Validation Testbench Files SNAP Test SNAP Test RTL gen translator Design.dsn Design.dsn Design_rtl.conf Client Download RTL Generation Perform Test bench Validation
  • SNAP advantages
    • Interconnect design involve solving many tradeoffs:
      • Speed = short wires => pipeline stages
      • Pipeline stages = gates = higher power
    • SNAP easy to use tool enable exploration of the interconnect design space:
      • Give control to the user to select the best choice for its application
      • Allow to specify independently connectivity and topology
        • Find the best topology amongst multiple options
      • Capability to insert pipeline registers on critical points of the communication path to ease timing closure
    May 2011 © Sonics, Inc., All rights reserved, May 2011
  • Performance exploration flows
    • Interconnect topology and features (pipelines registers, etc.) impact system performances
      • In combination with DRAM subsystem in most SoC
    • SNAP enable easy early performance explorations!
      • Masters and slaves replaced by high level models
      • Inject a simplified traffic representative of the application
      • Test bench automatically generated, can be customized
      • Instrumented with monitors
      • Tools to analyze performances out of monitors traces
    May 2011 © Sonics, Inc., All rights reserved, May 2011 BFM-M1 BFM-M2 SNAP BFM-M3 Model-M4 BFM-S0 BFM-S1 BFM-S2 Model-SWM WMphy Performance scenario Performance monitors
  • SNAP Validation approach
    • Each generated SNAP instance is unique
      • Validation need generator support!
    • Validation need to ensure:
      • IP interface protocols are fully respected ( generator )
      • Internal interconnect components works as expected ( generator )
      • Whole interconnect works as expected
    • SNAP deliver a complete validation testbench
      • Run on your machine
      • As simple as typing “make”
    • Extremely robust approach
      • 150+ design wins for our technology, not a single production bug
    May 2011 © Sonics, Inc., All rights reserved, May 2011 BFM-M1 BFM-M2 Interconnect BFM-M3 BFM-M4 BFM-S1 BFM-S2 BFM-S3 BFM-S4 Protocols monitors / checkers Random constraint scenario Internal checkers
  • User Input – simple GUI May 2011 © Sonics, Inc., All rights reserved, May 2011
  • You can try it by yourself!
    • http://www.sonicsinc.com/snap.htm
    May 2011 © Sonics, Inc., All rights reserved, May 2011
  • Summary - Benefits
    • Seamless upgrade path from a multilayer AHB architecture
    • Superior Performance, Power, and Area than Competitive Solutions Using AXI matrix + AHB buses
    • Ultra-Low Power
      • Automatic clock gating
    • High Performance
      • Cross-bar structure, separate request / response network, out of order response completion
      • AHB multi-ports agents: up to 8x the bandwidth of an AHB bus
    • Supports all popular interfaces
      • Does all the protocol, data width and clock conversions
      • No need for bridges
      • No validation required
    • Lowest Risk
      • Fully verified IP, guaranteed good-by-design by Sonics
    • Easy Delivery Process and Attractive business model
    May 2011 © Sonics, Inc., All rights reserved, May 2011
  • Industry Leader in System-Level IP May 2011 © Sonics, Inc., All rights reserved, May 2011
    • Answering the Challenge
      • Help designers integrate entire systems onto one piece of silicon and connect any IP on-chip
    • Proven Technology for 15 years
      • >1 Billion units shipped
      • >150 designs taped out
    • Key Designs with Semi Leaders
      • 7 of top 10 SoC semi companies
      • 4 of top 10 systems companies
    • Pioneering Technology Leader
      • Pioneer and World’s #1 supplier of on-chip networks for advanced SoCs
      • Highest efficiency memory subsystems
    • Market Leader
      • Leading supplier of on-chip networks in digital entertainment, wireless segments
  • May 2011 © Sonics, Inc., All rights reserved, May 2011 Sonics Confidential Thank you Jack Browne [email_address]