Track e low voltage sram - adam teman bgu

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Track e low voltage sram - adam teman bgu

  1. 1. Low Voltage SRAM DesignChallenges and Solutions<br />Adam Teman, Janna Mezhibovsky, Dr. Alexander Fish<br />Low Power Circuits and Systems Lab (LPC&S)<br />The VLSI Systems Center<br />Ben-Gurion University<br />May 4, 2011<br />
  2. 2. Lecture Contents<br />Introduction<br />Standard SRAMs at Low Voltages<br />Existing Solutions<br />LPC&S SRAM Design Activities<br />
  3. 3. Introduction<br />SRAMs are one of the main on-chip power consumers, often comprising 50% of silicon area and 50% of static power.<br />3<br />Total cache size per chip www.anandtech.com<br />
  4. 4. Introduction<br />The standard SRAM implementation is the 6T bitcell. Both write and read power are quadratically dependenton VDD.<br />4<br />
  5. 5. Introduction<br />During hold cycles, the 6T SRAM presents both subthreshold (DIBL) and gateleakage.<br />Both are exponentially dependent on supply voltage.<br />5<br />DIBL<br />Gate Bias and Oxide Thickness<br />
  6. 6. Cutoff Devices with VDS=VDD suffer from DIBL.<br /><ul><li>Devices with VGB=VDD suffer from Gate Leakage.</li></ul>0<br />0<br />VDD<br />VDD<br />VDD<br />VDD<br />VDD<br />VDD<br />Introduction<br />6<br />
  7. 7. Introduction<br />The best way to aggressively reduce SRAM power is to lower the operating voltage.<br />Quadratic reduction of Dynamic Power<br />Exponential Reduction of DIBL<br />Exponential Reduction of Gate Leakage<br />7<br />
  8. 8. Standard SRAMs at Low Voltages<br />The positive feedback of the 6T structure provides strong bi-stability and large noise margins.<br />8<br />
  9. 9. Standard SRAMs at Low Voltages<br />However, under read and write operations, the noise margins are depleted.<br />9<br />
  10. 10. Standard SRAMs at Low Voltages<br />Read and write accesses are ratioed operations and require two basic drive strength constraintsto succeed.<br />10<br />
  11. 11. Standard SRAMs at Low Voltages<br />Under strong-inversion operation, sizing the devices is usually sufficient.<br />However, global and local mismatch cause loss of functionality at voltages under ~700mV-800mV<br />11<br />
  12. 12. Existing Solutions<br />The basic solution to the read margin problem is decoupling the readout path.<br />12<br />
  13. 13. Existing Solutions<br />A differential decoupled readout provides better Sense Amplifier operation:<br />13<br />
  14. 14. Existing Solutions<br />Write margin still limits 8T operation to ~700mV, therefore write assist techniques are required. <br />14<br />Virtual Supply<br />
  15. 15. Existing Solutions<br />Word Line boosting and RSCE sizing have been implemented to improve 8T functionality.<br />15<br />Boosted WL<br />RSCE<br />
  16. 16. Existing Solutions<br />Several readout path implementations have been proposed to fight off-row leakage.<br />16<br />
  17. 17. Our work<br />Very few groups have tried to “think outside the box” and modify the internal cell structure.<br />We have proposed an internal supply feedback concept that cuts off the supply to reduce internal leakage.<br />17<br />
  18. 18. Our work<br />One example is the Quasi-Static RAM cell that floats the internal nodes, drastically reducing leakage.<br />This and other solutionsare under intensiveexamination and testing.<br />18<br />
  19. 19. Questions?<br />19<br />

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