Outline IC Power consumption – background MSC8157 brief overview State of the art power saving techniques description and their applications to MSC8157. Architecture – enabled power saving techniques. Design– enabled power saving techniques. Manufacturing technology and assembly – enabled power saving techniques. Summary
Power consumption - general Integrated Circuit (IC) device power consumption is defined as amount of energy, supplied by an external power supply to the device in pre-defined time period. We distinguish peak, maximum, typical application average and stand-by power consumption. Peak power consumption defines external power supply capability including bulk/decoupling capacitors influence. Maximum power consumption defines system thermal requirements and usually given for a time period, equal to or bigger than the system thermal reactance. Average power consumption stands to define system requirement for typical application. Stand-by power consumption describes system power consumption in stand-by/idle mode. Power consumption reduction became important to Modern Ultra Large Scale Integration (ULSI) products. Design teams fight for lower power consumption during all design stages.
IC Power consumption partitioning Power consumption comprises dynamic and static parts. Static power consumption is defined by IC active devices leakage and short circuit currents: Leakage is mainly caused by MOSFET devices sub-threshold and gate current. Short circuit current is characteristic to biased circuits, pull-up or pull-down devices and some terminated circuits. Static power consumption greatly depends on the power supply voltage VDDand temperature T. Dynamic power consumption is mainly set by active devises switching. Dynamic power consumption depends on the power supply voltage VDD and average system/device clock frequency F. P = f(VDD3,T) P = f(VDD2,F)
Power saving techniques State of the art power saving techniques include the following: Low power modes; Power supply separation; Active Power Shut-off; Active Clock gating; Multi-Voltage approach; Multi-Frequency approach; Multi-threshold CMOS design; MSC8157 make use of various power saving techniques, including architectural, design and manufacturing technology enabled – almost all known state of the art solutions, mentioned above.
Low power modes (LPM) Block functioning profile Powerconsumption Full utilization Low utilization Not in use High utilization Low Power Mode (LPM) is a mean of purposeful and environmental operation of a functional unit to achieve its lowest possible power consumption. LPM should be aligned with the purposeful utilization of the functional unit (block). Proper LPM definition allows best power consumption reduction. Improper LPM definition may cause opposite result and affects IC functionality and performance.
Low power modes (cont’d) Block functioning profile Powerconsumption Full utilization Low utilization Not in use High utilization Full utilization of the functional unit requires all its resources available, so no LPM can be applied. The functional unit design is usually targeted to this operating mode.
Low power modes (cont’d) Block functioning profile Powerconsumption Full utilization Low utilization Not in use High utilization High utilization allows some functional or environmental relaxation to save either dynamic or static power or both: Some voltage reduction saves both dynamic and static power; Frequency decrease or stopping some clocking signals saves dynamic power.
Low power modes (cont’d) Block functioning profile Powerconsumption Full utilization Low utilization Not in use High utilization Low utilization allows variety of low power modes to be applied to the block. Voltage reduction saves both dynamic and static power; Frequency decrease or alternatively disabling part of the clock signals toggling saves dynamic power; Power gating may be extensively used and greatly saves static power.
Low power modes (cont’d) Block functioning profile Powerconsumption Full utilization Low utilization Not in use High utilization When the block is not in use its physical disconnection from the power supply provides maximal leakage power saving. Physically disconnected blocks are not available for potential use. Alternatively on-die power gating also provides significant leakage power saving. This can allow the block usage in the future.
Active Power Shut-off (PSO) VDDC VDDC Switch Control Continuous supply Continuous supply VDD gated Gated supply Gated Power Domain Continuous Power Domain GND GND On-die power gating (PG) or Power Shutoff (PSO) technique is used for leakage power reduction in VLSI devices Characterized by disconnection of part(s) of a functional unit or the entire unit from the continuous power supply network Used when the unit’s operation is not required. The disconnection is provided by a switch, placed in power supply current path and controlled from another functional unit. PSO blocks when powered up, must start from the reset state.
Recovery from a PSO state LPM enable 7 1 5 3 2 6 4 Time Short LPM period tpower-up Vgated supply Time Supply voltage recovery at the PSO exit takes time (dozens to hundreds of system clock periods). This is in order to keep low noise on the continuous or keep-alive power supply part (which provides the power supply voltage to devices that should remain powered on, e.g. data retaining devices, PSO controls etc). The consequence of that is the reduction in the PSO method efficiency, especially for short Low Power Mode (LPM) periods (like periods ## 2, 6).
Clock disabling P=f(VDD2,F) Clock gate CK EN EN GCK CK GCK
Clock disabling is an effective method of dynamic power saving.
Clock network toggling provides more than 50% of the dynamic power consumption of a typical VLSI circuit.
Clock gating is a way of blocking the clock propagation, clock network toggling and consequent clocking signal arrival to registers, when logic operation does not require that.
Functional unit Clock disabling Local clock gating EN_A Unit A CKG_A EN_Z Unit Z EN CKG_Z Clocksource CKG CK Clock may be disabled either locally at the functional unit or globally for entire chip. Local disabling allows fine resolution of the blocks power management: Recovery from the local disabling is usually immediate or very short. Chip level clock distribution network and the clock source are still toggling even if all units are not in use.
Global Clock disabling Global clock gating EN_A Unit A CKG_A Clock source disabling EN_Z Unit Z EN CKG_Z Clocksource CKG CK Global clock disabling allows saving of the chip clock distribution network power. All chip units are disabled. Reset is usually required to recover from the global clock gating. Global clock source disabling (e.g. PLL stop) is the most efficient power saving way not employing power supply voltage manipulation. Reset is required to recover from the clock shut down. Recovery time is usually long.
Power distribution network partitioning VDD1 VDD2 Power Domain1 Power Domain2 P = f(VDD2,F) Die GND GND Power distribution network partitioning or power supply separation is a technique, used to provide different voltages to different parts of the IC. Static power saving for IC parts which are not in use for specific application. Power saving for IC parts which operation is possible at lower voltage. Power distribution network partitioning impacts global power distribution system quality. It should be avoided if not required. Exaggerated power distribution network partitioning requirement and improper use may bring to opposite results.
Dynamic voltage scaling (DVS) Software control function G(Ichip) VDD Ichip P=f(VDD2,F) GND
Dynamic Voltage Scaling stands for varying the power supply voltage based on the system needs and serves for dynamic and static power saving:
Manufacturing technology and environmental conditions (like “Faster” manufacturing process corner or lower temperature).
Multi-Threshold CMOS (MTCMOS) P=f(1/Vth) With the continuous scaling of CMOS devices, the device leakage current is becoming a major contributor to the IC power consumption and it is further expected to increase with the technology scaling.
The leakage current of MOSFET devices greatly influenced by its threshold voltage Vth.
MTCMOS (cont’d) For a VLSI circuit, some MOSFETs in non-critical logic signals electrical paths may be manufactured having higher threshold voltage.
the leakage current is reduced;
the performance is maintained since low threshold transistors are used in the critical signal path(s).
Both high performance and low power are achieved simultaneously. Multi-threshold technique is good for leakage power reduction during both standby and active modes without performance and die area penalty.
Power Saving in VLSI - Summary Defined IC Power consumption, including its parts and its influencing operational and environmental factors. Overviewed Architecture – enabled power saving techniques: Low power modes definition, Active Power shut-off (PSO) and Active Clock disable function. Outlined Design– enabled power saving techniques: Multi-Voltage and Multi-Frequency operation. Discussed Manufacturing technology – enabled power saving technique - Multi-threshold CMOS approach.