Challenges of Giant Silicons inAdvanced Process Technology NodePresenter: Sorel Horovitz, Design ManagerMarvell Israel
Introduction
21.5 x 23.7 = 509.55crcr crcrPLLDATADDR CNTL1.5 x 1.97DATADATADATADATADDRCNTL1.5x1.97DATADATADATADATADDRCNTL1.5x1.97DATADA...
•••••••Backend Challenges
••••Our Approach: Project partitioning
•Physical Partition
ooo••Top Routing channelsPhysical Partition
Clock StructurePhysical Partition
ooooWire SamplingPhysical Partition
• FC Timing Static Timing Flat / ETM / QTM Overlap Macros• Run time / Complexity• Macro Duplication• Inter-Block Connect...
Logical Partition
oo•Full-chip timingLogical Partition
Clock Balancing is done per cluster and between clusters.Database Collector:o Timing interface (setup / hold) per macro po...
Database Management
ooSummary
Questions
THANK YOU!
Upcoming SlideShare
Loading in …5
×

TRACK D: Challenges of Giant Silicons in Advanced Process Technology Node/ Sorel Horovitz

1,339 views

Published on

Published in: Technology, Business
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
1,339
On SlideShare
0
From Embeds
0
Number of Embeds
823
Actions
Shares
0
Downloads
1
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

TRACK D: Challenges of Giant Silicons in Advanced Process Technology Node/ Sorel Horovitz

  1. 1. Challenges of Giant Silicons inAdvanced Process Technology NodePresenter: Sorel Horovitz, Design ManagerMarvell Israel
  2. 2. Introduction
  3. 3. 21.5 x 23.7 = 509.55crcr crcrPLLDATADDR CNTL1.5 x 1.97DATADATADATADATADDRCNTL1.5x1.97DATADATADATADATADDRCNTL1.5x1.97DATADATADATADATADDRCNTL1.5x1.97DATADATADATADATADDRCNTL1.5x1.97DATADATADDRCNTL1.5x1.97DATADATADDRCNTL1.5x1.97DATADATADDRCNTL1.5x1.97DATADATADDR CNTL1.5 x 1.97DATADATADDR CNTL1.5 x 1.97DATADATADDR CNTL1.5 x 1.97DATAPLLPLLPLLPLLPEXPEXpexpexCG = 1.52 x 0.78 = 1.56Network PCL ETC(Ingress Lower 1)– 103.4 x 3.1 = 10.54Network L2I MT(Ingress Upper 1) – 18.654.4 x 4.25 = 18.7Network IPVX POLICER(Ingress upper 2)– 9.53.8 x 4.4 = 16.72BMEM lower – 2.62.563 x 1.1 = 2.8193PLLEMC LookUp– 102.2 x 4.4 = 9.68ILK_etc = 1.73.2 x 0.8 = 2.56SDSDSDSDSDSDSDSDSDSDSDSDCSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDCSDSDSDSDSDSDSDSDSDSDSDSDMiniGop21.5x2=3Network PCL(Ingress Lower 1)– 103.4 x 3.1 = 10.54Network L2I MT(Ingress Upper 1) – 13.44.4 x 4.25 = 18.7Network IPVX POLICER(Ingress upper 2)– 9.53.8 x 4.4 = 16.72MiniGop01.5x2=3MiniGop11.5x2=3CG = 1.52 x 0.78 = 1.56MiniGop21.5x2=3MiniGop01.5x2=3MiniGop11.5x2=3BMEM lower – 2.62.563 x 1.1 = 2.8193PLLPCL TCAMMacro3.3 x 2 = 6.6Action Table(19Mb)3.2 x 3.2 = 10.24PCL TCAMMacro3.3 x 2 = 6.6PCL TCAMMacro3.3 x 2 = 6.6PCL TCAMMacro3.3 x 2 = 6.6dfxBMEM lower – 2.62.5625 x 1.1 = 2.8187CMOS0CG+INLK = 2.52.3987 x 1.2 =2.8784MiniGop31.51.25 x1.2 = 1.5PLLSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDCBMEM upper 0 – 6.03.4 x 1.9 = 6.46BMEM upper 1 – 6.03.4 x 1.9 = 6.46SDSDSDSDSDSDSDSDSDSDSDSDSDSDSDSDCBMEM lower – 2.62.5625 x 1.1 = 2.8187BMEM upper 2 – 6.03.4 x 1.9 = 6.46BMEM upper 3 – 6.03.4 x 1.9 = 6.46MiniGop01.51.25 x1.2 = 1.5MiniGop11.51.25 x1.2 = 1.5MiniGop21.51.25 x1.2 = 1.5CG+INLK = 2.52.3987 x 1.2 =2.8784MiniGop31.51.25 x1.2 = 1.5MiniGop01.51.25 x1.2 = 1.5MiniGop11.51.25 x1.2 = 1.5MiniGop21.51.25 x1.2 = 1.5CMOC1CMOS2CMOS3CMOS4CMOS5FCU1.51.5 x 1 =1.5BMA – 6.53.2 x 2.0462 = 6.5477EMC Wide – 5.52.85 x 2.0185 = 5.7528TXQ2.1 x 3.45 = 7.245LL2.75 x 3.4 = 9.35CNC 01.6 x 2.3 =3.68 FB Control – 4.42.8 x 1.6 = 4.48FB Control – 4.42.8 x 1.6 = 4.48Eg2r_sht_dq21.95 x 1.8 =3.51Eg2r_sht_dq21.95 x 1.8 =3.51MPPMCNC 11.6 x 2.3 =3.68015 Fb_top 0 0 15Fb_top 1011nw_top1011Nw_top0023 Tcam ilknPLLSize & Technology
  4. 4. •••••••Backend Challenges
  5. 5. ••••Our Approach: Project partitioning
  6. 6. •Physical Partition
  7. 7. ooo••Top Routing channelsPhysical Partition
  8. 8. Clock StructurePhysical Partition
  9. 9. ooooWire SamplingPhysical Partition
  10. 10. • FC Timing Static Timing Flat / ETM / QTM Overlap Macros• Run time / Complexity• Macro Duplication• Inter-Block ConnectivityLogical Partition
  11. 11. Logical Partition
  12. 12. oo•Full-chip timingLogical Partition
  13. 13. Clock Balancing is done per cluster and between clusters.Database Collector:o Timing interface (setup / hold) per macro port is recordedo Tool analyzes database timing and decides which fixes to doDuplicated macrosFull-chip timingLogical Partition
  14. 14. Database Management
  15. 15. ooSummary
  16. 16. Questions
  17. 17. THANK YOU!

×