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TRACK D: Advanced design regardless of process technology/ Marco Casale-Rossi
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TRACK D: Advanced design regardless of process technology/ Marco Casale-Rossi

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  • 1. 1© Synopsys 2013Marco Casale-RossiSynopsys, Inc.Advanced Design ImplementationRegardless of Process Technology
  • 2. 2© Synopsys 2013Advanced Design, 1980The Mead & Conway Revolution“As a result of improvements infabrication technology, Large ScaleIntegrated (LSI) electronic has becameso dense that a single silicon LSI chipmay contain tens of thousands oftransistors. Many LSI chips, such asmicroprocessors, now consist ofmultiple, complex subsystems, and thusare really integrated systems rather thanintegrated circuits.What we have seen so far is only thebeginning. […] It will eventually bepossible to fabricate chips withhundreds of times as many componentsas today’s.”Source: C. Mead, L. Conway, Introduction to VLSI Systems, 1980
  • 3. 3© Synopsys 2013Advanced Design, 2013We Can Design Chips with Tens of Thousands TimesMore Transistors than in 1980,
  • 4. 4© Synopsys 2013Advanced Design, 2013We Can also Mix and MatchLogic + Analog & Mixed-Signal + RF +Source: Fabless, 2011 (180 & 65 Nanometers Mixed-Signal)
  • 5. 5© Synopsys 2013Advanced Design, 2013Emerging (“More of Moore”) vs.Established (“More than Moore”) Technology Nodes
  • 6. 6© Synopsys 20130%5%10%15%20%25%30%> 350 350 250 180 130 90 65/55 45/40 32/28 22/20 16/14 < 14Worldwide0%5%10%15%20%25%30%> 350 350 250 180 130 90 65/55 45/40 32/28 22/20 16/14 < 14Worldwide0%5%10%15%20%25%30%> 350 350 250 180 130 90 65/55 45/40 32/28 22/20 16/14 < 14Worldwide86%(20%)34%(66%)Advanced Design, 2013Design Starts, Established vs. Emerging Technology NodesSource: IBS, Design Starts, 2012(14%)
  • 7. 7© Synopsys 2013Advanced Design, 2013A Different View: Installed Wafer Capacity SplitEmerging vs. Established Technology NodesSource: IC Insights, April 2013
  • 8. 8© Synopsys 2013Advanced Design, 2013We See a Split• The Emerging Technology Nodes– Non-planar CMOS at 22nm (Intel) & 14nm (foundries)– Double patterning at 20nm, triple patterning ahead– Complex, high volume chips: microprocessors, high-end graphics, FPGA, wireless SoC• The Established Technology Nodes– A lot is done today in larger geometries– 45/40nm and 28nm are expected to have long lives– Key applications rely on them– SoC can be complemented by 2.5D & 3D-IC, MEMS,etc., enabling a longer technology lifespan
  • 9. 9© Synopsys 2013Advanced Design, 201xExplore, Analyze, then ImplementRTLPhysicalExplorationStageImplementationStageBlockFeasibilityBlockImplementationRTLExplorationRTLSynthesisDesignExplorationDesignPlanning
  • 10. 10© Synopsys 2013Look-Ahead & Physical Guidance1 Mx, 2 My, and 2 Mz (Almost Only P&G)> 80% Routing Utilization, > 10% Smaller DieDC-T + ICC not Routable DC-G + ICC RoutableSource: IDM, 2013 (130 Nanometers Mixed Signal)
  • 11. 11© Synopsys 2013Look-Ahead & Physical Guidance“Advanced Design Flow for LPDDR2 Non VolatileMemory Design”Source: Micron Technology, SNUG France 2012 (180 Nanometers PCM)
  • 12. 12© Synopsys 2013Advanced Design, 201xAnalyze, Verify, Guide & Repair as You ImplementImplementationSign-OffP&R STA,DRC,RepairAnalyze,Verify, GuideRepairAnalyze,Verify, GuideRepairAnalyze,Verify, Guide
  • 13. 13© Synopsys 2013Timing ClosureSetup Violations Reduction Across ReleasesBaseline 2010.03 = 0%, 130, 90 & 65 Nanometer DesignsSource: Synopsys Research, 2013Designs with lesser number of violations (< 100) are not included in this chart
  • 14. 14© Synopsys 2013Timing ClosureSetup Violations Reduction Across ReleasesBaseline 2010.03 SPG = 0%, 130, 90 & 65 Nanometer DesignsSource: Synopsys Research, 2013Designs with less number of violations (< 100) are not included in this chartDesigns with lesser number of violations (< 100) are not included in this chart
  • 15. 15© Synopsys 2013Much More Than InteroperabilityIn-Design Rail Analysis Detected a Resistance Issue(4 Instead of 1 ) in the Analog Pre-RoutingSource: IDM, 2012 (90 Nanometers Mixed Signal)
  • 16. 16© Synopsys 2013Much More Than InteroperabilityIn-Design Rail Analysis Detected a Voltage Drop and aGround Bounce IssueSource: IDM, 2012 (65 Nanometers)
  • 17. 17© Synopsys 2013Advanced Design, 201xA Great Deal of Low Power TechniquesMethodology EffectivenessMulti-Voltage Islands 1.2 – 2.5XMulti-Voltage Supplies 1.3 - 2XLower VDD Operation 1.3 - 5X ( )MTCMOS (Power Gating) 30 - 120XVTCMOS (Biasing) 2 – 1.05X ( )Multi-VTH Optimization 2 - 5XClock Gating 1.3 - 2XClock Tree Synthesis 1.4 – 3.3XMulti-Channel Optimization 2 – 5XDVFS/AVS 1.4 – 2X
  • 18. 18© Synopsys 2013Power Management12 Voltage Islands at 180 NanometersAdvanced Implementation Technology Helps a LotSource: STMicroelectronics, SNUG France 2012 (180 Nanometers Mixed-Signal)
  • 19. 19© Synopsys 2013Leakage Power ReductionThe Flow AdvantageSource: Synopsys Research, 2013
  • 20. 20© Synopsys 2013Leakage Power ReductionThe Flow Advantage0%10%20%30%40%50%60%70%80%90%100%baseline PT only FSLR+PT ICC+FSLR+PT DC+ICC+FSLR+PTgsp_fpmscoreDSS_28nmPwr % avg-33%Fair -42%Good -50%Better-59%BestSource: Synopsys Research, 2013Block 1Block 2Block 3
  • 21. 21© Synopsys 2013The Flow AdvantageMain Contributors to the 59% Leakage ReductionSource: Synopsys Research, 2013DC28%(48%)ICC + FSLR26%(43%)PT5%(9%)
  • 22. 22© Synopsys 2013The Flow AdvantageToday Design Implementation Technologyto the Rescue of Ten Year Old Process TechnologyBlock A Block GOriginal Leakage (mW) 1X 1XOriginal HS Cells (#) 100% 100%Original LL Cells (#) 0% 0%Final Leakage (mW) 0.375X 0.527XFinal HS Cells (#) 26.9% 40.3%Final LL Cells (#) 73.1% 59.7%Leakage Reduction (%) 62.5% 47.3%Source: IDM, 2013 (130 Nanometers Mixed Signal)
  • 23. 23© Synopsys 2013Advanced Design, 201xBesides Digital, Analog & Mixed SignalPlace & Route Custom Layout Round-TripSource: IDM, 2012 (180 Nanometers Mixed Signal)
  • 24. 24© Synopsys 2013Much More Than InteroperabilityPlace & Route Custom Layout Round-TripAnalog Routing in Custom Layout EnvironmentSource: IDM, 2012 (180 Nanometers Mixed Signal)
  • 25. 25© Synopsys 2013Much More Than InteroperabilityPlace & Route Custom Layout Round-TripDigital Routing in Place & RouteSource: IDM, 2012 (180 Nanometers Mixed Signal)
  • 26. 26© Synopsys 2013Much More Than InteroperabilityAnalog Pre-Routing & ShieldingIntegrity Analysis & Resistance CalculationSource: IDM, 2012 (90 Nanometers Mixed Signal)
  • 27. 27© Synopsys 2013Advanced Design, 201xBeyond IC, Towards Heterogeneous SystemsToday... Tomorrow13 x 13 x 2mmSource: iNEMO-M1, STMicroelectronics, 2012Note: These Examples Are for Illustration Purposes Only
  • 28. 28© Synopsys 2013Heterogeneous SystemsWill Enhance the Performance and Breadth of SolutionsProvided by IC VendorsCourtesy of A. Fontanelli, Monozukuri, 2012Package Substrate
  • 29. 29© Synopsys 2013Leveraging Existing ToolsSilicon Interposer (Detail) RoutedSource: Synopsys Research, 2011
  • 30. 30© Synopsys 2013A New RouterDie-to-Die (µBump to µBump) 45° RDL RoutingNot Only for 3D-ICSource: Synopsys Research, 2012
  • 31. 31© Synopsys 2013Leveraging Existing ToolsMulti-Technology SimulationX<instance_name> <interconnect> [<module_label>::]<subcircuit_name> <parameters>.module <label>.include <>.lib <>.model <>.param <>.option scale <>.endmodule
  • 32. 32© Synopsys 2013.module memorycube.lib ‘CMOS28.lib’.temp 85.subckt memory1 N1.ends.endmoduleMulti-Technology SimulationNot Only for 3D-ICX1 N1 memorycube::memory1X2 N2 logicdie::logic1X3 N3 analogdie::analog1V1.tran 1n 100n.print v(*).module analogdie.lib ‘CMOS130.lib’.temp 40.subckt analog1 N1.ends.endmodule.module logicdie.lib ‘CMOS20.lib’.temp 125.subckt logic1 N1.ends.endmodule
  • 33. 33© Synopsys 2013Three Years AgoUse of Routing Resources Across ReleasesBaseline = 2007.03, 130 & 90 Nanometer DesignsDesign A, 90 NanometersReleaseBaseline = 6 layers Routability in 5 layers# routingViolationspost ICC% change in area%change in netcount%change in wirelength# routingViolationspostICC% change inarea%change in netcount%change inwire length2007.03 4 100.0% 100.0% 100.0% 4582 100.0% 100.0% 100.0%2007.12 0 99.0% 100.8% 99.0% 2769 98.8% 100.8% 98.9%2008.09 0 98.4% 102.0% 94.3% 1947 98.1% 101.6% 93.0%2009.06 0 97.0% 103.6% 89.8% 511 96.9% 103.5% 90.2%2010.03 6 94.4% 100.3% 82.4% 23 94.1% 100.0% 81.8%Design B, 90 NanometersReleaseBaseline = 5 layers Routability in 4 layers# routingViolationspost ICC% change in area%change in netcount%change in wirelength# routingViolationspostICC% change inarea%change in netcount%change inwire length2007.12 5 100.0% 100.0% 100.0% 237 100.0% 100.0% 100.0%2008.09 3 95.1% 92.2% 97.8% 4 96.0% 92.3% 106.4%2009.06 3 91.6% 88.7% 87.6% 11 91.5% 88.5% 86.5%2010.03 7 91.7% 92.6% 88.4% 221 93.3% 91.6% 115.7%Design 3, 130 NanometersReleaseBaseline = 6 layers Routability in 5 layers# routingViolationspost ICC% change in area%change in netcount%change in wirelength# routingViolationspostICC% change inarea%change in netcount%change inwire length2007.12 0 100.0% 100.0% 100.0% 65792 100.0% 100.0% 100.0%2008.09 0 99.4% 105.9% 106.3% 75162 100.5% 108.1% 111.8%2009.06 7 97.8% 103.4% 94.8% 71154 95.9% 102.4% 95.1%2010.03 26 94.8% 94.4% 96.4% 35835 94.0% 93.8% 92.3%Source: Synopsys Research, 2010
  • 34. 34© Synopsys 2013TodayUse of Routing Resources Across ReleasesBaseline = 2010.03, 130 & 65 Nanometer DesignsDesignNameBaseline =Routing ViolationsUsing 8 layersRouting ViolationsUsing 6 LayersRouting ViolationsUsing 5 Layers2010.03 2010.12 2011.09 2012.06 2013.03 2010.03 2010.12 2011.09 2012.06 2013.03 2010.03 2010.12 2011.09 2012.06 2013.03Design 2 14 34 20 38 29 23 15 18 12 3 8460 6397 3508 4743 3301Design 3 135 117 112 119 130 120 116 125 120 116 560 112 106 107 117Design 8 2341 2038 2326 2223 2446 2692 2400 2587 2697 3099 3715 2911 3464 4202 3918Design 9 2460 2400 2159 2617 2490 2626 2706 2443 2711 2596 5425 5760 6305 7598 6050Design 10 25 12 28 15 15 43 40 12 28 17 27267 13274 809 15423 1534Source: Synopsys Research, 2013
  • 35. 35© Synopsys 2013Use Of Routing Resources3 Layers Instead of 4Utilization from 60% to 67%, 81% Double Via RateSource: IDM, 2012 (130 Nanometers Mixed Signal)
  • 36. 36© Synopsys 2013Use Of Routing Resources4 Layers Instead of 6Utilization 77%, 80% Double Via RateDC-G + ICC RoutableSource: IDM, 2012 (130 Nanometers Mixed Signal)
  • 37. 37© Synopsys 2013• Technologies look like “trailing edge” from a manu-facturing process point-of-view• Design, instead, is “bleeding edge” regardless of themanufacturing process, and will even more THEdifferentiator• EDA is a critical ingredient of successful design• The final result of combining “more than Moore” and“more of Moore” can be surprisingly more advanced thanwhat is allowed by the simple progression of thesemiconductor roadmap through scalingConclusionsSource: C. Cognetti, STMicroelectronics, Napa KGD Packaging & Test 2004
  • 38. 38© Synopsys 2013Follow Synopsys!facebook.com/synopsystwitter.com/synopsys youtube.com/synopsyslinkd.in/MThWJg
  • 39. 39© Synopsys 2013‫ה‬ ָ‫ּתֹוד‬May 2nd, 2013Tel Aviv, Israel