Designing At 2x Nanometers  Some New Problems Appear, and      Some Old Ones Remain     Marco Casale-Rossi       Synopsys,...
Designing At 2x NanometersWhat Are the Key Areas of Focus?(1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Meta...
More Complexity ChallengesSheer Complexity Remains the #1 Challenge                                              Intel CE4...
Gigascale Design ImplementationEvolving Into Two, Closely Connected “Sub-Systems”• The Initial “sub-system”   – Fast synth...
RTL Exploration~ 6X Faster Than RTL SynthesisSlack Distribution Comparison, Correlation ±8%           Slack Histogram     ...
Look-Ahead & Physical GuidanceSame Critical Paths, Correlation ±5%                   Synthesis           Place & RouteSour...
Gigascale Design Implementation  Constraints Analysis, Design Exploration & Block Feasibility  • Initial Floorplan Partiti...
Design ExplorationHeading Into the Right Direction ?Standard Placement (Fully Legalized)   Exploration Placement (Coarser)...
Block Feasibility45 Nanometers, 4M Instances                    Feasibility       Implementation          Feasibility     ...
Gigascale Design ImplementationLonger Term Evolution• Until now :   – Mostly “preserve” the gates   – “Change” placement, ...
ECO Flow  32 Nanometers, ~ 3M Instances, ~ 300 Macro Blocks  40 Scenarios, Runtime < 8 Hours, 99% Hold Fix Rate           ...
Leakage Recovery32 Nanometers, ~ 3M Instances, ~ 300 Macro Blocks               Leakage = 1X      Leakage = 0.77X, -23%Sou...
More Performance ChallengesThe Application Processors Race for “PP&A”                   Maximum Clock Frequency @ Nominal ...
High Speed And Low Power FlowBetter Quality-of-Results, Faster Time-to-Results    Targets               Typical flow on   ...
High Speed And Low Power FlowARM Cortex™-A9 MPCore™ Dual Core                                                             ...
More Performance ChallengesBesides Digital,                         Analog and Mixed-Signal                     Digital   ...
Much More Than Just InteroperabilityShared Tasks Between Digital and Analog EnvironmentsSource: Synopsys Research 2012    ...
Analog Pre-RoutingMatched Resistance RoutingSource: Synopsys Research 2012                                              18...
What Else Should We Look At?Three “Revolutions” After Thirty Years of “Evolution”     Device            Non-planar CMOS Li...
The Challenge: Planar CMOSInsufficient Performance, Excessive Power       32 Nanometer Planar         Not Enough   “Headro...
The Solution: Non-Planar CMOSThe First “Revolution”     22 Nanometer Tri-Gate         More “Headroom” !!!Source: K. Kuhn, ...
The SolutionSPICE Simulation, and Parasitic Extraction            Model/Compute                     Parasitics/Extract    ...
The Challenge: Single Exposure“Last Pitch With Single Exposure ~ 80 Nanometers                                            ...
The Solution: Double PatterningThe Second “Revolution”   We Can Print This,   and This,   And Then This!                  ...
The SolutionDPT Ready Logic Libraries and Placer     DPT-Aware Placement         DPT Compliant ColoringSource: Synopsys Re...
The SolutionDPT Ready Router and DRCSource: Synopsys Research 2012                                              26        ...
The Challenge: “> 2D-IC”“More of Moore” Requires “More than Moore”  1                                              2      ...
The Solution: 3D-ICThe Third “Revolution”Source: L. Madden, Xilinx, 2011                                               28 ...
The SolutionSide-by-Side, Passive Silicon Interposer,Single-Sided (F2F), to Begin withSource: Synopsys Research 2011      ...
The SolutionSilicon Interposer with P&G Grid, andµBumps, TSV, and C4Source: Synopsys Research 2011                        ...
Leveraging Existing ToolsSilicon Interposer (Detail)Source: Synopsys Research 2011                                        ...
Leveraging Existing ToolsSilicon Interposer (Detail) RoutedSource: Synopsys Research 2011                                 ...
‫תּוֹדָ ה‬May 2nd, 2012Tel Aviv, Israel                                33                   © Synopsys 2012
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Designing at 2x nanometers Some New Problems Appear & Some Old Ones Remain

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Designing at 2x nanometers Some New Problems Appear & Some Old Ones Remain

  1. 1. Designing At 2x Nanometers Some New Problems Appear, and Some Old Ones Remain Marco Casale-Rossi Synopsys, Inc. 1 © Synopsys 2012
  2. 2. Designing At 2x NanometersWhat Are the Key Areas of Focus?(1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate; (3) Planar CMOS Source: ITRS 2011, AMSL 2010, IBS 2008(1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate; (3) Planar CMOS; 2 © Synopsys 2012
  3. 3. More Complexity ChallengesSheer Complexity Remains the #1 Challenge Intel CE4200 45 nanometers (2010) Intel CE3100, 90 nanometers (2008) 96mm2, ~ 300M transistors 208mm2, 150M transistors, 10W 7-9W 3 © Synopsys 2012
  4. 4. Gigascale Design ImplementationEvolving Into Two, Closely Connected “Sub-Systems”• The Initial “sub-system” – Fast synthesis, floorplanning, and placement – Used for design exploration, constraints clean-up, feasibility – Findings – e.g. floorplan – will be “shared” with back-end• The Full “sub-system” – Takes over once “initial” done – Full synthesis and place & route – Heavy use of special “correction” techniques 4 © Synopsys 2012
  5. 5. RTL Exploration~ 6X Faster Than RTL SynthesisSlack Distribution Comparison, Correlation ±8% Slack Histogram Floorplan DC-E DC-T DC-E w/ Floorplan Information -1.3 -0.95 -0.55 -0.15 0.2 0.55 0.95 1.3 1.7 2.1Source: Synopsys Research 2011 5 © Synopsys 2012
  6. 6. Look-Ahead & Physical GuidanceSame Critical Paths, Correlation ±5% Synthesis Place & RouteSource: Synopsys Research 2011 6 © Synopsys 2012
  7. 7. Gigascale Design Implementation Constraints Analysis, Design Exploration & Block Feasibility • Initial Floorplan Partitions • Final Top Level Floorplan • Final Chip Implementation • Clean Top Level Routing • Block Level Floorplan • Blocks Modeled as ILM/ETM • Clean Top Level SDC • Timing Budgets Feasibility Stage Implementation StageChip Design Exploration Design Planning Top AssemblyLevelBlock Block Feasibility Block ImplementationLevel • Clean Block Level SDC • Final Block Implementation • Final Block Level Floorplan • Timing and Congestion Clean Dirty Clean Final Design Data 7 © Synopsys 2012
  8. 8. Design ExplorationHeading Into the Right Direction ?Standard Placement (Fully Legalized) Exploration Placement (Coarser) Several Hours 27M Instances in 1 HourSource: Fujitsu, SNUG Japan 2010 8 © Synopsys 2012
  9. 9. Block Feasibility45 Nanometers, 4M Instances Feasibility Implementation Feasibility Implementation Runtime Runtime Performance Performance Implementation 30 Results Improve w/ Cleaner SDC 200 Performance (MHz) 25 Runtime (Hours) Feasibility 20 QOR Same As Implementation 100 15 10 0 No false paths or 17 false paths not 17 false paths + 3 All false paths and Feasibility Feasibility Runtime multi-cycle paths identified multicycle paths not multi-cycle paths 2X Faster Than Independent of SDC Implementationidentified identified identified DirtinessSource: IDM, 2010 9 © Synopsys 2012
  10. 10. Gigascale Design ImplementationLonger Term Evolution• Until now : – Mostly “preserve” the gates – “Change” placement, and/or routing to close timing, power, • Very, very time consuming, and • Leads to a number of iterations• In the future : – Once the objective is “within reach” – “Hold” placement and routing – Systematically “change” the gates • Same footprint, different timing, power, temperature inversion point, etc. • The richness of the library is fundamentally important 10 © Synopsys 2012
  11. 11. ECO Flow 32 Nanometers, ~ 3M Instances, ~ 300 Macro Blocks 40 Scenarios, Runtime < 8 Hours, 99% Hold Fix Rate 1000000TNS, No. of Violations, WNS 100000 10000 1000 100 10 1 1st SignOff ECO1 ECO2 Total Hold Slack (ps) 19558 102 34 No. Hold Violations 2382 49 6 WNS (ps) 116 6 15 Source: STMicroelectronics, PrimeTime SIG, 2012 11 © Synopsys 2012
  12. 12. Leakage Recovery32 Nanometers, ~ 3M Instances, ~ 300 Macro Blocks Leakage = 1X Leakage = 0.77X, -23%Source: Synopsys Research 2011 12 © Synopsys 2012
  13. 13. More Performance ChallengesThe Application Processors Race for “PP&A” Maximum Clock Frequency @ Nominal Voltage, 125°C, 500mW12X10X 8X 6X 4X 2X X 90 65 45/40 32/28 22/20Source: Synopsys Research 2011 13 © Synopsys 2012
  14. 14. High Speed And Low Power FlowBetter Quality-of-Results, Faster Time-to-Results Targets Typical flow on Typical flow on high speed, standard designs low power designs 100% Better quality-of-results 90% 75% High speed and low power (HSLP) flow Typical flow Faster time-to-results HSLP flow Design-specific Time customizationSource: Synopsys Research 2011 14 © Synopsys 2012
  15. 15. High Speed And Low Power FlowARM Cortex™-A9 MPCore™ Dual Core Timing Closure Profile 110% Performance (% of Target) 100% 90% 80% Synthesis Placement CTS Routing Additional Customization For High Speed High Speed and Low Power Flow RM (Baseline) FlowSource: Global Unichip, SNUG Taiwan 2011 15 © Synopsys 2012
  16. 16. More Performance ChallengesBesides Digital, Analog and Mixed-Signal Digital Analog & M/SSource: R. Rutenbar, CMU, ICCAD 2006; H. Hiller, Infineon, DAC 2007 16 © Synopsys 2012
  17. 17. Much More Than Just InteroperabilityShared Tasks Between Digital and Analog EnvironmentsSource: Synopsys Research 2012 17 © Synopsys 2012
  18. 18. Analog Pre-RoutingMatched Resistance RoutingSource: Synopsys Research 2012 18 © Synopsys 2012
  19. 19. What Else Should We Look At?Three “Revolutions” After Thirty Years of “Evolution” Device Non-planar CMOS Lithography Double patterning Integration 3D-IC 19 © Synopsys 2012
  20. 20. The Challenge: Planar CMOSInsufficient Performance, Excessive Power 32 Nanometer Planar Not Enough “Headroom”Source: K. Kuhn, Intel, IDF 2011 20 © Synopsys 2012
  21. 21. The Solution: Non-Planar CMOSThe First “Revolution” 22 Nanometer Tri-Gate More “Headroom” !!!Source: K. Kuhn, Intel, IDF 2011 21 © Synopsys 2012
  22. 22. The SolutionSPICE Simulation, and Parasitic Extraction Model/Compute Parasitics/Extract M1 Contact Gate Source Fin Fin DrainSource: Synopsys Research 2011 22 © Synopsys 2012
  23. 23. The Challenge: Single Exposure“Last Pitch With Single Exposure ~ 80 Nanometers ” We Can Print This, But We Cannot Print ThisSource: M. van den Brink, ASML, ITF 2009; P. Magarshack, STMicroelectronics, 2010 23 © Synopsys 2012
  24. 24. The Solution: Double PatterningThe Second “Revolution” We Can Print This, and This, And Then This! 24 © Synopsys 2012
  25. 25. The SolutionDPT Ready Logic Libraries and Placer DPT-Aware Placement DPT Compliant ColoringSource: Synopsys Research 2012 25 © Synopsys 2012
  26. 26. The SolutionDPT Ready Router and DRCSource: Synopsys Research 2012 26 © Synopsys 2012
  27. 27. The Challenge: “> 2D-IC”“More of Moore” Requires “More than Moore” 1 2 C4 Silicon InterposerMemory (Wide I/O) Memory TSV 3D Stack µBump“Cube” “Cube” on Logic 4 3Source: Synopsys Research 2011 27 © Synopsys 2012
  28. 28. The Solution: 3D-ICThe Third “Revolution”Source: L. Madden, Xilinx, 2011 28 © Synopsys 2012
  29. 29. The SolutionSide-by-Side, Passive Silicon Interposer,Single-Sided (F2F), to Begin withSource: Synopsys Research 2011 29 © Synopsys 2012
  30. 30. The SolutionSilicon Interposer with P&G Grid, andµBumps, TSV, and C4Source: Synopsys Research 2011 30 © Synopsys 2012
  31. 31. Leveraging Existing ToolsSilicon Interposer (Detail)Source: Synopsys Research 2011 31 © Synopsys 2012
  32. 32. Leveraging Existing ToolsSilicon Interposer (Detail) RoutedSource: Synopsys Research 2011 32 © Synopsys 2012
  33. 33. ‫תּוֹדָ ה‬May 2nd, 2012Tel Aviv, Israel 33 © Synopsys 2012

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