Contemporary Design of High ADC

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Dr. Mikko E. Waltari,
IQ analog

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Contemporary Design of High ADC

  1. 1. Contemporary Design of High-Speed, High-Performance, Analog to Digital Converters in Deep Submicron CMOS ,Mikko Waltari San Diego, CA May 2,2, 2012 May 2012 1
  2. 2. Outline• Motivation• Deep Submicron Challenges for ADC Design• ADC Front-End• Linearity Calibration• Time Interleaving• 14-bit 200MS/s ADC core May 2, 2012 2
  3. 3. Motivation• Demand for high-speed high-resolution (>12 bits, >100MS/s) ADCs increasing. – Main applications in wired and wireless communications.• The architecture most suitable for meeting these specifications is the pipeline ADC.• Most commercially available products are implemented in SiGe or 0.18µm CMOS.• Deep sub-micron CMOS offers many attractive benefits – Low power consumption – High sampling rate – Higher level of integration • Multi-channel products, SoC integration, utilization of DSP for increased performance, integration of digital support functions (decimation, IQ mismatch correction, down conversion, etc) May 2, 2012 3
  4. 4. Deep Sub-Micron Challenges for ADC Design• Low supply voltage (< 1.2V). – Limited analog voltage swing. – Many traditionally used analog circuit structures unfeasible.• Low intrinsic gain of short channel devices. – Difficult to design high gain amplifiers, which are a key building blocks in pipelined ADCs.• Deep sub-micron is good for digital – Small size, low power consumption. -> use of digital techniques to enhance the analog performance. May 2, 2012 4
  5. 5. ADC Front-End• The front-end largely determines the ADC linearity at high 70dB SNDR frequencies.• The most demanding 50dB application is the direct IF sampling. – The use of sub-sampling F in (signal frequency > Fs/2) Typical Behavior increases the challenge. May 2, 2012 5
  6. 6. Front-End Driver• ADC input has a ADC switched sampling capacitor. – Difficult to drive with ADC good linearity.• Many SiGe/BiCMOS designs use integrated • Alternative is to make buffer amplifier. the capacitor easier to – Designing such an amplifier in CMOS drive. impractical. – Eliminate nonlinear charge kick-back. May 2, 2012 6
  7. 7. Sampling Switch• Largely determines the ADC linearity at high signal frequencies.• Simplest switch is a single NMOS transistor or a transmission gate. – Resistance depends on the signal voltage -> poor linearity.• Technique called bootstrapping makes the transistor gate voltage follow the input signal -> signal independent on-resistance. – Utilizing deep n-well provides further improvement. May 2, 2012 7
  8. 8. Switch Circuits CLKS in g le tra n s is to r s w itc h C LK CLK CLK CLK CLK B o o ts tra p p e d s w itc h CLK w ith d e e p N - w e ll May 2, 2012 8
  9. 9. Linearity Calibration• Capacitor mismatch and low amplifier gain produce INL (integral non-linearity) errors -> poor SNDR.• Can be improved by increasing device sizes -> larger area, higher power consumption.• Digital Calibration is a better solution – Correction coefficient added to every ADC output sample.• Foreground calibration at power up with a help of a calibration DAC. Doesn’t track temperature and voltage variations.• Continuous background calibration utilizing the statistics of the input signal to determine the calibration coefficients. May 2, 2012 9
  10. 10. Linearity Calibration May 2, 2012 10
  11. 11. Time-Interleaving• ADC sampling rate can be ADC1 increased by C LK In O ut time interleaving two ADC2 or more ADC cores. C L K /2 May 2, 2012 11
  12. 12. Time-Interleaving Errors• Gain mismatch, voltage offset, and clock skew between the ADC cores create spectral artifacts.• The effect of timing skew is signal frequency dependent, limiting the high frequency performance of time-interleaved ADC. May 2, 2012 12
  13. 13. Time-Interleaving Calibration• Gain mismatch and voltage offset relatively easy to calibrate.• Timing skew calibration is more difficult.• Calibration is divided into two tasks: 1. Error Detection 2. Error Correction• Correction can be done digitally or by feeding back an analog correction signal using a DAC• Detection is the more difficult of the two tasks. May 2, 2012 13
  14. 14. Clock Skew Calibration Using Out of Band Test Signal• A low-level narrow- band test signal is injected into the ADC Test Signal Generation input outside the DAC signal band. – A known test signal Analog ADC1 Digital Out In makes the error MUX detection robust and ADC2 Mismatch Error relatively fast. ge Parameter te Signal Estimation Generation• Error correction done with digital filters. May 2, 2012 14
  15. 15. Time Interleaving Calibration• Multi-tone pattern shows image tones before calibration.• Calibration reduces the artifacts by more than 40dB. May 2, 2012 15
  16. 16. bit 200MS/s ADC core in 65nm-14 CMOS• 65nm CMOS process, 1.2V supply voltage• High linearity input sampling: >78dB SFDR up to 366MHz input frequency.• Background linearity calibration• Low power consumption (130mW)• 2x time interleaving to extend the sampling rate to 400MS/s May 2, 2012 16
  17. 17. !Thank You May 2, 2012 17

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