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Final Year IEEE Projects On VLSI - 2013-14Ttitles
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Final Year IEEE Projects On VLSI - 2013-14Ttitles

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  • 1. VLSI PROJECT CODE Email: vlsi@pantechmail.com PROJECT THEME APPLICATION Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays LFSR-Reseeding Scheme For Achieving Test Coverage Cellular Telephony PSVLS303 DC Noise Margin and Failure Analysis of Proposed Low Swing Voltage SRAM cell for High Speed CMOS Circuits Microchip Manufacturing PSVLS304 Used self-controllable Voltage Level technique to reduce leakage current in DRAM 4×4 in VLSI Microchip Manufacturing PSVLS305 Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic Photovoltaics PSVLS306 Logical Effort for CMOS-Based Dual Mode Logic Gates TECHNOLOGY / CORE License Plate Recognition For Toll Gate System PSVLS323 Improved number plate localization algorithm and its efficient field programmable gate arrays implementation PSVLS309 PSVLS310 PSVLS311 PSVLS312 PSVLS313 PSVLS314 PSVLS315 PSVLS316 PSVLS317 PSVLS318 PSVLS319 PSVLS320 CMOS | MEMORY DESIGN PSVLS322 PSVLS308 LOW POWER DESIGN | CMOS | SEQUENTIAL, ARITHMETIC, DIGITAL AND ANALOG CIRCUITS PSVLS321 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Low-power high-speed full adder for portable electronic applications Low-Power Digital Signal Processing Using Approximate Adders Activity-Driven Fine-grained Clock Gating and Run Time Power Gating Integration A Novel Flip-Flop Design for Low Power Clocking System Modeling and Simulation of Low Power 14 T Full Adder with Reduced Ground Bounce Noise at 45 nm Technology Leakage Minimization of 10T Full Adder Using Deep Sub-Micron Technique Asynchronous Design of Energy Efficient Full Adder Design of a Low-Power Pulse-Triggered Flip-Flop with Conditional Clock Technique Design of High Speed and Low Power 15-4 Compressor Analysis and design of a Low-Voltage Low-Power Double-tail Comparator Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop Comparative Analysis For Hardware Circuit Architecture Of Wallace Tree Multiplier Rescue robo PSVLS307 IEEE 2013 TESTING | DFT PSVLS302 Avionics IEEE 2013 CADENCE PSVLS301 Microchip Manufacturing Photovoltaics MEMS Power Management Microchip Manufacturing Avionics Microchip Manufacturing Microchip Manufacturing Photovoltaics RF & MEMS Avionics Avionics Avionics Photovoltaics Microchip Manufacturing Machine Vision Electronic Article Surveillance Electronic Article Surveillance www.finalyearieeeprojects.com| www.pantechsolutions.net | www.pantechproed.com ©2013 Pantech ProEd Private Limited 12
  • 2. VLSI PSVLS330 PSVLS331 PSVLS332 PSVLS333 PSVLS334 PSVLS335 PSVLS336 PSVLS337 PSVLS338 PSVLS339 Machine Vision Remote Monitoring Design and Implement of Real-time Monitoring System of Urban Water Supply FPGA Based Embedded Webserver Using Microblaze Processor Exploration of Multi-thread Processing on XILKERNEL for FPGA Based Embedded Systems Energy Efficient Image Transmission Automotive Infotainment Automotive Infotainment Machine Vision Fast FPGA-Based Multi-object Feature Extraction “ i ” - A novel algorithm for Optical Character Recognition (OCR) Hardware Implementation of a Digital Watermarking System for Video Authentication Computer Vision Vehicular Networking Reconfigurable Processor for Binary Image Processing Machine Vision FPGA Implementation of Pipelined Architecture For SPIHT Algorithm Least Significant Bit Matching Steganalysis Based on Feature Analysis Defence Biomedical Signal Defence Networking Line Card PSVLS340 Implementation of I2C Master Bus Controller on FPGA PSVLS341 Pipelined Radix-2K Feed forward FFT Architectures Radar PSVLS342 Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT OFDM PSVLS343 PSVLS344 PSVLS345 PSVLS346 High-Throughput Compact Delay-Insensitive Asynchronous NoC Router Design of Sobel Operator Using Field Programmable Gate Arrays Modified Gradient Search for Level Set Based Image Segmentation Selective Eigen background for Background Modeling and Subtraction in Crowded Scenes IEEE 2013 SPARTAN 3AN Asset Tracking REAL-TIME APPLICATONS (GPS, GSM, ZIGBEE , RF) PSVLS329 An Interactive RFID-based Bracelet for Airport Luggage Tracking System RFID-based Location System for Forest Search and Rescue Missions Electronic Article Surveillance IEEE 2013 SPARTAN 6 EDK | SOFT CORE PROCESSOR DESIGN PSVLS328 A Smarter Toll Gate Based on Web Of Things Signal Jamming IEEE 2013 PSVLS327 Machine Vision COMMUNICATION PROTOCOL DESIGN PSVLS326 Machine Vision IEEE 2013 PSVLS325 Prototype of a Fingerprint Based Licensing System For Driving Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing Secure Transmission in Downlink Cellular Network with a Cooperative Jammer SPARTAN 6 BIOMEDICAL PSVLS324 Email: vlsi@pantechmail.com Computer Networking Machine Vision Bio-Medical Computer Vision www.finalyearieeeprojects.com| www.pantechsolutions.net | www.pantechproed.com ©2013 Pantech ProEd Private Limited 13
  • 3. VLSI PSVLS354 PSVLS355 PSVLS356 PSVLS357 PSVLS358 PSVLS359 PSVLS360 PSVLS361 PSVLS362 PSVLS363 PSVLS364 PSVLS365 PSVLS366 PSVLS367 PSVLS368 PSVLS369 PSVLS370 Low-Power and Area-Efficient Carry Select Adder Designing and Simulation of Full Adder Cell Using FINFET Technique A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique A Low Power CMOS Voltage Mode SRAM Cell for High Speed VLSI Design Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks Ultralow-Voltage Process-Variation-Tolerant SchmittTrigger-Based SRAM Design Single Phase Clocked Quasi Static Adiabatic Tree Adder An Embedded Real-Time Finger-Vein Recognition System for Mobile Devices Gesture Recognition Using Field Programmable Gate Arrays An improved three-factor authentication scheme using smart card with biometric privacy protection Platform-Independent Customizable UART Soft-Core Computer Vision IEEE 2013 SPARTAN 6 BIOMEDICAL NON LINEAR FILTERS PSVLS353 Computer Vision NETWORK SECURITY PSVLS352 Computer Vision LOW POWER DESIGN CIRCUITS | TANNER EDA S-EDIT & W-EDIT PSVLS351 Machine Vision IEEE 2013 SPARTAN 6 PSVLS350 Computer Vision IEEE 2013 PSVLS349 Computer Vision IEEE 2012 TESTING PSVLS348 FPGA Implementation of Moving Object Detection in Frames by Using Background Subtraction Algorithm Realization of Beamlet Transform Edge Detection Algorithm using FPGA An Analysis of SOBEL and GABOR Image Filters for Identifying Fish Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT Optical Flow Estimation for Flame Detection in Videos An Efficient Denoising Architecture for Removal of Impulse Noise in Images Design and Implementation of Hardware Architecture for Denoising Using FPGA Performance Analysis of Encryption Algorithms for Information Security Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware Parallel AES Encryption Engines for Many-Core Processor Arrays FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial using VHDL Optimization of Microcode Built-In Self Test By Enhanced Faults Coverage for Embedded Memory Computer Vision Defence NSA Products NSA Products Microchip Manufacturing Microchip Manufacturing Power Management Avionics Avionics Microchip Manufacturing Photovoltaics MEMS Microchip Manufacturing Photovoltaics Machine Vision Machine Vision Machine Vision Modems www.finalyearieeeprojects.com| www.pantechsolutions.net | www.pantechproed.com ©2013 Pantech ProEd Private Limited IEEE 2012 BIOMETRIC WSN PSVLS347 Email: vlsi@pantechmail.com 14
  • 4. VLSI PSVLS372 PSVLS373 PSVLS374 PSVLS375 PSVLS376 PSVLS377 PSVLS378 PSVLS379 PSVLS380 PSVLS381 PSVLS382 PSVLS383 PSVLS384 WLAN, , Bluetooth BPSK System on Spartan 3E FPGA Design of an error detection and data recovery architecture for motion estimation testing applications Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS Analysis of CT and MRI Image Fusion using Wavelet Transform A Level Set Based Deformable Model for Segmenting Tumors in Medical Images Edge Detection of Angiogram Images Using the Classical Image Processing Techniques FPGA Hardware of the LSB Steganography Method An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform A Level Set Based Deformable Model for Segmenting Tumors in Medical Images A Novel Architecture for VLSI Implementation of RSA Cryptosystem An efficient FPGA implementation of the Advanced Encryption Standard Algorithm A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL Computer Vision Radar Automotive Infotainment Bio-Medical Machine Vision Machine Vision Defence Computer Vision Biomedical Biomedical Defence NSA Products NSA Products www.finalyearieeeprojects.com| www.pantechsolutions.net | www.pantechproed.com ©2013 Pantech ProEd Private Limited IEEE 2012 SIGNAL PROCESSING CORE PROCESSOR DESIGN | CRYPTOGRAPHY PSVLS371 Email: vlsi@pantechmail.com 15