Jasmin Ibrahimovic
Senior Design Engineer: SoC, ASIC, FPGA, Embedded, High-Speed
jasmin@chili-chips.com
http://www.linkedin.com/in/jasminibrahimovic
7275 Calabria Court 65, San Diego, California 92122, Phone 858 535 9132
20 years in applied R&D with focus on Digital Design & Embedded Processing
Full development cycle with solid system, application & customer perspective
Pragmatic problem solver with extreme attention to detail & passion for excellence
Independent in execution, issue clearing, progress reporting, customer, vendor & team interactions
All phases of product development
Feature, Feasibility, Performance, Trade-off Analysis. Technology selection
System Partitioning & Architecture. Interfaces & Handshakes, at HW/FW, top and block level
Documentation & Specmanship
Logic & Timing Design. RTL coding. Verilog
Modeling & Functional Verification in comprehensive, self-checking simulations
Scripting. Constraint-driven Synthesis. Place-n-Route. Timing Analysis
Circuit & Schematics Design. Board supervision. Microcontrollers. Firmware coding
Interfacing & gluing the system together. High-Speed I/O, DDR & SerDes
Bring-up. HW/FW integration & debug. Lab hands-on
Networking (datacom/telecom). Exposure to video
Project/Team lead and liaison to third parties
Senior Consultant @ Chili.CHIPS
March 2009 – present, San Diego, California
Completed a number of Virtex5 (LX220, LX50, SXT50/ML506-Xtreme-DSP-Platform) projects, including: Custom I/O for an
embedded, mission-critical, COTS SBC built around Intel Mobile Core i7 architecture; Video capture from a
100fps, 15Mpix, 12-bit high-end camera chip; Data acquisition via PCI Express add-on card for a 64-bit
RAID 0 Linux PC
> Completed Intel MindShare training in PCI Express, including Gen2.0 additions
> Completed Altera training in Quartus II tool suite, C2H and PCIe on Arria2GX
Principal Design Engineer @ AMCC
July 2006 – March 2009, San Diego, California
Architected APB-based (AMBA3.0) control plane for a 4-million gate 10Gbps SR/LR/LRM/KR Ethernet PHY
in a 65nm ASIC-like flow. Used 8051 MCU @ 312MHz. Created IEEE802.3 Clause 45 MDIO IF and solved
access concurrency between on-chip and off-chip hosts. Automated CSR generation using Perl. Wrote
interface gaskets for all on-chip modules, including a 32-bit MACsec IP block. Devised transparent,
hardware-accelerated 8-to-16 bit bridging which boosted firmware throughput so that a low-end 8-bit
8051 core sufficed. Wrote APB, I2C, SPI and UART device drivers in Keil AX51 Assembly & C51 ‘C’
Integrated soft DDR2/3-SDRAM-controller and mixed-signal-PHY hard IP in a TSMC 90nm test chip, using
COT flow. Created comprehensive requirements specs for IP vendors and coordinated their deliverables.

Wrote DC synthesis and PTSI sign-off scripts in TCL & SDC and guided P&R towards timing closure. Worked
with Product and Test Engineering to characterize the IP, then assisted the (AXI-based) SoC to integrate it
Led prototyping of MoCA modem, which included MAC with QAM2to256 data pump in a Virtex4 LX200
FPGA baseband board and OFDM RF stage on a separate discrete board. Designed on-chip PowerPC 405
embedded subsystem with DMA-enabled packet buffering. PPC ran the MAC layer (soft, in firmware) and
DSP coefficient management. Worked very closely with firmware and DSP system engineers
Facilitated Simulink acceleration of a DFE/FFE CDR algorithm using a Virtex5 SXT50 FPGA (Xilinx ML506
board with System Generator & AccelDSP platform). Facilitated emulation of a Fractional PLL algorithm in FPGA
Used Synopsys DC Ultra, VCS, Prime Time SI, Formality; Mentor Precision RTL, QuestaSim with SV/SVA and
OVM; Cadence Incisive/NC-Log; SpringSoft Verdi. Worked with users of Cadence Virtuoso & Magma flows
> Received performance-based awards
Staff Engineer @ Copper Mountain Networks (now Motorola, Video Distribution Division)
October 2000 – June 2006, San Diego, California
Architected and implemented FPGA-hosted system-wide data plane Fabric for a NEBS-grade IPTV
switched video delivery system, BRAS and DSLAM. Wide disparity of cell, packet, TDM & streaming traffic
types converged in the Fabric where transformations, classification, routing, flow control & buffering were
done. The Fabric spanned some 20 different FPGA designs distributed across two flavors of Switch Card,
two flavors of Video Processor Card and an assortment of I/O Line Cards:
+) Video Processor Card, gen2: One Virtex2P7 hub with eighteen Spartan3_1500 access node FPGAs. Each Spartan
with two memory-mapped (EMIF/DMA) TI6415 DSP processors executing algorithms for bit-rate conditioning, channel
grooming, MPEG2/4 en/de/trans/coding...
+) Video Processor Card, gen1: Double Decker. Each deck with two Altera Stratix head-of-bus and six Cyclone access
node FPGAs. Each Cyclone has two satellite TI6415 DSPs
+) RF Line Cards (AMVSB, QAM, QPSK): Virtex2P7 FPGA with MPEG Transport Stream (MTS) LVDS interface to RF cans
+) Switch Card, gen 2: Two Virtex2P30, three Virtex2P7 FPGAs with on-chip 3.125GBaud SerDes. FPGAs interfaced to
two Intel IXP2800 Network Processors via 10Gbps CSIX
+) Switch Card, gen 1: Two Virtex2_6000 FPGAs, three Virtex2_1500, 24 ports of external Vitesse 1.25GBaud SerDes.
Interface to two Intel IXP1250 NPs via IXBus
+) GigE Line Card, gen 2: Virtex2P7 with XAUI interface to 12-port Broadcom Ethernet switch, I2C and Motorola
MPC850 QUICC Microcontroller. Gen1 was based on Virtex2_1000 & Intel 1000BT MAC
+) 10/100 Line Card: Virtex2P7 with SPI3 interface to two 8-port Ethernet MACs. FPGA was also responsible for packet
reassembly, VLAN lookup and throttle-based flow control
+) OC48 Line Card: Virtex2P7 with SPI3 interface to Intel SONET/SDH framer/mapper. Fourty-eight Virtual FIFOs
implemented in on-chip BRAMs for 48 logical ports in VC and GFP mode. OC12 and OC3 also supported. FPGA
featured discard-based congestion management scheme with proprietary on-chip CAM-like traffic classifier
+) DS3T1E1 Line Card: Virtex2_1500 with APPI and SBI interface to IMA_84/32, HDLC_84/32 and 3x AAL1_32
peripheral ASSPs. Side-port interface to an external QDR SRAM data storage element of 1024-port Virtual FIFO, each
2KByte deep. FPGA handled three traffic types: AAL5 ATM, Packet, AAL1 ATM and hosted discard flow control
+) OC3 Line Card: Virtex2_250 with POSPHY2 interface to 4-port OC3/STM1 framer/mapper
+) DS3/E3 Line Card: Virtex2_250 with Utopia2 interface to 4-port DS3/E3 framer/mapper
+) SHDSL; ADSL2; ADSL and Voice Processor Gateway Line Card: Virtex2_250 FPGA
MPEG Transport Stream (MTS) de-jittering circuit in a Virtex4 FX100 FPGA. Directly responsible for SerDes
front-end, packet reassembly and convergence of two time-shifted data-paths. Design was software-laden
and included two on-chip PowerPC 405 subsystems.
As the lead of a team of 3, defined & instituted FPGA development process for design correctness, re-use,
manageability & portability. This resulted in significant time-to-market edge
Set-up functional simulation framework. Its clean, structured, layered design and comprehensive scope
paid off in the rapid board bring-up and bug-free final product

Strove for simple excellence through meticulous analysis of the functions to implement. Was in that way
able to put more in less silicon and help the bottom line
Used ModelSim, Synplify, Xilinx ISE and Platform Studio
> Received formal training in System Verilog
> Received 'Leader of the Pack Award' for leading by example
> Received 'Certificate of Achievement' for succeeding to accommodate a major last-minute feature change
Senior Engineer @ Nortel Networks (Optical Networks Division)
July 1997 – Sept. 2000, Ottawa, Canada
Key contributor to an 11-million gate standard-cell SONET/SDH PHY chip in 150nm (all Cu) IBM ASIC node.
Responsible for clocking scheme (over 70 trees), all timing handoffs, TSI, Framer and liaison to mixed-signal
team designing a 2.5Gbps SerDes IP, which then integrated into main chip
Designed FPGA-assisted, software-driven numeric Stratum-3 PLL card, using Motorola Power QUICC
controller and an array of Actel MX36 FPGAs. Wrote all Verilog and some of the ‘C’ device drivers
Mentored junior designers
> Received formal training in Verilog, Advanced Verilog, C, Perl, Synopsys VCS, DC, Prime Time, (formerly)
Chrysalis Equivalence Checker, Nortel COT flow, Nortel DFT, RF I, RF II, Assertiveness, Negotiations
Senior Engineer @ Gandalf Data Ltd. (now Mitel, Communications Infrastructure Division)
Sept. 1993 – June 1997, Ottawa, Canada
Developed communications products (Terminal Server, Bridge, Router, ISDN, POTS) based on Intel
i960CF/HX RISC processor, Lucent (now Lattice) ORCA2C FPGAs, Altera FLEX8K FPGAs, Intel Flash EPLDs and
Altera MAX7K CPLD. Used Mentor, Viewlogic and OrCAD for circuit/schematics digital/analog design and
VHDL, AHDL, PALASM for programmable logic
> Received formal training in VHDL, Exemplar synthesis, ViewLogic and Mentor Design Architect schematics
Design Engineer @ Energoinvest/IRCA
May 1989 – March 1993, Sarajevo, Bosnia-Herzegovina
Developed communication products based on Intel 80188 processor & AMD PALs. Wrote device driver &
BIST functions in ASM86 as ‘C’ externs. Circuit & logic design in OrCAD & Able. Set up AX.25 RF network
BSEE, Control Theory & Electronics
Sept. 1984 - May 1989, University of Sarajevo, Bosnia-Herzegovina
Endorsed by US Department of Labor and University of Toronto, Canada. Graduated with Honors