3d ic

1,855 views
1,743 views

Published on

0 Comments
2 Likes
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total views
1,855
On SlideShare
0
From Embeds
0
Number of Embeds
5
Actions
Shares
0
Downloads
376
Comments
0
Likes
2
Embeds 0
No embeds

No notes for slide

3d ic

  1. 1. 3d ictechnology SAMBIT PATNAIK M.Tech Sem-2 1
  2. 2. outline 3D IC’sConcept of integrated micro channel coolingFabrication processTheoretical analysisExperimental characterizationBenefitsChallengesApplicationsConclusion 2
  3. 3. Three Dimensional Integrated Circuits Technology The 3d ic is a chip with two or more layers ofactive electronic components, integrated bothvertically and horizontally into a single circuit. An electronic components is a basic elementusually packed in a discrete form with two ormore connecting leads. Some active components are likesemiconductors and vacuum tubes those whohave gain or directionality. About micro channel by definition it states thatany channel with less than 1 mm and greater than1 μm can be called as micro channel. Currently most micro channel fall in the rangeof 30 to 300 μm. 3
  4. 4. Concept 4
  5. 5. The concept behindmicro channel cooling3d ic technology areillustrated in the givenfig 1:Cooling fluid can be delivered to the 3d stack eitherby using tubes on the back side of the stack or byusing fluidic channels on the substrate.This fluid is then delivered to micro channel heatsink on the back side of each chip through silicon vias(TSVs) and fluidic pipes.Electric TSVs are present to communicate betweendifferent chips. 5
  6. 6. Fabrication processi) Chip level fabrication technologyii) I/O and Assembly technology 6
  7. 7.  It starts with the fabricationof electrical TSVs on a waferafter FEOL and BEOLprocesses. Bosch process is utilizedfor etching fluidic TSVs andmicro channel. The polymer material likeUnity is spin coated on themicro channels and arepolished. A polymer like Avatrel isthen spun on, patterned andcured to form a cover for themicro channels and fluidicTSVs. 7
  8. 8.  Unity is then decomposed by heating it to 260degree centigrade The image below is the sample after the chip levelfabrication process is complete. The entire process is outlined at less than 260degree centigrade which makes it compatible withCMOS. The fluidic processes at the wafer level makes theprocess economically feasible. 8
  9. 9.  The fluidic pipes arefabricated with polymer suchas Avatrel for the top chip intwo chip 3d stack after solderbumping. The bottom chip is firstassembled onto the substratewith a flip chip bonder. The top chip in 3d stack isassembled onto the bottomchip. The under lining betweenthe two chip is dispensed toseal fluidic pipes and controlthe co-efficient of thermalexpansion mismatch between 9the chip and the substrate.
  10. 10. 10
  11. 11. THEORETICAL ANALYSIS 11
  12. 12. Using these two equations determine the path way offluid from external tube to the die. Here Re is Reynolds number, f is a friction factor, Wcand Hc are width and height of each micro channel,ηvia/pipe is the number of fluidic TSVs , Dvia/pipe is theinner diameter of fluidic TSVs, ηc is the number of microchannels on each chip, Hvia-pipe-ηtotal is the total lengthof fluidic TSVs/pipes for the die having longest fluidicpathway. 12
  13. 13. Now substituting the values ofLc=10mm,Wc=100mm,Hc=200um,Dvia/pipe=250um,Hvia-pipe-total=0.9mm(for 400um silicon chips),ηc=2nvia/pipe=50,we get 13
  14. 14. Experimental Characterization 14
  15. 15.  The thermal resistance for each chip in a two chip3d-IC may be approximated by measuring propertiesof single micro channel heat sink.Platinum thin film resistors were fabricated on a chipwith a micro channel heat sink to facilitate thismeasurement. Chip was packed and copper pads on the siliconsubstrate were used to deliver current to the platinumresistors and monitor their resistance. Platinum thin film resistor are used in fabrication. Deionized water must be circulated through microchannels at 65 ml/min 15
  16. 16. 3D Ic Integration 16
  17. 17. 3D Ic Packaging 17
  18. 18. Benefits 3d ic provide significant benefits to high performanceservers. The chip to chip interconnect is less as compared to 2dic. The thermal resistance is low.The performance, power and operation temperaturecan be obtained for each chip of a 65 nm micro channelcooled 3d-ic. 18
  19. 19. 19
  20. 20. 20
  21. 21. Challenges During fabrication process, cleanliness is required.Care must be taken during the delivery and extractionof cold to hold liquid from the micro channel heat sink. 21
  22. 22. ApplicationsHigh performance servers 22
  23. 23. A 65 nm micro channel cooled 3D-IC 23
  24. 24. Conclusion The 3d ic technology is considered as a breakthrough technology with a promising potential. The micro channel cooled 3d ic provides less chipto chip interconnect length. With shorter interconnect in 3d ic , the switchingenergy and cycle time is expected to reduced.It also gives improved thermal resistance then theair cooled 2d servers. The technology is more reliable . 24
  25. 25. References Deepak Sarkar , Kalvin King, Bing Dang, et al, “A3D-IC Technology with Integrated Micro channelCooling”, Georgia Institute of Technology ,IBMRESEARCH, Nan nexus Inc ,IEEE, pp-13-15,yy-JAN2008. S.Garimella, et al, proc, IEEE, Aug 2006 J.Early, proc, ISSCC, 1960.B.Dang, PhD dissertation, Georgia Tech, 2006.D.Tuckerman, F. Pease, Electron Device Letters,Vol.27, 2006 25
  26. 26. 26

×