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Điện tử số thầy Phạm Ngọc Nam.

Điện tử số thầy Phạm Ngọc Nam.

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    Điện tử số thầy Phạm Ngọc Nam. Điện tử số thầy Phạm Ngọc Nam. Presentation Transcript

    • ©R.LauwereinsImec 2001 Course contentsDigital • Digital designdesign • Combinatorial circuits: without statusCombina-torial • Sequential circuits: with statuscircuits • FSMD design: hardwired processorsSequentialcircuits  Language based HW design: VHDLFSMDdesignVHDL5/1
    • Language based HW design:©R.LauwereinsImec 2001 a VHDL primerDigital • Introductiondesign • A first look at VHDLCombina-torial • Signals and data typescircuits • VHDL operatorsSequentialcircuits • Concurrent versus sequential statementsFSMDdesign • Sequential construction statementsVHDL • Higher performance, less portability: e.g. synthesis issues for Xilinx5/2
    • Language based HW design:©R.LauwereinsImec 2001 a VHDL primerDigital  Introductiondesign • A first look at VHDLCombina-torial • Signals and data typescircuits • VHDL operatorsSequentialcircuits • Concurrent versus sequential statementsFSMDdesign • Sequential construction statementsVHDL • Higher performance, less portability: e.g. synthesis issues for Xilinx5/3
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • Acronym:design  VHDL = VHSIC Hardware Description LanguageCombina-  VHSIC = Very High Speed Integrated Circuittorialcircuits • What is VHDL?  A programming language for describing the behaviorSequentialcircuits of digital systems  Design entry language, used forFSMDdesign  Unambiguous specification at behavioral and RTL levelVHDL  Simulation (executable specification…)  Synthesis  Documentation • Standardisation: IEEE 1076  First version: 1986  Second version: 1993  New version about to appear5/4
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • When to use VHDL instead ofdesign schematics?Combina-  Drawbacks:torialcircuits  VHDL is easy to learn but hard to master (semantics are quite different from softwareSequential languages)circuits  VHDL has a difficult syntax (Language sensitiveFSMD editors with templates for all languagedesign constructs)  VHDL is very ‘wordy’: lots of code to type for justVHDL a few simple things  A list of instructions is less intuitive to understand than a block diagram for a human being  VHDL is designed to make simulation efficient: contains aspects that have hardly anything to do with hardware behavior, but is useful to speed-up event driven simulation5/5
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • When to use VHDL instead ofdesign schematics?Combina-  Easier to capture complex circuits: higher leveltorialcircuits of abstraction with automated synthesis you specify ‘add’ instead of jottingSequentialcircuits down a specific type of adder: theFSMD synthesis tool will instantiate thedesign best type of adder under timing, areaVHDL & power constraints easy to parametrise (e.g. word length, queue depth) easy to specify arrays of components  Portable across many tools for simulation, synthesis, analysis, verification, … of different5/6
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • Limitations of VHDLdesign  The standard only describes syntax andCombina- semantics, but not the coding styletorial  you can specify the same behavior (e.g. MUX) incircuits an almost unlimited number of waysSequential  each leading to a completely differentcircuits implementation (e.g. Multiplexor or tri-state bus)  which is synthesis tool dependent.FSMDdesign  You should do lots of experimentation with style- tool combinations to be able to predict how theVHDL hardware will look like that will be synthesised. Is prediction necessary? You also do not predict the ASM generated by C; C is less efficient than ASM but faster to write. Currently, it is hard to tolerate the inefficiency caused by the higher level specification for hardware.  Note: for DSP processors programmed in C, we do predict ASM and have to experiment with style-5/7 compiler combinations for efficiency reasons!!
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • Limitations of VHDL (ctud)design  Only a subset of VHDL can be automaticallyCombina- synthesised; each vendor supports a differenttorial subsetcircuits  Only digital; special extension (not yet widelySequential adopted) for analog: VHDL-AMS (acronym forcircuits VHDL Analog and Mixed Signal)FSMDdesign IEEE standard 1076.1-1999 is a super-set of the full IEEE VHDLVHDL 1076-1993 standard for digital design5/8
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • Abstraction levelsdesign  BehavioralCombina- Interconnected functionstorialcircuits Only info on functions or algorithmsSequential (what)circuits Only timing needed to let theFSMDdesign function work correctly OK for VHDLVHDL Behavioral synthesisers immature; used for high level executable specification in top-down design and manual synthesis into RTL5/9
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • Abstraction levelsdesign  RTLCombina-  Interconnected registers and combinatorial unitstorialcircuits  Info on function (what) and architecture (how)  Cycle accurateSequential  No technology dependent timing infocircuits  OK for VHDLFSMD  Good synthesisersdesign  Gate levelVHDL  Interconnected gates and flip-flops  Info on function and architecture  Info on technology dependent timing (gate delays)  Layout  Info on layout on silicon  Continuous timing5/10  Analog effects
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • Other hardware description languagesdesign (HDL)Combina-  Verilogtorialcircuits More widespread in USA than inSequential Europecircuits Often required for gate level or RTLFSMD level ASIC sign-offdesign Never ending discussion which isVHDL better  PLD languages like ABEL, PALASM, … These are more at the gate level, capturing also technology dependent features (e.g. detailed timing)5/11
    • ©R.LauwereinsImec 2001 VHDL primer: IntroductionDigital • Difference between HDLs and traditionaldesign software programming languagesCombina-  Concurrency: all hardware components operatetorialcircuits in parallel  Data types: support is needed for arbitrary sizeSequentialcircuits integers, bit vectors, fixed point numbers  Concept of timeFSMDdesignVHDL5/12
    • Language based HW design:©R.LauwereinsImec 2001 a VHDL primerDigital • Introductiondesign  A first look at VHDLCombina-torial • Signals and data typescircuits • VHDL operatorsSequentialcircuits • Concurrent versus sequential statementsFSMDdesign • Sequential construction statementsVHDL • Higher performance, less portability: e.g. synthesis issues for Xilinx5/13
    • A First look at VHDL:©R.LauwereinsImec 2001 Example 1 task descriptionDigital • Design a circuit named ‘Test’ with 3 8-bitdesign inputs (In1, In2, In3) and two booleanCombina- outputs (Out1, Out2). The first outputtorialcircuits equals ‘1’ when the first and second input are equal; the second output equals ‘1’Sequentialcircuits when the first and third input are equal.FSMD • Let’s first make a schematic design:designVHDL5/14
    • A First look at VHDL:©R.LauwereinsImec 2001 Schematic specificationDigital • The circuit will be hierarchicallydesign decomposed into a top level componentCombina- ‘Test’ containing 2 instantiations of atorialcircuits comparator component ‘Compare’Sequentialcircuits Test CompareFSMD In1 Out1design A EQVHDL B In2 Compare A In3 EQ Out2 B5/15
    • A First look at VHDL:©R.LauwereinsImec 2001 Schematic specificationDigital • The comparator is then hierarchicallydesign decomposed into a gate levelCombina- combinatorial circuittorialcircuits CompareSequentialcircuits A[0] XNOR AFSMD B[0]design A[1] ANDVHDL EQ B[1] EQ B A[7] B[7]5/16
    • A First look at VHDL:©R.LauwereinsImec 2001 Entity and ArchitectureDigital • Declaration of the ‘Compare’ designdesign entity: ‘Entity’ specifiesCombina- the interfacetorial -- Eight bit comparator to the circuit, thecircuits -- black box of a entity Compare is schematicSequential port( A,B: in bit_vector(0 to 7);circuits EQ: out bit); Input and output end entity Compare; signals are calledFSMD ‘ports’design architecture Behav1 of Compare is begin ‘Architecture’ describesVHDL EQ <= ‘1’ when (A=B) else ‘0’; the behavior and structure end architecture Behav1; of the entity, Notes: the internals of the box - Multiple architectures per entity are possible: different ways of implementing same behavior - This architecture specifies behavior at RTL level and not the actual structure of gates; synthesis tool will automatically translate this RTL behavioral description into gate level5/17 - Ports have an explicit direction and are (vectors of) bits
    • A First look at VHDL:©R.LauwereinsImec 2001 Component and InstantiationDigital • Specification of the next higher level indesign the circuit hierarchy: ‘Test’ Virtual device: allows -- Dual comparator Test componentCombina- for concurrenttorial -- development of bothcircuits entity Test is hierarchical levels, port( In1,In2,In3: in bit_vector(0 to 7); by different persons.Sequential Out1,Out2: out bit); ‘Comparator’ will becircuits end entity Test; bound to ‘Compare’ laterFSMD architecture Struct1 of Test isdesign component Comparator is port( X,Y: in bit_vector(0 to 7); Two instantiationsVHDL Z: out bit); of the same component end component Comparator; ‘Comparator’ with its begin signal binding Compare1: component Comparator port map (In1,In2,Out1); Compare2: component Comparator port map (In1,In3,Out2); end architecture Struct1; Notes: - The two ‘comparator’ components work concurrently!!! - This architecture describes structure, i.e. how this entity5/18 consists of an interconnection of lower level components
    • A First look at VHDL:©R.LauwereinsImec 2001 Comparison with CDigital • This is very similar to softwaredesign programming languages, e.g. CCombina-torial /* Eight bit comparatorcircuits */ Interface to the function int CompareSequential (int A, int B)circuits Inputs and outputs are called ‘arguments’ {FSMDdesign return (A == B); Behavior of the function }VHDL Notes: - Only one behavior per function possible - Behavior is specified at rather high level and will be automatically translated by the compiler into ASM instructions - Function arguments do not have a direction and are of type int5/19
    • A First look at VHDL:©R.LauwereinsImec 2001 Comparison with CDigital • This is how the higher hierarchical leveldesign looks like in CCombina- /* Dual comparator Test programtorial */circuits main()Sequential {circuits Two calls to the function int In1, In2, In3; ‘Compare’ with its int Out1, Out2; argument bindingFSMDdesign Out1 = Compare(In1, In2);VHDL Out2 = Compare(In1, In3); } Notes: - The two ‘compare’ function calls are executed sequentially - This main program is executed once and stops. In VHDL, all components describe relations that are valid continuously and forever5/20
    • A First look at VHDL:©R.LauwereinsImec 2001 ConfigurationDigital • When an entity has multipledesign architectures, how do you indicate whichCombina- one to use?torialcircuits • How do you bind ‘Components’ toSequential ‘Entities’?circuits -- Configuration information: architecture selection -- and component-entity bindingFSMD Both ‘use entity’s coulddesign be combined in one: configuration Build1 of Test is for All: Comparator ... for Struct1VHDL for Compare1: Comparator use entity Compare(Behav1) port map (A => X, B => Y, EQ => Z); end for; for others: Comparator use entity Compare(Behav1) port map (A => X, B => Y, EQ => Z); end for; end for; end configuration Build1;5/21 Note: ‘configuration’ corresponds in SW to ‘linking’
    • A First look at VHDL:©R.LauwereinsImec 2001 SyntaxDigitaldesign ENTITY:Combina-torial entity Entity_name iscircuits port( Signal_name: in Signal_type; Signal_name: out Signal_type);Sequentialcircuits end entity Entity_name;FSMDdesign ARCHITECTURE:VHDL architecture Architecture_name of Entity_name is local_signal_declarations; component_declarations; begin statements; end architecture Architecture_name;5/22
    • A First look at VHDL:©R.LauwereinsImec 2001 SyntaxDigital COMPONENT:design component Component_name is port( Signal_name: in Signal_type;Combina- Signal_name: out Signal_type);torial end component Component_name;circuitsSequential COMPONENT INSTANTIATION:circuits -- component instantiation Instance_name: component Component_nameFSMD port map (Signal_list);design or -- direct instantiationVHDL Instance_name: entity Entity_name(Architecture_name) port map (Signal_list); Name used in SIGNAL LIST: component declaration -- two variants: -- variant 1: ordered list of signals as in software languages -- e.g. (In1,In2,Out1) -- variant 2: named list Locally used name -- e.g. (B => In2, EQ => Out1, A => In1)5/23
    • A First look at VHDL:©R.LauwereinsImec 2001 SyntaxDigitaldesign CONFIGURATION:Combina- configuration Config_name of Entity_name istorial for Architecture_namecircuits for Instance_name: Component_name use entity Entity_name(Architecture_name)Sequentialcircuits port map (Signal_list); end for; end for;FSMDdesign end configuration Config_name;VHDL5/24
    • A First look at VHDL:©R.LauwereinsImec 2001 Example 2Digital • Declare a 3-input AND gatedesignCombina- A Ytorial Bcircuits CSequentialcircuits -- 3-input AND gate entity AND3 isFSMDdesign port ( A,B,C: in bit; Y: out bit);VHDL end entity AND3; architecture RTL of AND3 is begin Y <= ‘1’ when ((A=‘1’) and (B=‘1’) and (C=‘1’)) else ‘0’; end architecture RTL;5/25
    • A First look at VHDL:©R.LauwereinsImec 2001 Example 2Digital • Declare a 3-input OR gatedesignCombina- A Ytorial Bcircuits CSequentialcircuits -- 3-input OR gate entity OR3 isFSMDdesign port ( A,B,C: in bit; Y: out bit);VHDL end entity OR3; architecture RTL of OR3 is begin Y <= ‘0’ when ((A=‘0’) and (B=‘0’) and (C=‘0’)) else ‘1’; end architecture RTL;5/26
    • A First look at VHDL:©R.LauwereinsImec 2001 Example 2Digital • Declare an INV gatedesignCombina-torial A YcircuitsSequentialcircuits -- INV gate entity INV isFSMDdesign port ( A: in bit; Y: out bit);VHDL end entity INV; architecture RTL of INV is begin Y <= ‘1’ when (A=‘0’) else ‘0’; end architecture RTL;5/27
    • A First look at VHDL:©R.LauwereinsImec 2001 Example 3Digital • Build a 2-to-1 MUX using both adesign behavioral as well as a structuralCombina- descriptiontorial Acircuits Y BSequentialcircuits S entity MUX21 is The black box port ( A,B,S: in bit; interfaceFSMDdesign Y: out bit); end entity MUX21;VHDL architecture Behav of MUX21 is begin Behavioral description Y <= A when (S=‘1’) else B; end architecture Behav;5/28
    • A First look at VHDL:©R.LauwereinsImec 2001 Example 3Digital • Build a 2-to-1 MUX using both a behav. asdesign well as a structural description A YCombina- architecture Struct of MUX21 is Btorial signal U,V,W : bit;circuits component AND2 is S port ( X,Y: in bit;Sequential Z: out bit); Structural descriptioncircuits end component AND2; component OR2 is AFSMD port ( X,Y: in bit; Wdesign Z: out bit); S Y end component OR2;VHDL component INV is U V port ( X: in bit; Z: out bit); B end component INV; begin Gate1: component INV port map (X=>S,Z=>U); Gate2: component AND2 port map (X=>A,Y=>S,Z=>W); Gate3: component AND2 port map (X=>U,Y=>B,Z=>V); Gate4: component OR2 port map (X=>W,Y=>V,Z=>Y);5/29 end architecture Struct;
    • A First look at VHDL:©R.LauwereinsImec 2001 Example 3Digital • Assume that we want to use thedesign previously declared AND3, OR3 and INVCombina- for this structural description of MUXtorialcircuits configuration Use3InputGates of MUX21 isSequential for Behav Entitiescircuits A end for; Y for Struct BFSMD for Gate1:INV use entity INV(RTL) Cdesign port map (A=>X,Y=>Z); end for; A YVHDL for All:AND2 use entity AND3(RTL) port map (A=>X,B=>Y,C=>’1’,Y=>Z); end for; for Gate4:OR2 use entity OR3(RTL) Components port map (A=>X,B=>Y,C=>’0’,Y=>Z); X end for; Z end for; Y end configuration Use3InputGates; X Z5/30
    • A First look at VHDL:©R.LauwereinsImec 2001 Test benchDigital • How can we verify the circuit that wedesign made?Combina-  We have to apply representative stimulitorialcircuits  to the circuit  and check whether the outputs are correctSequentialcircuits • A VHDL ‘test bench’ can be considered toFSMD be the top level of a designdesign  It instantiates the Design Under Test (DUT)VHDL  applies stimuli to it  checks whether the stimuli are correct or  captures the outputs for visualisation in a waveform viewer5/31
    • A First look at VHDL:©R.LauwereinsImec 2001 Test benchDigital • Create a test bench for the behavioraldesign version of the MUXCombina- entity Testbench is Testbench is Atorialcircuits end entity Testbench; self-contained: Y B MUX21 no portsSequentialcircuits SFSMD architecture BehavTest of Testbench isdesign Signal In1,In2,Select,Out : bit; beginVHDL DUT: entity MUX21(Behav) port map (In1, In2, Select, Out); Stimulus: process is begin In1<=‘0’;In2<=‘1’;Select<=‘0’; wait for 20 ns; Select<=‘1’; wait for 20 ns; In1<=‘1’;In2<=‘0’; wait for 20 ns; ... end process Stimulus; end architecture BehavTest;5/32
    • A First look at VHDL:©R.LauwereinsImec 2001 Re-useDigital • Often, parts of a design can be re-used indesign another designCombina-torial • New products in industry often containcircuits 95% of re-used parts and 5% is newlySequential designed: evolutionary design • VHDL encourages this by the concept ofcircuitsFSMD ‘Packages’design • A ‘Package’ contains definitions ofVHDL constant values, component declarations, user data types, and sub-programs of VHDL code • But first the concept ‘Library’: a library is name of directory into which the binary code resulting from analysis/compilation5/33 is stored. Default: WORK
    • A First look at VHDL:©R.LauwereinsImec 2001 Re-useDigital Package interface declaration:design package Package_name isCombina- -- constantstorial -- user defined typescircuits -- component declarations -- sub programsSequential end package Package_name;circuitsFSMDdesignVHDL How to use a package? use Library_name.Package_name.all; … U1: entity Package_name.Entity_name(Architecture_name);5/34
    • Language based HW design:©R.LauwereinsImec 2001 a VHDL primerDigital • Introductiondesign • A first look at VHDLCombina-torial  Signals and data typescircuits • VHDL operatorsSequentialcircuits • Concurrent versus sequential statementsFSMDdesign • Sequential construction statementsVHDL • Higher performance, less portability: e.g. synthesis issues for Xilinx5/35
    • Signals and Data Types:©R.LauwereinsImec 2001 Predefined signal typesDigital package Standard isdesign type Bit is (‘0’,’1’); type Boolean is (False, True);Combina- type Character is (--ASCII set);torial type Integer is range implementation_defined;circuits type Real is range implementation_defined; type Bit_vector is (--array of bits);Sequentialcircuits type String is (--array of characters); type Time is range implementation_defined;FSMD end package Standard;design Bit, Boolean and Character are enumeration typesVHDL All standard types are ‘unresolved’ (see later for the meaning of this)5/36
    • Signals and Data Types:©R.LauwereinsImec 2001 Predefined signal typesDigitaldesign Examples of integer declarations: type Year is range 0 to 99;Combina- type Memory_address is range 65535 downto 0;torialcircuits Checked by simulator Examples of real declarations:Sequentialcircuits type Probability is range 0.0 to 1.0; type Input_level is range -5.0 to 5.0;FSMDdesign A Bit_vector is a collection of bits; a value is specified betweenVHDL double quotes: constant State1: bit_vector(4 downto 0) := “00100”; MSB, bit 4 LSB A String is a collection of characters; a value is specified between double quotes: constant Error_message: string := “Unknown error: ask your poor sysop for help”;5/37
    • Signals and Data Types:©R.LauwereinsImec 2001 Predefined signal typesDigitaldesign Time is a physical type: type Time is range implementation_definedCombina- unitstorial fs; Primary unit:circuits ps = 1000 fs; resolution limit ns = 1000 ps;Sequential us = 1000 ns;circuits ms = 1000 us; Secondary units sec = 1000 ms;FSMD min = 60 sec;design hr = 60 min; end units;VHDL Examples of use: wait for 20 ns; constant Sample_period: time := 2 ms; constant Clock_period: time := 50 ns;5/38
    • Signals and Data Types:©R.LauwereinsImec 2001 User defined physical typesDigitaldesign The user may define his/her own physical types: type Length is range 0 to 1E9Combina- units Primary unit:torial um; resolution limitcircuits mm = 1000 um; m = 1000 mm; Metric secondary unitsSequential km = 1000 m;circuits mil = 254 um; inch = 1000 mil;FSMD foot = 12 inch;design Imperial secondary units yard = 3 foot; end units;VHDL5/39
    • Signals and Data Types:©R.LauwereinsImec 2001 User defined enumeration typesDigitaldesign The user may define his/her own enumeration types: type FSM_states is (reset, wait, input, calculate, output);Combina-torialcircuits Not all synthesis tools support enumerated typesSequentialcircuits When they do support them, the default encoding is often straightforward encoding using the minimum number of bitsFSMDdesign Often, the default encoding may be over-written by somewhere specifying something like “encoding_style is gray_code” or byVHDL explicitly specifying the encoding for each possible value: constant reset: bit_vector := “10000”; constant wait: bit_vector := “01000”; constant input: bit_vector := “00100”; constant calculate: bit_vector := “00010”; constant output: bit_vector := “00001”;5/40
    • Signals and Data Types:©R.LauwereinsImec 2001 Array typesDigitaldesign The user may define arrays of types: type 1D_array is array (1 to 10) of integer;Combina- type 2D_array is array (5 downto 0, 1 to 10) of real;torialcircuits Keep in mind that a vector of bits has NO numerical meaningSequentialcircuits and that hence arithmetic operations on vectors of bits make no sense:FSMDdesign signal Bus,Address : bit_vector (0 to 3);VHDL Bus <= Address + 1; -- This makes no sense!!! Solution: via operator overloading (cf. C++): - two functions ‘+’ will exist, one working on integers and one working on vectors of bits - the latter is defined in a vendor specific ‘vector arithmetic package’ that should be use’d at the beginning of your VHDL5/41
    • Signals and Data Types:©R.LauwereinsImec 2001 Standard logicDigital • We have seen that we need more logicdesign levels than just ‘0’ and ‘1’ (e.g. don’t care,Combina- unknown after setup violation, …)torialcircuits • Therefore the IEEE defined in standardSequential number 1164 9-valued logic signals andcircuits operations on them: use always thoseFSMD instead of ‘bit’!!design • Exists in unresolved form (std_ulogic) andVHDL resolved form (std_logic) -- again: see later for meaning • Exists in single bit and array form:  constant A: std_ulogic := ‘U’; -- unitialized  constant B: std_logic := ‘U’;  constant C: std_ulogic_vector (0 to 15);5/42  constant D: std_logic_vector (15 downto 0);
    • Signals and Data Types:©R.LauwereinsImec 2001 Standard logicDigitaldesign library IEEE; use IEEE.Std_logic_1164.All;Combina-torial type std_logic is (circuits ‘U’, -- uninitialized e.g. after power-up ‘X’, -- strongly driven unknown e.g. after setup violationSequentialcircuits ‘0’, -- strongly driven logic zero ‘1’, -- strongly driven logic oneFSMD ‘Z’, -- high impedance e.g. not driven at alldesign ‘W’, -- weakly driven unknown ‘L’, -- weakly driven logic zeroVHDL ‘H’, -- weakly driven logic one ‘-’); -- don’t care5/43
    • Signals and Data Types:©R.LauwereinsImec 2001 Assignment to signalsDigital Is the following code valid?design signal Z,A,B: std_ulogic;Combina-torial Z <= A;circuits Z <= B;Sequentialcircuits No, because: - all statements are concurrently valid and are not executedFSMD sequentially as in SW languagesdesign - when A=‘0’ and B=‘1’, we have a short circuitVHDL A A Resolver circuit R Z Z B B5/44
    • Signals and Data Types:©R.LauwereinsImec 2001 Assignment to signalsDigital • VHDL is a single assignment language fordesign unresolved data typesCombina-torial • For resolved data types (std_logic &circuits std_logic_vector), the resolver circuit isSequential inferred by the synthesis toolcircuitsFSMDdesign A Resolver signal Z,A,B: std_logic; circuitVHDL Z <= A; R Z <= B; B Z5/45
    • Signals and Data Types:©R.LauwereinsImec 2001 Assignment to signalsDigital • When an array is assigned to anotherdesign array, both arrays must have same sizeCombina-torial • Assignment is by position, not by index!!!circuits signal Down: std_logic_vector (3 downto 0);Sequential signal Up: std_logic_vector (0 to 3);circuits Up <= Down;FSMDdesign Which of the two following interpretations is correct?VHDL Up(0) Down(3) Up(0) Down(0) Up(1) Down(2) Up(1) Down(1) OR Up(2) Down(1) Up(2) Down(2) Up(3) Down(0) Up(3) Down(3)5/46 Correspondence by position!
    • Signals and Data Types:©R.LauwereinsImec 2001 Assignment to signalsDigital • Assignment to a part of an array isdesign possibleCombina-torial • Make sure that the direction (to orcircuits downto) is the same as in the declarationSequential signal Bus: std_logic_vector (7 downto 0);circuits signal A: std_logic_vector (0 to 3);FSMD Which of the following VHDL codes is correct?design Bus(0 to 3) <= A; Direction of Bus differs from declarationVHDL Bus <= A; Array sizes do not match Bus(3 downto 0) <= A; OK! Bus(3) is driven by A(0) Bus(5 downto 4) <= A(0 to 1); OK! Bus(5) is driven by A(0) Bus(5 downto 4) <= A(0 to 1); OK! Bus(4) is driven by A(1) Bus(4 downto 3) <= A(2 to 3); and by A(2): resolved data5/47 type… use with care!!
    • Signals and Data Types:©R.LauwereinsImec 2001 Assignment to signalsDigital • ‘Concatenation’: bring wire bundlesdesign together to assign them to a bigger arrayCombina- signal Byte_bus: std_logic_vector(7 downto 0);torialcircuits signal Nibble_busA, Nibble_busB: std_logic_vector(3 downto 0); Byte_bus <= Nibble_busA & Nibble_busB;Sequentialcircuits Nibble_busA(3)FSMD Nibble_busA(2)design Byte_bus(7) Nibble_busA(1) Byte_bus(6) Nibble_busA(0)VHDL Byte_bus(5) Byte_bus(4) Byte_bus(3) Byte_bus(2) Byte_bus(1) Nibble_busB(3) Byte_bus(0) Nibble_busB(2) Nibble_busB(1) Nibble_busB(0)5/48
    • Signals and Data Types:©R.LauwereinsImec 2001 Assignment to signalsDigital • ‘Aggregation’: alternative method todesign assign multiple small arrays to a biggerCombina- arraytorialcircuits • Not supported by all synthesis tools!!Sequentialcircuits signal X,Y,Z,T: std_logic_vector(3 downto 0); signal A,B,C: std_logic;FSMDdesign X <= (A,B,C,C); -- correspondence by positionVHDL Y <= (3 => A, 1 downto 0 => C, 2 => B); Z <= (3 => A, 2 => B, others => C); T <= (others => ‘0’); -- initialization irrespective of width of T5/49
    • Signals and Data Types:©R.LauwereinsImec 2001 Generic constantsDigital • Allows to parameterize behaviordesign • Enables re-use of entities in slightlyCombina-torial changing environmentscircuits • Makes VHDL much more powerful thanSequential schematic entrycircuits • Generic constants need to have a value atFSMDdesign synthesis time! entity General_mux isVHDL generic (width : integer); port ( Input : in std_logic_vector (width - 1 downto 0); Select : in integer range 0 to width - 1; Output : out std_logic); end entity General_mux;5/50
    • ©R.LauwereinsImec 2001 Generic constants entity General_mux is generic (width : integer); port ( Input : in std_logic_vector (width - 1 downto 0);Digital Select : in integer range 0 to width - 1;design Output : out std_logic); end entity General_mux; This is not valid VHDL:Combina- index is not known attorial architecture Behav of General_mux is design time! We willcircuits begin replace this by valid Output <= Input(Select); code later!Sequentialcircuits end architecture Behav; entity Testbench isFSMDdesign end entity Testbench; architecture Build1 of Testbench isVHDL constant Input_size : integer := 8; signal A : std_logic_vector (Input_size-1 downto 0); signal S : integer range 0 to Input_size - 1; signal B : std_logic; begin DUT: entity General_mux(Behav) generic map (width => Input_size) port map (Input => A, Select => S, Output => B); ...5/51 end architecture Build1;
    • Language based HW design:©R.LauwereinsImec 2001 a VHDL primerDigital • Introductiondesign • A first look at VHDLCombina-torial • Signals and data typescircuits  VHDL operatorsSequentialcircuits • Concurrent versus sequential statementsFSMDdesign • Sequential construction statementsVHDL • Higher performance, less portability: e.g. synthesis issues for Xilinx5/52
    • ©R.LauwereinsImec 2001 Logical OperatorsDigital • List of logical operators: not, and, or, xor,design nand, norCombina-torial • Precedence:circuits  ‘not’ has highest precedenceSequential  all others have equal precedence, lower thancircuits ‘not’FSMD • Logical operators are predefined fordesign following data types: bit, bit_vector,VHDL boolean, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector • A logical operator may work on an array:  arrays should have same size  elements are matched by position5/53
    • ©R.LauwereinsImec 2001 Logical OperatorsDigitaldesign library IEEE;Combina- use IEEE.Std_Logic_1164.All;torialcircuits entity Gate isSequential port( A,B,C: in std_logic;circuits Z: out std_logic); end entity Gate;FSMDdesign architecture Logical of Gate is beginVHDL Z <= A and not(B or C); end architecture Logical;5/54
    • ©R.LauwereinsImec 2001 Logical OperatorsDigitaldesign library IEEE;Combina- use IEEE.Std_Logic_1164.All;torialcircuits entity Gate is generic(width : integer range 0 to 31);Sequential port( A,B,C: in std_logic_vector(width-1 downto 0);circuits Z: out std_logic_vector(width-1 downto 0)); end entity Gate;FSMDdesign architecture Logical of Gate is beginVHDL Z <= A and not(B or C); end architecture Logical;5/55
    • ©R.LauwereinsImec 2001 Relational OperatorsDigital • List of relational operators: <, <=, =>, >, =,design /=Combina-torial • Relational operators return a booleancircuits • Both operands need to be of the sameSequential typecircuits • A relational operator may work on anFSMDdesign array:  arrays may have different size!!VHDL  They are left alligned and the number of bits equal to the smallest array are compared; the comparison is done bit by bit, from left to right  Remember: vectors of bits do not have a numerical meaning!! However, this comparison works on vectors of bits with the meaning of an unsigned integer when both vectors have5/56 equal length
    • Relational Operators©R.LauwereinsImec 2001 library IEEE use IEEE.Std_Logic_1164.All;Digital What is thedesign entity Compare is value of Z? port( A: in std_logic_vector(3 downto 0); B: in std_logic_vector(0 to 4); TRUE?Combina-torial Z: out boolean); FALSE?circuits end entity Compare;Sequential architecture Relational of Compare is 1110circuits begin is compared to Z <= TRUE when A<B else FALSE; 1011FSMDdesign end architecture Relational; by bit position from left to entity Testbench right;VHDL end entity Testbench; in the 2nd position architecture Build1 of Testbench is A(2) > B(1) signal A: std_logic_vector(3 downto 0) := “1110”; hence (A<B) signal B: std_logic_vector(0 to 4) := “10111”; is FALSE signal Z: boolean; begin DUT: entity Compare(Relational) port map (A => A, B => B, Z => Z);5/57 end architecture Build1;
    • ©R.LauwereinsImec 2001 Arithmetic OperatorsDigital • List of arithmetic operators: +, -, *, /, **design (exponential), abs (absolute value), modCombina- (modulus), rem (remainder)torialcircuits • They are defined on types integer andSequential real (except mod and rem) and not oncircuits vectors of bits; use overloading packageFSMD for the latter (vendor dependent)design • Both operands have to be of same type;VHDL different ranges are allowed • A variable of physical type (e.g. time) may be multiplied by an integer or real and will still return a variable of the physical type5/58
    • ©R.LauwereinsImec 2001 Arithmetic OperatorsDigital entity Add isdesign port ( A,B: in integer range 0 to 7; Z: out integer range 0 to 14);Combina- end entity Add;torialcircuits architecture Behav of Add is beginSequentialcircuits Z <= A + B; end architecture Behav;FSMDdesignVHDL5/59
    • Language based HW design:©R.LauwereinsImec 2001 a VHDL primerDigital • Introductiondesign • A first look at VHDLCombina-torial • Signals and data typescircuits • VHDL operatorsSequentialcircuits  Concurrent versus sequential statementsFSMDdesign • Sequential construction statementsVHDL • Higher performance, less portability: e.g. synthesis issues for Xilinx5/60
    • ©R.LauwereinsImec 2001 Concurrent StatementsDigital • All statements are concurrent and aredesign continuously valid: this mimics theCombina- behavior of hardware, where all gatestorialcircuits operate concurrentlySequentialcircuits entity Concurrent is port ( A,B,C,D: in std_logic; Schematic:FSMD Y,Z: out std_logic);design end entity Concurrent; AVHDL architecture Struct of Concurrent is Y B begin NAND1: entity NAND2 port map (A,B,Y); C Z NAND2: entity NAND2 port map (C,D,Z); D end architecture Struct; What is the difference in behavior when NAND1 is specified after NAND2?5/61
    • ©R.LauwereinsImec 2001 Concurrent StatementsDigital • All statements are concurrent and aredesign continuously valid: this mimics theCombina- behavior of hardware, where all gatestorialcircuits operate concurrentlySequentialcircuits entity Concurrent is port ( A,B,C,D: in std_logic; Schematic:FSMD Y,Z: out std_logic);design end entity Concurrent; AVHDL architecture Struct of Concurrent is Y B begin NAND2: entity NAND2 port map (C,D,Z); C Z NAND1: entity NAND2 port map (A,B,Y); D end architecture Struct; Behavior is exactly the same!!!5/62
    • ©R.LauwereinsImec 2001 Concurrent Statements Does this schematic specify sequential Behavior?Digitaldesign Yes Schematic:Combina- Notorialcircuits A entity Concurrent is B T1Sequential port ( A,B, D: in std_logic;circuits Z: out std_logic); Z end entity Concurrent; DFSMDdesign architecture Struct of Concurrent is signal T1: std_logic;VHDL begin NAND2: entity NAND2 port map (T1,D,Z); NAND1: entity NAND2 port map (A,B,T1); end architecture Struct; Both gates continuously update their outputs5/63
    • ©R.LauwereinsImec 2001 SimulationDigital • This continuously updating of outputsdesign poses problems to the simulator: even ifCombina- nothing in the circuit changes, thetorialcircuits simulator has to compute continuously the ‘new’ outputs of all gatesSequentialcircuits • Solution: event-driven simulationFSMD  a statement is only re-evaluated when one ordesign more of its input signals changes (i.e. when an event occurs at one of its inputs)VHDL  we say that a statement is sensitive to all its input signals, because an event at any input signals triggers a re-evaluation  keep in mind that this mechanism is only for making simulation fast while maintaining the same behavior as in reality, where all gates work continuously!!5/64
    • ©R.LauwereinsImec 2001 SimulationDigital • How is an event-driven simulatordesign practically implemented?Combina- 1. Put all statements with at least one changed input in thetorialcircuits ‘process execution queue’ 2. Execute all statements in the process execution queueSequential one by one (or concurrently if the simulator is executedcircuits on a parallel computer) without updating the output signalsFSMD 3. After all statements in the process execution queue aredesign processed, update the output signals 4. Add all statements to the process execution queue thatVHDL have an event because of the updated output signals 5. Repeat until the process execution queue is empty 6. Advance system time to the next time where a timed event is planned (e.g. testbench: waitfor 20 ns) Delta cycle Delta cycle convergence5/65
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B NAND1 NAND1 NAND2 Q Q’ Step 1: Put statements with input T1 T2 event in PEQ5/66
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q’ <= 1 B NAND1 NAND1 NAND2 Q Q’ Step 2: Execute statements in PEQ T1 T2 and remember output5/67
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q’ <= 1 B NAND2 NAND1 NAND1 NAND2 Q Q’ Step 3: Update outputs T1 T25/68
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B NAND2 NAND1 NAND2 Q Q’ Step 4: Add statements with event T1 T2 to PEQ5/69 End Delta cycle 1 of T1
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q <= 0 B NAND2 NAND1 NAND2 Q Q’ Step 2: Execute statements in PEQ T1 T2 and remember output5/70
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q <= 0 B NAND2 NAND1 NAND2 Q Q’ Step 3: Update outputs T1 T25/71
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B NAND1 NAND1 NAND2 Q Q’ Step 4: Add statements with event T1 T2 to PEQ5/72 End Delta cycle 2 of T1
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q’ <= 1 B NAND1 NAND1 NAND2 Q Q’ Step 2: Execute statements in PEQ T1 T2 and remember output5/73
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q’ <= 1 B NAND1 NAND1 NAND2 Q Q’ Step 3: Update outputs T1 T25/74 Output does not change
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B NAND1 NAND2 Q Q’ Step 4: Add statements with event T1 T2 to PEQ5/75 End Delta cycle 3 of T1: convergence
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B NAND1 NAND2 Q Q’ Step 6: Advance system time T1 T25/76
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q’ <= 1 B NAND2 NAND1 Q <= 1 NAND2 Q Q’ Step 2: Execute statements in PEQ T1 T2 and remember output5/77 NAND2 computed using this Q’, not the remembered
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q’ <= 1 B NAND2 NAND1 Q <= 1 NAND2 Q Q’ Step 3: Update outputs T1 T25/78
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B NAND1 Q Q’ Step 4: Add statements with event T1 T2 to PEQ5/79 End Delta cycle 1 of T2
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q’ <= 0 B NAND1 Q Q’ Step 2: Execute statements in PEQ T1 T2 and remember output5/80
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q’ <= 0 B NAND1 Q Q’ Step 3: Update outputs T1 T25/81
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B NAND2 Q Q’ Step 4: Add statements with event T1 T2 to PEQ5/82 End Delta cycle 2 of T2
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q <= 1 B NAND2 Q Q’ Step 2: Execute statements in PEQ T1 T2 and remember output5/83
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Remembered Execution ExecutionVHDL Outputs Queue Queue A T1 T2 Q <= 1 B NAND2 Q Q’ Step 3: Update outputs T1 T25/84 Output does not change
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B Q Q’ Step 4: Add statements with event T1 T2 to PEQ5/85 End Delta cycle 3 of T2: convergence
    • ©R.LauwereinsImec 2001 Simulation entity Flipflop is A Q’Digital port ( A,B: in std_logic;design Q,Q’: out std_logic); end entity Flipflop; QCombina- Btorial architecture Struct of FlipFlop iscircuits begin NAND2: entity NAND2 port map (Q’,B,Q);Sequentialcircuits NAND1: entity NAND2 port map (A,Q,Q’); end architecture Struct;FSMDdesign Process Process Execution ExecutionVHDL Queue Queue A T1 T2 B Q Q’ Step 6: Advance system time T1 T25/86
    • ©R.LauwereinsImec 2001 ProcessDigital • Sometimes, the combinatorial equation indesign a single statement becomes veryCombina- complicated:torial Acircuits B CSequentialcircuits D Y entity Complex is EFSMD port( A,B,C,D,E,F,G,H,I,J: F Sdesign in std_logic; G Y,Z: out std_logic);VHDL H end entity Complex; I Z architecture Struct of Complex is J begin Y <= ((A nand B) nand (C nand D)) when (S = ‘1’) else ((E nand F) nand (G nand H)); Z <= I nand J; end architecture Struct;5/87
    • ©R.Lauwereins Unfortunately, in VHDLImec 2001 Process terminology they are also called ‘Statements’Digital • Therefore a process has been defined:design  a process acts as a single statement that isCombina- executed concurrently with all othertorial statementscircuits  inside a process, commands are executedSequential sequentially in the order they are listed. Thiscircuits makes it easy to break down a very complicated statement into a list of smallerFSMDdesign commands  to pass data from one command to the other,VHDL we may declare temporary variables; they do not have necessarily a physical realization  a statement, and hence also a process, is sensitive to all its input signals; to facilitate finding out what the input signals of a process are, since they can occur in any command, we have to explicitly add them to a sensitivity list. A process is recalculated when a signal in the5/88 sensitivity list has an event.
    • ©R.LauwereinsImec 2001 ProcessDigital Syntax of process:design Process_name: process (sensitivity_list) isCombina- -- variable declarations;torial begincircuits -- sequential commands end process Process_name;SequentialcircuitsFSMD Syntax of variable declaration:design variable Variable_name: type;VHDL Syntax of variable assignment: Variable_name := expression; When assigning to variable → := When assigning to signal → <=5/89
    • ©R.LauwereinsImec 2001 Process • Rewrite the example using a process:Digitaldesign entity Complex is T1 and T2 have no port( A,B,C,D,E,F,G,H,I,J: physical meaning sinceCombina- in std_logic; each refers to 2 differenttorial Y,Z: out std_logic); physical wirescircuits end entity Complex; T1 T2Sequential architecture Struct of Complex iscircuits Sensitivity list begin Y_process: process (A,B,C,D,E,F,G,H,S) isFSMDdesign variable T1,T2: std_logic; begin A if (S=‘1’) then BVHDL T1 := A nand B; C T2 := C nand D; Y D else T1 := E nand F; E T2 := G nand H; F S end if; G Y <= T1 nand T2; H end process Y_process; Z <= I nand J; I Z5/90 end architecture Struct; J
    • ©R.LauwereinsImec 2001 ProcessDigital • Processes and delta cycle convergence.design What is the behavior of following process:Combina- Example: process (A,B,M) istorialcircuits begin Y <= A; Old M!!! M gets M <= B; only new valueSequential at end of processcircuits Z <= M; end process Example;FSMDdesign 1. Assume event at B with new value B’ 2. Process Example is executed once sequentially. FollowingVHDL outputs are remembered: Y’ <= A; M’ <= B’; Z’ <= M; 3. Process Example suspends (i.e. is executed once completely). Y, M and Z get their new values Y’, M’, Z’. 4. Since M is in the sensitivity list, the Example process is placed again in the Process Execution Queue. 5. Process Example is executed: Y” <= A; M” <= B’; Z” <= M’; 6. Outputs Y, M and Z get their new values Y”, M”, Z”. 7. No signals of the sensitivity list changed => delta cycle5/91 convergence
    • ©R.LauwereinsImec 2001 ProcessDigital • Processes and delta cycle convergence.design What is the behavior of following process:Combina-torial Example: process (A,B,C,D) iscircuits begin Z <= A + B;Sequential Z <= C + D;circuits end process Example;FSMDdesign 1. Assume event at B with new value B’ 2. The commands of Process Example are executedVHDL sequentially. First following output is remembered: Z’ <= A + B’; 3. Next, the second command is executed and following output is remembered: Z’ <= C + D. This overwrites the previously remembered Z’ 4. Process Example suspends and hence signal Z is updated with its new value C + D When the same two statements would have occurred outside a process, both would drive signal Z and a resolver would be necessary5/92
    • Language based HW design:©R.LauwereinsImec 2001 a VHDL primerDigital • Introductiondesign • A first look at VHDLCombina-torial • Signals and data typescircuits • VHDL operatorsSequentialcircuits • Concurrent versus sequential statementsFSMDdesign  Sequential construction statementsVHDL • Higher performance, less portability: e.g. synthesis issues for Xilinx5/93
    • Sequential construction©R.LauwereinsImec 2001 statementsDigital • Sequential construction statements aredesign only allowed within a process!!!Combina-torial • There are 3 sequential constructioncircuits statements: IF, CASE, FORSequential IF statement:circuits if condition thenFSMD -- sequential statementsdesign multiple IF statements: else -- sequential statementsVHDL end if; if condition1 then -- sequential statements elseif condition2 then -- sequential statements The first condition which elseif condition3 then turns out to be TRUE -- sequential statements determines which else sequential statements are -- sequential statements executed: built-in priority end if;5/94
    • Sequential construction©R.LauwereinsImec 2001 statements case Expression isDigital when Value_1 =>design -- sequential statements when Value_2 =>Combina-torial -- sequential statementscircuits -- etc. end case; Requirements:Sequentialcircuits 1. All possible values should be specifiedFSMD Example: process (A,B,C,X) isdesign begin 2. The values should be case X is constant and known atVHDL when 0 to 4 => design time Z <= B; 3. The values should have the when 5 => same type as the Z <= C; expression when 7 | 9 => Z <= A; when others => Z <= ‘0’; end process Example;5/95
    • Sequential construction©R.LauwereinsImec 2001 statementsDigitaldesign for I in 0 to 3 loop -- sequential statementsCombina- end loop;torialcircuits Remarks:Sequential 1. The loop variable must not be declaredcircuits 2. The synthesis tool will unfold the loop and create logic for each iteration of the loop. Then, it will start minimizing theFSMDdesign complete circuitVHDL5/96
    • Sequential construction©R.LauwereinsImec 2001 statements entity General_mux isDigital generic (width : integer);design port ( Input : in std_logic_vector (width - 1 downto 0); Select : in integer range 0 to width - 1;Combina-torial Output : out std_logic);circuits end entity General_mux;Sequential architecture Behav of General_mux iscircuits begin We indicated that Output <= Input(Select); this is not valid VHDL:FSMD end architecture Behav; index is not known atdesign design time! We will replace this now byVHDL valid code using the loop construct.5/97
    • Sequential construction©R.LauwereinsImec 2001 statementsDigitaldesign entity General_mux is generic (width : integer);Combina- port ( Input : in std_logic_vector (width - 1 downto 0);torial Select : in integer range 0 to width - 1;circuits Output : out std_logic); end entity General_mux;Sequentialcircuits architecture Behav of General_mux is beginFSMD Selector: process (Input, Select) isdesign begin for I in 0 to width-1 loopVHDL if Select=I then Output <= Input(I); end if; end loop; end process Selector; end architecture Behav;5/98
    • ©R.LauwereinsImec 2001 VariablesDigital • A variable can only be used within adesign processCombina-torial • A variable is updated immediately; acircuits signal is stored in the signal update queueSequential till the process suspends • Variables may be assigned to signals andcircuitsFSMD vice versadesign • Variables are used as intermediate valuesVHDL to facilitate the specification of the process; when the value of a variable needs to be accessible outside the process, it should be assigned to a signal5/99
    • ©R.LauwereinsImec 2001 Variables With which hardware schematic does following code correspond?Digitaldesign entity Parity is generic (width : integer);Combina- port (A: in std_logic_vector (0 to width-1);torialcircuits Odd: out std_logic); end entity Parity; This is the HW structure as it is given to the synthesisSequentialcircuits architecture Struct of Parity is tool. The synthesis tool begin will optimize away the xorFSMD Parity: process(A) is with constant ‘0’ inputdesign variable Temp: std_logic; and will transform it to begin a binary tree of less depthVHDL Temp := ‘0’; for I in A’low to A’high loop Temp := Temp xor A(I); 0 Temp end loop; A(0) Odd <= Temp; end process Parity; Temp end architecture Struct; A(1) Odd A(2)5/100
    • ©R.LauwereinsImec 2001 Rising clock edge With which function does following code correspond?Digitaldesign entity What is port (D,Clk: in std_logic; Q: out std_logic);Combina-torial end entity What;circuits Since there is no ELSE part architecture RTL of What is the previous Q value hasSequential begin to be remembered for the casecircuits process (D, Clk) is where Clk=‘0’. begin The synthesis tool will henceFSMD if (Clk=‘1’) then infer a latch instead of justdesign Q <= D; combinatorial logic!!! end if;VHDL end process; Beware of unintended latches end architecture RTL; when ELSE parts are omitted With a latch, not with a D-flip-flop!! When a Clk-event occurs and Clk is low, nothing happens When a Clk-event occurs and Clk is high, the D input is copied to the Q output When a D-event occurs and Clk is high, the D input is copied to5/101 the Q output => hence a latch: when Clk is high, Q follows D
    • ©R.LauwereinsImec 2001 Rising clock edge How do we describe a rising clock edge?Digitaldesign Method 1: WAIT UNTILCombina-torial entity DFlipFlop iscircuits port (D,Clk: in std_logic; Q: out std_logic);Sequential end entity DFlipFlop;circuits architecture RTL of DFlipFlop isFSMD begindesign process is This is not synthesisable beginVHDL wait until Clk’event and Clk=‘1’; Q <= D; end process; end architecture RTL;5/102
    • ©R.LauwereinsImec 2001 Rising clock edge How do we describe a rising clock edge?Digitaldesign Method 2: Sensitivity list Preferred method!Combina- entity DFlipFlop istorial port (D,Clk: in std_logic;circuits Q: out std_logic); end entity DFlipFlop;Sequentialcircuits architecture RTL of DFlipFlop is beginFSMDdesign process (D,Clk) is begin if (Clk’event and Clk=‘1’) thenVHDL Q <= D; end if; end process; end architecture RTL;5/103
    • ©R.LauwereinsImec 2001 Rising clock edge How do we describe combinatorial circuits with registered outputs?Digitaldesign ACombina- B Ztorialcircuits CSequential Method 1: WAIT UNTILcircuits D entity RegisteredCircuit isFSMD port (A,B,C,D,Clk: in std_logic;design Z: out std_logic); end entity RegisteredCircuit; ‘Wait until’ has to beVHDL first line of process, architecture RTL of RegisteredCircuit is followed by begin the description of the process is combinatorial circuit begin wait until Clk’event and Clk=‘1’; -- combinatorial circuit Z <= (A and B) or (C and D); end process; end architecture RTL;5/104
    • ©R.LauwereinsImec 2001 Rising clock edge How do we describe combinatorial circuits with registered outputs?Digitaldesign ACombina- B Ztorialcircuits Method 2: Sensitivity list CSequentialcircuits entity RegisteredCircuit is D port (A,B,C,D,Clk: in std_logic;FSMD Z: out std_logic);design end entity RegisteredCircuit; ‘if Clk’event’ has to be first line of process,VHDL architecture RTL of RegisteredCircuit is with the description begin of the combinatorial process (A,B,C,D,Clk) is circuit in the THEN begin part and with no if (Clk’event and Clk=‘1’) then ELSE part -- combinatorial circuit Z <= (A and B) or (C and D); end if; end process; end architecture RTL;5/105
    • ©R.LauwereinsImec 2001 Rising clock edgeDigital • The amount of logic we describe in thedesign combinatorial part, determines theCombina- combinatorial delaytorialcircuits • It hence determines the maximum clockSequential frequency with which we can clock thecircuits flip-flopFSMD • Re-timing requires re-writing the VHDLdesign codeVHDL5/106
    • ©R.LauwereinsImec 2001 Rising clock edge How do we describe flip-flops with asynchronous reset?Digitaldesign entity DFlipFlop isCombina-torial port (D,Clk, Reset: in std_logic;circuits Q: out std_logic); end entity DFlipFlop;Sequentialcircuits architecture RTL of DFlipFlop is beginFSMD process (D, Clk, Reset) isdesign begin if (Reset = ‘1’) thenVHDL Q <= ‘0’; elseif (Clk’event and Clk=‘1’) then Q <= D; end if; end process; end architecture RTL;5/107
    • ©R.LauwereinsImec 2001 Rising clock edge How do we describe flip-flops with synchronous reset?Digitaldesign entity DFlipFlop is port (D,Clk, Reset: in std_logic;Combina-torial Q: out std_logic);circuits end entity DFlipFlop;Sequential architecture RTL of DFlipFlop iscircuits begin process (D, Clk, Reset) isFSMD begindesign if (Clk’event and Clk=‘1’) then if (Reset=‘1’) thenVHDL Q <= 0; else Q <= D; end if; end if; end process; end architecture RTL;5/108
    • ©R.LauwereinsImec 2001 Finite State MachineDigital Start=0design WaitCombina- Reset Start=1 00torial Out Output Start=1circuits Up=1 Up=0 put logicSequentialcircuits Up1 Down3 State 01 11 Reg CurrentStateFSMDdesign Next NextState Up2 Down2VHDL state 10 10 logic Up3 Down1 11 01 Start Up5/109
    • ©R.LauwereinsImec 2001 Finite State Machine entity FSM isDigital port ( Start, Up, Reset, Clk: in std_logic; Start=0design Output: out std_logic_vector(0 to 1)); end entity FSM; WaitCombina- 00torial architecture Behav of FSM is Start=1 Start=1circuits type FSM_States = (Wait,Up1,Up2, Up=1 Up=0 Up3,Down1,Down2,Down3);Sequential signal CurrentState, NextState : Up1 Down3circuits FSM_States; 01 11 beginFSMDdesign OutputLogic: process(CurrentState) is … Up2 Down2VHDL end process OutputLogic; 10 10 NextStateLogic: process(CurrentState,Start,Up) is … end process NextStateLogic; Up3 Down1 StateRegister: 11 01 process(NextState,Clk,Reset) is … end process StateRegister;5/110 end architecture Behav;
    • ©R.LauwereinsImec 2001 Finite State MachineDigital Start=0design WaitCombina- 00torial OutputLogic: Start=1 Start=1circuits process(CurrentState) is Up=1 Up=0 beginSequential case CurrentState is Up1 Down3circuits when Wait => 01 11 Output <= “00”;FSMDdesign when Up1|Down1 => Output <= “01”; when Up2|Down2 => Up2 Down2VHDL Output <= “10”; 10 10 when Up3|Down3 => Output <= “11”; end case; end process OutputLogic; Up3 Down1 11 015/111
    • ©R.LauwereinsImec 2001 Finite State Machine NextStateLogic:Digital process(CurrentState,Start,Up) is Start=0design begin case CurrentState is WaitCombina- when Wait => Start=1 00 Start=1torial if (Start=‘0’) thencircuits NextState <= Wait; Up=1 Up=0 elseif (Up=‘1’) thenSequential NextState <= Up1; Up1 Down3circuits else 01 11 NextState <= Down3;FSMDdesign end if; when Up1 => NextState <= Up2; Up2 Down2VHDL when Up2 => 10 10 NextState <= Up3; when Up3|Down1 => NextState <= Wait; when Down3 => Up3 Down1 NextState <= Down2; 11 01 when Down2 => NextState <= Down1; end case;5/112 end process NextStateLogic;
    • ©R.LauwereinsImec 2001 Finite State MachineDigital Start=0design WaitCombina- 00torial Start=1 Start=1circuits Up=1 Up=0Sequential StateRegister:circuits process(NextState,Clk,Reset) is Up1 Down3 begin 01 11FSMD if Reset=‘1’ thendesign CurrentState <= Wait; elseif (Clk’event and Clk=‘1’) thenVHDL CurrentState <= NextState; Up2 Down2 end if; 10 10 end process StateRegister; Up3 Down1 11 015/113
    • Language based HW design:©R.LauwereinsImec 2001 a VHDL primerDigital • Introductiondesign • A first look at VHDLCombina-torial • Signals and data typescircuits • VHDL operatorsSequentialcircuits • Concurrent versus sequential statementsFSMDdesign • Sequential construction statementsVHDL  Higher performance, less portability: e.g. synthesis issues for Xilinx5/114
    • ©R.LauwereinsImec 2001 Resource sharing What is the circuit corresponding to: A B A CDigitaldesign if Sel = ‘1’ then Z <= A + B;Combina- else + +torialcircuits Z <= A + C; end if;Sequential Selcircuits MUX This is kind of stupid, since bothFSMD additions are mutually exclusive: Zdesign it is hence not necessary to implement 2 adders.VHDL B C A Some synthesis tools are capable to recognize this (often only within MUX Sel the scope of a process) and transform this into the shared use of one adder for both additions. Xilinx Foundation Series performs + this optimization within a hierarchical level.5/115 Z
    • ©R.LauwereinsImec 2001 Resource sharingDigital If the synthesis tool does not do B C Adesign this optimization automatically, you should re-write your code: MUX SelCombina-torialcircuits if Sel = ‘1’ then X := B; elseSequential +circuits X := C; end if; Z <= A + X; ZFSMDdesignVHDL The VHDL coding style together with the capabilities of the synthesis tool determine the circuit that is eventually synthesized.5/116
    • ©R.LauwereinsImec 2001 Using LogiBLOX in VHDLDigital • LogiBLOX modules lead to highly efficientdesign FPGA implementationsCombina-torial • The LogiBLOX module generator creates,circuits apart from the FPGA implementation, alsoSequential a behavioral level VHDL module forcircuits simulation!FSMD • How to use LogiBLOX modules in yourdesign VHDL code:VHDL  use the package containing the LogiBLOX modules: library My_Library; use My_Library.My_Package.all;  instantiate the entity • Using LogiBLOX makes your VHDL implementation more efficient on Xilinx FPGA but less portable to other devices!!5/117
    • ©R.LauwereinsImec 2001 Encoding of State MachinesDigital • The default encoding in Foundationdesign Express is one-hot since this matchesCombina- well with the structure of a CLB (little bittorialcircuits of combinatorial logic in front of a D-flip- flop)Sequentialcircuits • The encoding can be specified in theFSMD VHDL code:design type State_Type is (S1, S2, S3, S4);VHDL attribute ENUM_ENCODING: string; attribute ENUM_ENCODING of State_Type: type is “11 10 01 00”;5/118
    • ©R.LauwereinsImec 2001 Safe state machinesDigital • Assume a statedesign machine of threeCombina- states, encoded with NextStateLogic:torialcircuits 2 bits process(CurrentState) isSequential • What would happen begin case CurrentState iscircuits when the state when Idle =>FSMD machine enters the NextState <= S1; when S1 =>design 4th state, due to NextState <= S2;VHDL some error (noise, when S2 => NextState <= Idle; power-up, …)? Will it when others => be able to recover? NextState <= Idle; end case; • Make provisions for end process NextStateLogic; this situation in your VHDL code:5/119
    • ©R.LauwereinsImec 2001 Family specific issuesDigital • Not all families provide per flip-flop bothdesign asynchronous set as well as reset.Combina-torial • Check what your family provides beforecircuits you write VHDLSequentialcircuits process (Clk, Rst, Set) is Can only be implemented begin efficiently when theFSMD if Rst = ‘1’ then family has both andesign Q <= ‘0’; asynchronous set elseif Set = ‘1’ then as well as resetVHDL Q <= ‘1’; elseif Clk’event and Clk = ‘1’ then -- actions end if; end process;5/120
    • ©R.LauwereinsImec 2001 Family specific issuesDigital • Always use LogiBLOX for RAM, becausedesign RAM would otherwise be created out ofCombina- separate flip-flopstorialcircuitsSequentialcircuitsFSMDdesignVHDL5/121
    • ©R.LauwereinsImec 2001 I/O buffer typesDigital • Put all the core logic in one entitydesign • In a higher hierarchical level, instantiateCombina-torial the I/O buffers as well as the core logiccircuits • The hierarchy hence becomesSequential  Top level: test bench instantiating DUTcircuits  DUT: Instantiation of core logic and I/O buffersFSMD  Core logic: real designdesignVHDL5/122
    • ©R.LauwereinsImec 2001 I/O buffer types How to force a 3-state output buffer:Digital Enabledesign if (Enable = ‘1’) then Out_pad Out_pad <= Bus_out; Bus_outCombina- elsetorialcircuits Out_pad <= ‘Z’; end if;SequentialcircuitsFSMDdesign How to force a bidirectional buffer:VHDL Bus_in <= Bidi_pad; process (Enable, Bus_out) is Enable begin if (Enable = ‘1’) then Bus_out Bidi_pad <= Bus_out; Bidi_pad else Bidi_pad <= ‘Z’; end if; Bus_in end process;5/123
    • ©R.LauwereinsImec 2001 I/O buffer types How to force a bidirectional buffer with registered output:Digitaldesign Bus_in <= Bidi_pad; process (Enable,Q) is beginCombina-torial if (Enable = ‘1’) thencircuits Bidi_pad <= Q; elseSequential Bidi_pad <= ‘Z’;circuits end if; end process;FSMD process (Clk, Bus_out) isdesign begin if Clk’event and Clk = ‘1’ thenVHDL Q <= D; end if; end process; Clk Enable Bus_out D Q Bidi_pad Bus_in5/124
    • ©R.LauwereinsImec 2001 I/O buffer types How to force a pull-up resistor at an input: VccDigital entity Pullup_in isdesign port ( In_pad: in std_logic; In_pad Core_in: out std_logic); Core_inCombina- end entity Pullup_in;torialcircuits architecture RTL of Pullup_in isSequentialcircuits component PULLUP port (O: out std_logic);FSMD end component PULLUP;design component IBUFVHDL port (I: in std_logic; O: out std_logic); end component IBUF; signal Dummy: std_logic; begin Dummy <= In_pad; PU: component PULLUP port map (Dummy); Buf: component IBUF port map (Dummy,Core_in); end architecture RTL;5/125
    • ©R.LauwereinsImec 2001 Using the Global Set Reset blockDigitaldesign entity OneHot is port ( Rst, Clk: in std_logic;Combina- Q: out std_logic_vector (0 to 3));torial end entity OneHot;circuits architecture Behav of OneHot isSequentialcircuits component STARTUP port (GSR: out std_logic);FSMD end component STARTUP;design beginVHDL U1: component STARTUP port map (Rst => GSR); if Rst = ‘1’ then Q <= “0001”; elseif Clk’event and Clk = ‘1’ then Q <= Q(1 to 3) & Q(0); endif; end architecture RTL;5/126
    • ©R.LauwereinsImec 2001 Clock NetworksDigital • Foundation Express synthesizesdesign automatically clock buffersCombina-torial • Check whether you do not need morecircuits clock buffers than are available in theSequential target familycircuitsFSMDdesignVHDL5/127