Design and Simulation Triple-DES

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Design and Simulation Triple-DES

  1. 1. Simulation on Triple Data Encryption standard Adviser Aj. Jarern Vongshumyen By Chatsiri Rattana 47221163 Woranart Hasawayukul 47221858
  2. 2. Agenda <ul><li>Introduction </li></ul><ul><li>Theory on Triple DES </li></ul><ul><li>Design on Triple DES </li></ul><ul><li>Testing and Result on Triple DES </li></ul><ul><li>Conclusion </li></ul>
  3. 3. Introduction
  4. 4. Background <ul><li>Low security of general data transfer. </li></ul><ul><li>Use encryption system to secure the data communicates. </li></ul><ul><li>Then we choose Triple-DES. </li></ul><ul><li>Apply for design digital circuit by using VHDL(VHSIC Hardware Description Language). </li></ul>
  5. 5. Objective <ul><li>To learn about Triple-DES(Triple-Data Encryption Standard) algorithm. </li></ul><ul><li>To learn about VHDL(VHSIC Hardware Description Language) coding. </li></ul><ul><li>Can design an implementable digital circuit of Triple-DES. </li></ul><ul><li>Can simulate a circuit that perform result of encryption and decryption. </li></ul>
  6. 6. Tools for Development Xilinx Inc.Webpack 8.2i. ModelSim
  7. 7. Theory on Triple DES
  8. 8. What is DES? <ul><li>DES - Data Encryption Standard </li></ul><ul><li>Symmetric system - uses the same key to encrypt/decrypt data. </li></ul>Ciphertext Plaintext DES Key Key Encrypt Decrypt
  9. 9. DES Algorithm Structure <ul><li>The algorithm consists of: </li></ul><ul><ul><li>An initial permutation of the input data </li></ul></ul><ul><ul><li>Sixteen rounds of the same process –the DES round </li></ul></ul><ul><ul><li>A final inverse initial permutation of the data </li></ul></ul>
  10. 10. Step 1: Create 16 subkeys, each of which is 48-bits long.
  11. 11. Step 2: Encode each 64-bit block of data The Feistel ( F ) function
  12. 12. Mode of 3DES <ul><li>3 DES – EDE (2 keys 3DES) </li></ul><ul><li>Keys = 112 bits </li></ul>C = E k1 ( D k2 (E k1 (M)))
  13. 13. 3DES-EDE E D E k 1 k 2 k 1 Plaintext Ciphertext D E D k 1 k 2 k 1 Ciphertext Plaintext
  14. 14. Design on Triple DES
  15. 15. Schematic On Top Module
  16. 16. Coding Entity Top module <ul><li>entity test_tdestop is </li></ul><ul><li>Port ( data_intdes : in std_logic_vector ( 0 to 63 ) ; </li></ul><ul><li>key1_intdes : in std_logic_vector ( 0 to 63 ) ; </li></ul><ul><li>key2_intdes : in std_logic_vector ( 0 to 63 ) ; </li></ul><ul><li>key3_intdes : in std_logic_vector ( 0 to 63 ) ; </li></ul><ul><li>clock : in std_logic; </li></ul><ul><li>function_selecttdes : in std_logic; </li></ul><ul><li>set_out : in std_logic; </li></ul><ul><li>lddatatdes : in std_logic; </li></ul><ul><li> ldkeytdes : in std_logic; </li></ul><ul><li>resettdes : in std_logic; </li></ul><ul><li>data_outtdes : out std_logic_vector ( 0 to 63 ) ; </li></ul><ul><li>out_readytdes : out std_logic </li></ul><ul><li> ) ; </li></ul>
  17. 17. Structure on DESCIPHERTOP
  18. 18. DESCIPHERTOP 1,2,3 KEYSCHEDULE DES
  19. 19. KEYSCHEDULE
  20. 20. DESTOP
  21. 21. BLOCKTOP
  22. 22. E_EXPANSION FUCNTION
  23. 23. ADDKEY
  24. 24. SBOX
  25. 25. PBOX
  26. 26. ADDLEFT
  27. 27. Device Utilization Summary Logic Utilization Used Available Utilization Slices 1398 4656 30 % Slice FF 1140 9312 12% IOB 305 232 131% GCLKs 1 24 4% MAX CLK 77.548MHz
  28. 28. Testing and Result on Triple DES
  29. 29. Test by Test Bench and Wave Form <ul><li>Injection Key 1,2,3 and Data to Triple DES </li></ul><ul><ul><li>Key1<=“DataBit”,Key2<=“DataBit”,Key3<=“DataBit” </li></ul></ul><ul><li>Use Text I/O Read and Write Data to Triple DES </li></ul><ul><li> write </li></ul><ul><ul><li>write(out_data_out,data_outtdes); </li></ul></ul><ul><ul><li>writeline(logdata_out,out_data_out); </li></ul></ul><ul><ul><li>read </li></ul></ul><ul><ul><li>readline(read_inputtest,read_inputtest_line); </li></ul></ul><ul><ul><li>read(read_inputtest_line,input_temp); </li></ul></ul><ul><li>Test Bench not permission injection Output </li></ul>
  30. 30. Strategy for test Encryption Decryption Text File Text File Data
  31. 31. Test Triple DES ( Encryption ) Input Output
  32. 32. Test of Triple DES ( Decryption ) Input Output
  33. 33. Conclusion
  34. 34. Conclusion <ul><li>Can design and simulation circuit . </li></ul><ul><li>Use function for simulation circuit. </li></ul><ul><li>Can Applied Algorithm Triple DES . </li></ul><ul><li>Circuit has delay time and cannot control some gate. </li></ul><ul><li>Can synthesis on FPGA board but it need clock generator and RAM. </li></ul><ul><li>Large IOB must has floorplanning to save spaces that use. </li></ul>

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