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Capacitance Sensing - EMC Design Considerations for PSoC CapSense Applications
 

Capacitance Sensing - EMC Design Considerations for PSoC CapSense Applications

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Designing capacitive touch sense systems with PSoC® CapSense for compliance with EMC standards results in easier qualification of new designs and more robust, low-cost system design. Examples are ...

Designing capacitive touch sense systems with PSoC® CapSense for compliance with EMC standards results in easier qualification of new designs and more robust, low-cost system design. Examples are shown with test results demonstrating compliance.

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    Capacitance Sensing - EMC Design Considerations for PSoC CapSense Applications Capacitance Sensing - EMC Design Considerations for PSoC CapSense Applications Document Transcript

    • Capacitance Sensing - EMC Design Considerations for PSoC CapSense Applications AN2318 Author: Mark Lee Associated Project: No Associated Part Family: CY8C21x34 GET FREE SAMPLES HERE Software Version: PSoC Designer™ 4.2 Associated Application Notes: AN2155, AN2292 Application Note Abstract Designing capacitive touch sense systems with PSoC® CapSense for compliance with EMC standards results in easier qualification of new designs and more robust, low-cost system design. Examples are shown with test results demonstrating compliance. include requirements of EN55011, the European standard for medical devices. Devices that include motor controls Introduction are covered under EN55014; lighting devices are covered Every electronic device is required to comply with specific under EN50015. These specifications have essentially limits for emitted energy and susceptibility to external similar performance limits for radiated and conducted upsets. These limits are specified by the FCC in the US emissions. and by similar regulatory bodies in other countries. The Radiated and conducted immunity (susceptibility) regulations help ensure that electronic devices will not performance requirements are specified by several interfere with each other… so that your computer does not sections of EN61000-4 and EN55024. ESD testing is interfere with your television, or worse yet, a hospital X-ray covered in EN55024. machine or ventilator does not corrupt the operation of a critical medical monitor. Emissions Modern high-speed digital electronics are capable of generating very high-speed signals that have the potential Radiated: Radiated emissions primarily result from digital to radiate substantial amounts of noise. CMOS analog and transients on inputs and outputs. To the greatest extent digital circuits have essentially infinite input impedance. As possible, the bandwidth of digital outputs should be a result, they are quite sensitive to external fields and limited. The PSoC™ device has I/O limited to 12.0 MHz by suitable precautions must be taken to ensure their proper the global bus structure. This clocking limitation provides operation in the presence of large amounts of radiated and the first line of defense against radiated emissions. PSoC conducted, interfering energy. This Application Note devices CY8C21xxx, CY8C24xxxA, CY8C27xxx, outlines the basic specifications involved, provides CY8C29xxx and all planned future generations provide the guidance for secure and compliant designs, and shows option to enable slower rise and fall times, which will limit the test results from a successful PSoC CapSense design. harmonic energy in the digital outputs. This option is not available in the earlier generation parts, CY8C25xxx and CY8C26xxx. Routed high-speed traces on the board Specifications should be kept as short as practical. If the signal leaves Computing devices are regulated in the US by the FCC the board to drive an external load, it should have a under Part 15, Sub-Part B for unintentional radiators. The series-terminating resistor at the chip to provide the standards for Europe and the rest of the world are adapted necessary bandwidth limit. Fifteen to 50 ohms is usually from CENELEC. These are covered under CISPR sufficient on high-speed lines. Note that a digital output standards (dual labeled as ENxxxx standards) for that is at a logic one is directly connected (by the output P- emissions and under IEC standards (also dual labeled as channel FET's RDS(ON)) to Vdd. Thus, the Vdd bus is ENxxxx standards) for immunity and safety concerns. essentially directly connected to the output, and any high frequency noise that appears on the Vdd bus will also The general emissions specification is EN55022 for appear on the output. It is important to provide a well- computing devices. This standard covers both radiated coupled, high frequency bypass capacitor from Vdd to VSS and conducted emissions. Medical devices in the US are at the PSoC chip. The capacitor bypass traces should be not regulated by the FCC, but rather by FDA rules, which September 16, 2005 Document No. 001-31162 Rev. ** 1 [+] Feedback
    • AN2318 very short; ground and power planes should be used include the location of the discharge on the case of the where possible. A design example for radiated emissions device under test, the voltage level of the discharge, and for CapSense is presented later in this Application Note. the environment in which the ESD event occurs. A design example for ESD for CapSense is presented later in this Conducted: Conducted emissions result as a function of Application Note. comparatively low frequency RF conduction into the power supply system. High frequency bypass capacitors, and a bulk bypass capacitor at the PSoC power pins to support Design Example – Radiated large instantaneous load demands are effective at Emissions eliminating coupling from the PSoC chip and its direct loads from the power system. Switching power supply A circuit was assembled to implement a simple 8-button transients are not a PSoC chip problem per se, but CapSense project using a CY8C21534-24PVXI chip. represent the bulk of conducted emissions. Standard General layout guidelines found in Application Note design practices for reducing this noise include the use of AN2292 were applied in the design of the PCB. Please differential and common mode inductors on the input consult AN2292 to understand the reasoning behind the power connection and the use of high voltage capacitors following features. The circuit was assembled on a 0.062” from AC line and AC neutral-to-earth ground. Conducted thick FR4 double-sided PCB. The CapSense ground plane electrical energy influences system measurements and resides solely on the topside of the board and consists of upsets the operation of the processor core by driving the a 60% partial ground fill. There is no ground plane on the PSoC chip's power supply out of range. Power line inputs bottom of the board. For evaluation purposes, the should be protected with common mode and differential diameter of 4 of the buttons on this test board is 1.0cm, mode chokes and transient voltage suppressors such as and the other 4 are 1.2cm”. The gap between the buttons MOVs. A design example for general PSoC applications and ground is 0.020”. For each size of button, two pads involving conducted emissions can be found in Application are solid conductors and two are inter-digitated. A photo of Note AN2155. the PCB is shown below. This board was built for internal testing purposes at Cypress and is not available to the general public. Susceptibility Radiated: Radiated electrical energy can influence system Figure 1. Internal Test CapSense PCB measurements and potentially influence the operation of the processor core. The interference enters the PSoC chip at the Printed Circuit Board (PCB) level, through the pins. Means to prevent upsets from radiated energy are directed to careful board layout as well as good PSoC project design. These steps include the following: 1. Minimize source impedances (where possible) of signal sources coming to the chip. The system is self-powered from a 9V battery. Debug data is sent out from the PSoC over a UART 2. Minimize loop areas of input signal traces. (asynchronous RS232 at 4800 baud). The PC side of the 3. Use ground planes where possible. UART interface is isolated from the test board by a pair of opto-isolators. A custom cable was made to communicate 1. Set unused I/O pins to strong digital output, with logic from the test board opto-isolators to the PC over the state set to zero. RS232 interface. This consisted of a 5-pin plug, a DB9 connector, a 75K pull-up resistor, two 9V batteries, and a A design example for radiated susceptibility for CapSense shielded cable. A schematic of the communications is presented later in this Application Note. interface is shown below. Conducted: Conducted electrical energy influences system measurements and upsets the operation of the Figure 2. Communications Interface Schematic processor core by driving the PSoC chip's power supply out of range. Power line inputs should be protected with common mode and differential mode chokes and transient voltage suppressors such as MOVs. A design example for general PSoC applications involving conducted susceptibility can be found in Application Note AN2155. Electrostatic Discharge - ESD The system was tested at the Northwest EMC facility in Sultan, WA on August 29, 2005. The CapSense buttons Electrostatic discharge or ESD is caused by the buildup of were tested per the requirements of EN55022 (Amds. electrical charge on one surface that is suddenly A1:200, A2:2003) Class B:1998. transferred to another surface when it is touched. This discharge is typically several thousand volts. A system that is susceptible to ESD will respond to the discharge in different ways depending on a number of factors, which September 16, 2005 Document No. 001-31162 Rev. ** 2 [+] Feedback
    • AN2318 EN55022 consists of a quot;pre-scanquot; test and an Open Area Test Site (OATS) test. The purpose of the pre-scan test is Design Example – Radiated to discover the frequencies at which the device emits the Susceptibility most energy. The pre-scan test is conducted in a test chamber. The OATS test is used to take more precise The 8-button circuit and EMC test facilities used in the measurement of the emissions. OATS testing is radiated emissions testing of the previous section are conducted in a large chamber (10 meters or open air.) For again employed for radiated susceptibility testing. most PSoC applications (Class B - lower threshold for The CapSense buttons were tested per the requirements residential use), the Pass/Fail threshold is 30 dBuV/m of EN55024. The purpose of the EN55024 radiated from 30 MHz to 230 MHz and 37 uV/m from 230 MHz to 1 immunity test is to discover the frequencies of radiated GHz. interference that cause the most disruption for the device The result of the EN55022 pre-scan test is shown in the under test. The radiated immunity test is conducted in an plot below. From this plot, a set of frequencies is identified electro-magnetically sealed anechoic test chamber. The for investigation in the more precise OATS test. procedure for this test is as follows: 1. Inside the chamber are the device under test, an Figure 3. EN55022 Pre-Scan Test Result antenna that radiates the RF interference, and another antenna that monitors the frequency of the interference. 2. Outside the chamber are an RF signal generator and power amplifier that are operated automatically by a controlling PC over GPIB. This RF source creates the interference for the susceptibility test. 3. Also outside the chamber is a monitoring PC that observes the operation of the device under test. A frequency counter outside the chamber connects to the monitoring antenna inside the chamber. This counter connects to the monitoring PC via GPIB The PSoC CapSense 8-button circuit board passed the through an RS232 extension cable. Counter data is EN55022 with a large margin, >= 10 dB. A plot of the used to correlate the response of the device under OATS testing results is shown below. The technician in test to the frequency of the interference. charge of conducting the test is quoted: quot;This is the most boring OATS test we have ever conducted.quot; In this case, 4. Antenna feeds and the RS232 extension cable are boring is a good thing. fed through a small electromagnetically insulated hole in the test chamber. Figure 4. “Boring” OATS Test Results 5. The technician in charge of performing the test sweeps the device with a 3V/m logarithmic sweep from 80 MHz to 1 GHz. 6. The technician in charge of the test enters the chamber and adjusts the antenna from horizontal to vertical polarization or visa-versa. 7. The technician seals the chamber and performs another sweep. Steps 5-7 are repeated until the following eight combinations of polarization and position are swept at required frequency and level and recorded by the PC: September 16, 2005 Document No. 001-31162 Rev. ** 3 [+] Feedback
    • AN2318 The plots show that button sensitivity has at least 10 Table 1. Radiated Immunity Test Combinations counts of design margin over the 80 MHz to 1 GHz test spectrum. Based on these test results, the PSoC Polarization Position CapSense 8-button circuit board passes the requirements Horizontal Front of the EN55024 radiated susceptibility test. Horizontal Right Design Example - ESD Horizontal Back A consumer product that currently incorporates an array of Horizontal Left PSoC CapSense buttons is used for an ESD design example. The PSoC in this example is a CY8C21434- Vertical Front 24LFXI. General layout guidelines found in Application Vertical Right Note AN2292 were applied in the design of the PCB for this product. Please consult AN2992 to understand the Vertical Back reasoning behind the following features. The circuit was assembled on a reinforced Kapton flexible PCB with four Vertical Left layers. Total board thickness including top and bottom mask layers is 0.014”. The top layer has a 3 x 3 button array. Dimensions of the array are approximately 1.5” x The requirement for passing the EN55024 radiated 1”. The ground plane is formed by a 40% partial ground fill susceptibility test is that normal operation of the system is on the bottom side of the PCB. A copper trace surrounds maintained in the presence of the radiated interference. the perimeter of the PCB to form a ground ring that For CapSense buttons, normal operation is defined as a improves the performance of the CapSense circuit. The measured sensitivity that is greater than a lower sensitivity button array is embedded inside the product. The case is limit for a given application. Sensitivity of the buttons is made of acrylic, which functions as a 1.0-mm thick overlay defined as the difference in count values between a finger over the button array. touching and not touching a button. The system is self-powered from a 3V battery. The LCD Button Sensitivity = on this product is observed for signs of normal operation (Counts with Finger) – (Counts without Finger) during the test. Two plots are shown below that show sensitivity of the The system was tested at the Northwest EMC facility in buttons as the RF source is scanned from 80 MHz to 1 Sultan, WA on August 19, 2005. The CapSense buttons GHz. Button #5 represents a typical test result for the were tested per the requirements of EN55024 (Amds. group of buttons. Button #6 represents the worst test A1:2001, A2:2003), method IEC61000-4-2, which result for the group. describes two tests: 1. “Contact Test” Figure 5. EN55024 Susceptibility Test Plots The product with the CapSense button array is placed on a dielectric mat that rests upon a conductive plate (“ground plane”). A high-voltage ESD generator is repeatedly brought into contact with exposed conductive material on the case of the product (connectors, bezels, etc.). A second plate is placed orthogonal to the product and the ground plane. The ground plane is stimulated with the ESD generator. The position of the product and the secondary conductive plate is shifted and the ground plane is stimulated again. This test was performed at +/-9 kV. 2. “Air Test” An ESD probe is brought into contact with non-conductive components on the product under test (keypad and LCD). This test was performed at +/-15 kV. As with ESD testing for any product, PSoC CapSense boards presented a “discovery opportunity.” Erroneous button presses found during the initial 9-kV contact test were eliminated with detection algorithm updates that were incorporated into the design of the Capacitive Switch, Relaxation Oscillator (CSR) User Module. The 15- kV air test was passed on the first attempt without any observed unintended behavior. September 16, 2005 Document No. 001-31162 Rev. ** 4 [+] Feedback
    • AN2318 Design References About the Author Name: Design for electromagnetic compatibility considerations is Mark Lee Title: an important and exhaustively published topic. There are Senior Applications Engineer literally hundreds of texts on the subject. Some favorite Cypress MicroSystems titles include: Contact: olr@cypress.com Henry Ott, Noise Reduction Techniques in Electronic 425.787.4804 Systems, 2nd Edition. John Wiley & Sons. David Terrell and R. Kenneth Keenan, Digital Design for Interference Specifications, A Practical Handbook for Emi Suppression. Newnes. William D. Kimmel and Daryl D. Gerke, Electromagnetic Compatibility in Medical Equipment: A Guide for Designers and Installers. IEEE Press In March of 2007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new documentation number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions. PSoC is a registered trademark of Cypress Semiconductor Corp. quot;Programmable System-on-Chip,quot; PSoC Designer, and PSoC Express are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: 408-943-2600 Fax: 408-943-4730 http://www.cypress.com/ © Cypress Semiconductor Corporation, 2005-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. September 16, 2005 Document No. 001-31162 Rev. ** 5 [+] Feedback