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denme

  1. 1. An Overview of Serial ATA Technology Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 [email_address]
  2. 2. Objectives <ul><li>Why SATA was invented </li></ul><ul><li>The differences between PATA and SATA </li></ul><ul><li>How the hardware is structured to transmit and receive SATA </li></ul><ul><li>Protocol of SATA transmission </li></ul>
  3. 3. What is PATA? <ul><li>All of the below synonyms refer to a modern day PATA drive </li></ul><ul><ul><li>PATA – Parallel Advanced Technology Attachment </li></ul></ul><ul><ul><li>UDMA – Ultra Direct Memory Access </li></ul></ul><ul><ul><li>IDE – Integrated Device Electronics </li></ul></ul><ul><ul><li>EIDE – Enhanced IDE </li></ul></ul>
  4. 4. More on PATA <ul><li>40 & 80 wire cable option </li></ul><ul><ul><li>40 wire limited to UDMA 33 MB/s and below </li></ul></ul><ul><ul><li>80 wire allowed for UDMA 66, 100, 133 MB/s </li></ul></ul><ul><li>Required by ATA spec to be 5v tolerant (3.3v has been the norm for several years) </li></ul><ul><li>Must support Master/Slave/Cable Select </li></ul>
  5. 5. SATA Basics <ul><li>New Connector </li></ul><ul><ul><li>Saves space </li></ul></ul><ul><ul><li>More reliable </li></ul></ul><ul><ul><li>More air flow </li></ul></ul><ul><li>Connector has 4 transmission wires </li></ul><ul><ul><li>Tx differential pair </li></ul></ul><ul><ul><li>Rx differential pair </li></ul></ul>
  6. 6. SATA Basics <ul><li>SATA I for 1.5Gbps ~ 150MB/s </li></ul><ul><li>SATA II for 3.0Gbps ~ 300MB/s </li></ul><ul><li>Provides support for legacy command set </li></ul><ul><li>Includes new commands for SATA BIST and power management </li></ul>
  7. 7. Connectivity <ul><li>Serial ATA is point-to-point topology </li></ul><ul><ul><li>Hosts can support multiple devices but requires multiple links </li></ul></ul><ul><ul><li>100% available link bandwidth </li></ul></ul><ul><ul><li>Failure of one device or link does not affect other links </li></ul></ul>
  8. 8. Link Characteristics <ul><li>SATA uses full-duplex links </li></ul><ul><ul><li>Protocol only permits frame transfer in one direction at a time </li></ul></ul><ul><ul><li>Each link consists of a transmit and a receive pair </li></ul></ul><ul><li>SATA uses low voltage levels </li></ul><ul><ul><li>Nominal voltage +/-250mV differential </li></ul></ul>
  9. 9. Power Management <ul><li>SATA has </li></ul><ul><ul><li>Phy Ready – Capable of sending and receiving data. Main phase locked loop are on and active </li></ul></ul><ul><ul><li>Partial – Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 us. </li></ul></ul><ul><ul><li>Slumber – Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 ms. </li></ul></ul><ul><li>ATA also defines IDLE, STANDBY, and SLEEP </li></ul><ul><li>Necessary for newer laptop & mobile devices </li></ul>
  10. 10. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
  11. 11. Physical Layer <ul><li>Transmission (Tx) and Reception (Rx) of a 1.5Gb/s serial stream </li></ul><ul><li>Perform power on sequencing </li></ul><ul><li>Perform speed negotiation </li></ul><ul><li>Provide status to link layer </li></ul><ul><li>Support power management requests </li></ul><ul><li>Out-of-Band (OOB) signal generation and detection </li></ul>
  12. 12. Out of Band <ul><li>Part of normal power on sequence </li></ul><ul><li>Allows host to issue a device hard reset </li></ul><ul><li>Allows device to request a hard reset </li></ul><ul><li>Brings device out of low power state </li></ul>
  13. 13. Out of Band Signals <ul><li>COMRESET </li></ul><ul><ul><li>Always originated by the host </li></ul></ul><ul><ul><li>Forces a hard reset in the device </li></ul></ul><ul><ul><li>Used to start link initialization </li></ul></ul><ul><li>COMINIT </li></ul><ul><ul><li>Always originated by the device </li></ul></ul><ul><ul><li>Requests a link reset </li></ul></ul><ul><ul><li>Issued by device in response to COMRESET </li></ul></ul>
  14. 14. Out of Band Signals (cont.) <ul><li>COMWAKE </li></ul><ul><ul><li>Can be originated by either host or device </li></ul></ul><ul><ul><li>Used as final phase of OOB initialization </li></ul></ul><ul><ul><li>Used to bring out of low power & test states </li></ul></ul><ul><ul><ul><li>Exit Partial </li></ul></ul></ul><ul><ul><ul><li>Exit Slumber </li></ul></ul></ul><ul><ul><ul><li>Exit BIST </li></ul></ul></ul>
  15. 15. Out of Band Signal Forms COMRESET / COMINIT COMWAKE 106.7 ns 106.7 ns 106.7 ns 320 ns
  16. 16. Out of Band Signaling Protocol COMRESET COMWAKE COMINIT COMWAKE Host Device
  17. 17. SATA Port Model Clock & Data Recovery Serializer Deserializer Analog Front End OOB Detect COMRESET / COMINIT COMWAKE Data Out RX Clock Port Control Logic Tx Clock Align Generator Data In Phy Reset Phy Ready Slumber Partial SPD Mode System Clock SPD Select Tx + Tx - Rx - Rx +
  18. 18. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
  19. 19. Link Layer <ul><li>8b / 10b encoding </li></ul><ul><li>Scrambles and descrambles data and control words </li></ul><ul><li>Converts data from transport layer into frames </li></ul><ul><li>Conduct CRC generation and checking </li></ul><ul><li>Provides frame flow control </li></ul>
  20. 20. Encoding Concepts <ul><li>All 32 bit Dwords are encoded for SATA </li></ul><ul><ul><li>32 bits data = 40 bits of transmission </li></ul></ul><ul><li>Provides sufficient transition density </li></ul><ul><ul><li>Guarantees transition (0s and 1s) even if data is 0x00 or 0xFF </li></ul></ul><ul><li>Provides an easy way to detect transmission error </li></ul>
  21. 21. Current Running Disparity (CRD ) <ul><li>As each character is encoded a count is maintained of the number of 0’s and 1’s being transmitted </li></ul><ul><ul><li>More 1’s than 0’s give positive disparity </li></ul></ul><ul><ul><li>More 0’s than 1’s gives negative disparity </li></ul></ul><ul><ul><li>Same number gives neutral disparity </li></ul></ul><ul><li>Only valid values of CRD are -1 and 1 </li></ul><ul><ul><li>Any other value indicates that a transmission error has occurred </li></ul></ul>
  22. 22. CRD+ & CRD- Encoded Characters 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1 8b Character 0x3F This 10b Character transmitted when CRD negative This 10b Character transmitted when CRD positive This character 6 ones 4 zeros Disparity +2 This character 4 ones 6 zeros Disparity -2
  23. 23. SATA Primitives <ul><li>Convey real-time state information </li></ul><ul><li>Control transfer of information between host and device </li></ul><ul><li>Provide host/device coordination </li></ul>
  24. 24. SATA Primitives <ul><li>ALIGN – Speed negotiation and at least every 256 Dword </li></ul><ul><li>SYNC – Used when in idle to maintain bit synchronization </li></ul><ul><li>CONT – Used to suppress repeated primitives </li></ul>
  25. 25. SATA Primitives <ul><li>X_RDY </li></ul><ul><li>R_RDY </li></ul><ul><li>R_IP </li></ul><ul><li>R_OK </li></ul><ul><li>R_ERR </li></ul><ul><li>SOF </li></ul><ul><li>EOF </li></ul><ul><li>HOLD </li></ul><ul><li>HOLDA </li></ul>
  26. 26. SATA Frame Structure <ul><li>All SATA frames consist of: </li></ul><ul><ul><li>A start of frame (SOF) delimiter </li></ul></ul><ul><ul><li>A payload – transport layer information </li></ul></ul><ul><ul><li>A Cyclic Redundancy Check (CRC) </li></ul></ul><ul><ul><li>An end of frame (EOF) delimiter </li></ul></ul>SOF CRC EOF Payload Data
  27. 27. Link Layer Protocol (1) Host Device SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC
  28. 28. Link Layer Protocol (2) Host Device SYNC SYNC X_RDY X_RDY X_RDY X_RDY SYNC SYNC SYNC SYNC SYNC SYNC
  29. 29. Link Layer Protocol (3) Host Device X_RDY X_RDY X_RDY X_RDY X_RDY X_RDY SYNC R_RDY R_RDY R_RDY R_RDY SYNC
  30. 30. Link Layer Protocol (4) Host Device X_RDY X_RDY SOF DATA DATA DATA R_RDY R_RDY R_RDY R_RDY R_RDY R_RDY
  31. 31. Link Layer Protocol (5) Host Device DATA DATA DATA DATA DATA DATA R_RDY R_IP R_IP R_IP R_IP R_RDY
  32. 32. Link Layer Protocol (6) Host Device DATA DATA CRC EOF WTRM WTRM R_IP R_IP R_IP R_IP R_IP R_IP
  33. 33. Link Layer Protocol (7) Host Device CRC EOF WTRM WTRM WTRM WTRM R_IP R_IP R_IP R_IP R_IP R_IP
  34. 34. Link Layer Protocol (8) Host Device WTRM WTRM WTRM WTRM WTRM WTRM R_IP R_OK R_OK R_OK R_OK R_IP
  35. 35. Link Layer Protocol (9) Host Device WTRM WTRM SYNC SYNC SYNC SYNC R_OK R_OK R_OK R_OK R_OK R_OK
  36. 36. Link Layer Protocol (last) Host Device SYNC SYNC SYNC SYNC SYNC SYNC R_OK SYNC SYNC SYNC SYNC R_OK
  37. 37. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
  38. 38. Transport Layer <ul><li>Responsible for the management of Frame Information Structures (FIS) </li></ul><ul><li>At the command of Application layer: </li></ul><ul><ul><li>Format the FIS </li></ul></ul><ul><ul><li>Make frame transmission request to Link layer </li></ul></ul><ul><ul><li>Pass FIS contents to Link layer </li></ul></ul><ul><ul><li>Receive transmission status from Link layer and reports to Application layer </li></ul></ul>
  39. 39. Frame Information Structure (FIS) <ul><li>A FIS is a mechanism to transfer information between host and device application layers </li></ul><ul><ul><li>Shadow Register Block contents </li></ul></ul><ul><ul><li>ATA commands </li></ul></ul><ul><ul><li>Data movement setup information </li></ul></ul><ul><ul><li>Read and write data </li></ul></ul><ul><ul><li>Self test activation </li></ul></ul><ul><ul><li>Unique FIS Type Code </li></ul></ul>
  40. 40. FIS types D H Data 46h D H PIO Setup 5Fh D H BIST Activate 58h D H DMA Setup 41h D H DMA Activate 39h D H Set Device bits A1h D H Register transfer device to host 34h H D Register transfer host to device 27h Direction Description FIS TYPE CODE
  41. 41. Register – Host to Device FIS Reserved Reserved Reserved Reserved Dword 4 Sector Count Sector Count Reserved Control Dword 3 Sector Number Cyl Low (exp) Cyl High (exp) Features (exp) Dword 2 Sector Number Cyl Low Cyl High Dev/Head Dword 1 FIS TYPE (27h) Reserved Command Features Dword 0 Byte 0 Byte 1 Byte 2 Byte 3
  42. 42. BIST Activate FIS T - Far end transmit only – transmit Dwords defined in words 1 & 2 A - No ALIGN transmission (valid only with T) S - Bypass scrambling (valid only with T) L - Far end retimed loopback with ALIGN insertion F - Far end analog loopback P - Transmit primitives defined in words 1 & 2 of the FIS R - Reserved V - Vendor Unique Test Mode – other bits undefined Data [7:0] Data [15:8] Data [23:16] Data [31:24] 2 Data [7:0] Data [15:8] Data [23:16] Data [31:24] 1 FIS Type 58h Reserved [ TASLFPRV ] Reserved 0 Byte 0 Byte 1 Byte 2 Byte 3
  43. 43. Data FIS Dword N . . . Dword 2 N Dwords of Data Minimum 1 Dword Maximum 2048 Dwords Dword 1 FIS TYPE (46h) Reserved Reserved Reserved Dword 0 Byte 0 Byte 1 Byte 2 Byte 3
  44. 44. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
  45. 45. Command / Application Layer <ul><li>Defined using a series of state diagrams </li></ul><ul><ul><li>Register H  D </li></ul></ul><ul><ul><li>Register D  H </li></ul></ul><ul><ul><li>DMA data in </li></ul></ul><ul><ul><li>DMA data out </li></ul></ul><ul><li>Host command layer may be the same but may only support legacy commands </li></ul>
  46. 46. Completed !! <ul><li>Any Question? Comments? </li></ul>

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