Assignment 1
Heart Murmurs
Heart Operation
Heart Cycle
Phonogram http:// www.wilkes.med.ucla.edu/intro.html
UNIX
UNIX Concept? User Users UNIX kernel Shell Shell Shell Shell Hardware
UNIX Concept System Calls vi UNIX kernel open() close() read() write() Chmod() ksh csh a.out cpp Hardware
UNIX Structure I/O Manager Central Kernel File Manager System Calls Network Manager Buffer Cache Hardware
UNIX Services I/O Manager Central Kernel File Manager System Calls Network Manager Buffer Cache Hardware Process Managemen...
Kernel Source Code <ul><li>usr/src/uts/machine (eg. MIPS) </li></ul><ul><li>../boot  boot  </li></ul><ul><li>../os process...
Kernel Source Code <ul><li>usr/src/uts/machine </li></ul><ul><li>../disp low level process switching </li></ul><ul><li>../...
UNIX Look-alikes <ul><li>AIX IBM </li></ul><ul><li>HP-UX Hewlett-Packard </li></ul><ul><li>OSF/1 Open Software Foundation ...
Computer System Structures Chapter 2
Computer System Disk Controller System Bus CPU Video Printer Controller Memory Controller Display Keypad Expansion RAM
PC Computer
Bootstrap <ul><li>Stored in ROM (read-only memory) </li></ul><ul><li>Initializes CPU registers, memory, controllers </li><...
System Operation <ul><li>I/O devices, CPU execute concurrently </li></ul><ul><li>CPU generally controls data on bus </li><...
Computer System Disk Controller System Bus CPU Video Printer Controller Memory Controller CPU-controlled One per device ty...
Interrupts Device Controller <ul><li>Hardware interrupt </li></ul>Operating System ISR
Interrupts <ul><li>Software interrupt </li></ul>User Code <ul><li>System call </li></ul><ul><li>Error traps </li></ul>Oper...
Interrupts Pr 0 System Stack User Code <ul><li>Return address stored on system stack </li></ul>Operating System User Code ...
“ Data In” Interrupt Sequence <ul><li>Save address of interrupted instruction </li></ul><ul><li>Transfer control to Interr...
Read Request <ul><li>Synchronous  I/O: </li></ul><ul><li>CPU requests read, waits </li></ul><ul><li>Disk controller sends ...
Read Request Disk Controller CPU Memory Controller <ul><li>Asynchronous  I/O: </li></ul><ul><li>CPU requests read, does so...
Device Status Table Task 1 File: zzz Op:  Write Task 1 File: xxx Op:  Read Add: 43026 Len: 20000 Task 2 File: yyy Op:  Wri...
Direct Memory Access (DMA) <ul><li>CPU initiates, does something else </li></ul><ul><li>One interrupt per block of data </...
Data Storage Registers Cache DRAM Magnetic Disk Magnetic Tape Disk Controller CPU Memory Controller
von Neuman Architecture Instruction Register Processor Instruction Random Access Memory Other Registers Operand 1 … Operan...
I/O Architecture Printer Controller CPU Memory Memory-mapped I/O Mapped to device controller registers
I/O Architecture Printer Controller CPU Data Register Control Register 1. Load data byte 2. Set ready bit I/O Port 3. Data...
I/O Architecture Printer Controller CPU Data Register Control Register 5. Poll for cleared bit 6. Send next byte I/O Port ...
I/O Architecture Printer Controller CPU Data Register Control Register 5. Interrupt CPU 6. Send next byte I/O Port Interru...
Magnetic Disks
Storage Hierarchy Registers Cache Main Memory Electronic Disk Magnetic Disk Optical Disk Magnetic Tapes volatile nonvolati...
Instruction Cache Instruction Register Main Memory Instruction Instruction Cache Instruct 1 … Instruct n Instruct n+1 … … ...
Memory as Disk Cache Main Memory Instruction Cache Hard Drive Instruct 1 … Instruct n Instruct n+1 … … … …
Disk Backup System Tape Jukebox Hard Drive Weekly rotation Off-site OO OO OO OO
Cache Coherency Main Memory A’ A A A A CPU 2 Cache CPU 3 Cache CPU 1 Cache CPU 4 Cache … … …
Hardware Protection <ul><li>Illegal instructions </li></ul><ul><li>Address out of range </li></ul>Trap and terminate job O...
Operating Modes <ul><li>Monitor Mode </li></ul><ul><ul><li>System mode </li></ul></ul><ul><ul><li>Supervisor mode </li></u...
I/O Protection User Code Operating System I/O Device
Memory Protection User Code Operating System Interrupt Service Routines Interrupt Vector
Memory Protection User Code Base Register Limit Register
CPU Protection User Code CPU Countdown Timer Time <ul><li>Interrupt long jobs </li></ul>
CPU Protection User Code CPU Countdown Timer Time <ul><li>Time slices for time sharing </li></ul>
Local Area Networks <ul><li>Bluetooth 1 Mb/s </li></ul><ul><li>Ethernet </li></ul><ul><ul><li>10BaseT </li></ul></ul><ul><...
Wide Area Networks R R R CP R CP CP R <ul><li>Routers </li></ul><ul><li>Communication Processors </li></ul>
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2_Computers.ppt

  1. 1. Assignment 1
  2. 2. Heart Murmurs
  3. 3. Heart Operation
  4. 4. Heart Cycle
  5. 5. Phonogram http:// www.wilkes.med.ucla.edu/intro.html
  6. 6. UNIX
  7. 7. UNIX Concept? User Users UNIX kernel Shell Shell Shell Shell Hardware
  8. 8. UNIX Concept System Calls vi UNIX kernel open() close() read() write() Chmod() ksh csh a.out cpp Hardware
  9. 9. UNIX Structure I/O Manager Central Kernel File Manager System Calls Network Manager Buffer Cache Hardware
  10. 10. UNIX Services I/O Manager Central Kernel File Manager System Calls Network Manager Buffer Cache Hardware Process Management Virtual Memory Machine Communications Programmatic Interface Memory Management File System Management System Initialization Fault, trap, interruption, exception handling I/O Device Drivers
  11. 11. Kernel Source Code <ul><li>usr/src/uts/machine (eg. MIPS) </li></ul><ul><li>../boot boot </li></ul><ul><li>../os process management code </li></ul><ul><li>../sys C-language include files </li></ul><ul><li>../fs file management systems </li></ul><ul><li>../io I/O management subsystem </li></ul>
  12. 12. Kernel Source Code <ul><li>usr/src/uts/machine </li></ul><ul><li>../disp low level process switching </li></ul><ul><li>../exec reading and starting executables </li></ul><ul><li>.. /vm memory, virtual memory </li></ul><ul><li>../debug kernel debugging system </li></ul><ul><li>../ml machine-dependent code </li></ul><ul><li>../master.d describe system configuration </li></ul>
  13. 13. UNIX Look-alikes <ul><li>AIX IBM </li></ul><ul><li>HP-UX Hewlett-Packard </li></ul><ul><li>OSF/1 Open Software Foundation </li></ul><ul><li>Ultrix DEC </li></ul><ul><li>IRIX SGI </li></ul><ul><li>UTS Amdahl </li></ul><ul><li>Solaris Sun </li></ul>
  14. 14. Computer System Structures Chapter 2
  15. 15. Computer System Disk Controller System Bus CPU Video Printer Controller Memory Controller Display Keypad Expansion RAM
  16. 16. PC Computer
  17. 17. Bootstrap <ul><li>Stored in ROM (read-only memory) </li></ul><ul><li>Initializes CPU registers, memory, controllers </li></ul><ul><li>Loads operating system </li></ul>
  18. 18. System Operation <ul><li>I/O devices, CPU execute concurrently </li></ul><ul><li>CPU generally controls data on bus </li></ul><ul><li>Device controller for each device type </li></ul><ul><li>Local buffer for each device controller </li></ul><ul><li>I/O is from device to local controller </li></ul><ul><li>Device controller informs CPU that it has finished its operation, by an Interrupt </li></ul>
  19. 19. Computer System Disk Controller System Bus CPU Video Printer Controller Memory Controller CPU-controlled One per device type Concurrent execution Local buffer I/O Flow Interrupt Display Keypad Expansion
  20. 20. Interrupts Device Controller <ul><li>Hardware interrupt </li></ul>Operating System ISR
  21. 21. Interrupts <ul><li>Software interrupt </li></ul>User Code <ul><li>System call </li></ul><ul><li>Error traps </li></ul>Operating System ISR
  22. 22. Interrupts Pr 0 System Stack User Code <ul><li>Return address stored on system stack </li></ul>Operating System User Code Interrupt Handler Interrupt Vector Pr 1 … Pr n Pr n+1
  23. 23. “ Data In” Interrupt Sequence <ul><li>Save address of interrupted instruction </li></ul><ul><li>Transfer control to Interrupt Service Routine </li></ul><ul><li>ISR saves contents of required registers </li></ul><ul><li>ISR checks for error conditions on data input </li></ul><ul><li>ISR takes input, store in buffer </li></ul><ul><li>ISR sets flag to indicate new data </li></ul><ul><li>ISR restores contents of saved registers </li></ul><ul><li>Control back to interrupted instruction </li></ul>
  24. 24. Read Request <ul><li>Synchronous I/O: </li></ul><ul><li>CPU requests read, waits </li></ul><ul><li>Disk controller sends interrupt when done </li></ul>Loop: jmp Loop Disk Controller CPU Memory Controller
  25. 25. Read Request Disk Controller CPU Memory Controller <ul><li>Asynchronous I/O: </li></ul><ul><li>CPU requests read, does something else </li></ul><ul><li>Disk controller sends interrupt when done </li></ul>
  26. 26. Device Status Table Task 1 File: zzz Op: Write Task 1 File: xxx Op: Read Add: 43026 Len: 20000 Task 2 File: yyy Op: Write Add: 03458 Len: 500
  27. 27. Direct Memory Access (DMA) <ul><li>CPU initiates, does something else </li></ul><ul><li>One interrupt per block of data </li></ul>Disk Controller CPU Memory Controller
  28. 28. Data Storage Registers Cache DRAM Magnetic Disk Magnetic Tape Disk Controller CPU Memory Controller
  29. 29. von Neuman Architecture Instruction Register Processor Instruction Random Access Memory Other Registers Operand 1 … Operand n Operand n+1 Accumulator MQ Register Register n Register n+1 … … … …
  30. 30. I/O Architecture Printer Controller CPU Memory Memory-mapped I/O Mapped to device controller registers
  31. 31. I/O Architecture Printer Controller CPU Data Register Control Register 1. Load data byte 2. Set ready bit I/O Port 3. Data byte to device 4. Clear ready bit 1 2 3 4
  32. 32. I/O Architecture Printer Controller CPU Data Register Control Register 5. Poll for cleared bit 6. Send next byte I/O Port Programmed I/O 6 5
  33. 33. I/O Architecture Printer Controller CPU Data Register Control Register 5. Interrupt CPU 6. Send next byte I/O Port Interrupt-driven I/O 6 5
  34. 34. Magnetic Disks
  35. 35. Storage Hierarchy Registers Cache Main Memory Electronic Disk Magnetic Disk Optical Disk Magnetic Tapes volatile nonvolatile $
  36. 36. Instruction Cache Instruction Register Main Memory Instruction Instruction Cache Instruct 1 … Instruct n Instruct n+1 … … … …
  37. 37. Memory as Disk Cache Main Memory Instruction Cache Hard Drive Instruct 1 … Instruct n Instruct n+1 … … … …
  38. 38. Disk Backup System Tape Jukebox Hard Drive Weekly rotation Off-site OO OO OO OO
  39. 39. Cache Coherency Main Memory A’ A A A A CPU 2 Cache CPU 3 Cache CPU 1 Cache CPU 4 Cache … … …
  40. 40. Hardware Protection <ul><li>Illegal instructions </li></ul><ul><li>Address out of range </li></ul>Trap and terminate job Operating System Job 1 Job 2 Job 3 Job 4
  41. 41. Operating Modes <ul><li>Monitor Mode </li></ul><ul><ul><li>System mode </li></ul></ul><ul><ul><li>Supervisor mode </li></ul></ul><ul><ul><li>Privileged mode </li></ul></ul><ul><ul><li>Privileged instructions </li></ul></ul><ul><li>User mode </li></ul>Mode bit Hardware Operating System Job 1 Job 2 Job 3 Job 4
  42. 42. I/O Protection User Code Operating System I/O Device
  43. 43. Memory Protection User Code Operating System Interrupt Service Routines Interrupt Vector
  44. 44. Memory Protection User Code Base Register Limit Register
  45. 45. CPU Protection User Code CPU Countdown Timer Time <ul><li>Interrupt long jobs </li></ul>
  46. 46. CPU Protection User Code CPU Countdown Timer Time <ul><li>Time slices for time sharing </li></ul>
  47. 47. Local Area Networks <ul><li>Bluetooth 1 Mb/s </li></ul><ul><li>Ethernet </li></ul><ul><ul><li>10BaseT </li></ul></ul><ul><ul><li>100BaseT </li></ul></ul><ul><ul><li>100 Gb/s </li></ul></ul><ul><li>Twisted pair </li></ul><ul><li>Fiber optic </li></ul>
  48. 48. Wide Area Networks R R R CP R CP CP R <ul><li>Routers </li></ul><ul><li>Communication Processors </li></ul>

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