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2.1                                                  2.1USING A CUSTOM-BUILT HDL FORPRINTED CIRCUIT BOARD DESIGN          ...
Sponsorship   Sandia National Laboratories is a multi- program laboratory managed and operated   by Sandia Corporation, a ...
Who Are We?•    Dr. Brent Nelson          (Professor)•    Brad Riching              (MS student)•    Richard Black        ...
Overview•  Why HDL’s for PCB design capture?•  PHDL – An HDL for PCB design capture   –  The language   –  The tool flow• ...
2.1Part 1MOTIVATION: HDL’S FORPCB DESIGN            5
Graphical Schematic Entry•  Imitates manual drawing  –  Intuitive  –  Spatial information + human visual system è        ...
HDL’s for PCB Design                          netlist•  Design capture                     •  Physical design   –  Capture...
Schematic Scalability                    Note: this entire page is                    mainly the symbol for               ...
Drawing a Schematic Net•  subroutine drawSchematicNet() {    foreach pin in net {      1. pan to page and area of pin     ...
Design File Management                            Need a mechanism                            for naming and•    PowerSupp...
Design Change Tracking •  Design changes between two versions?   % diff a.sch b.sch
   Binary files a.sch and b.sch differ...
Design Sharing•  Sharing a design amongst a team  –  Divide and conquer•  Design reuse  –  How do you reuse portions of a ...
Schematic Tools: Proprietary Source•  Schematic design files:  –  Traditionally in protected, binary formats  –  Specializ...
2.1Part 2INTRO TO PHDL           14
What is PHDL?   Schematic Capture                      PCB Layout    produces netlist                    interprets netlis...
PHDL: A First Example•  Our example circuit:            R1	     120	     S1	              R2	     120	     S2	            ...
PHDL: A First Example•  Four types of devices            R1	     120	     S1	              R2	     120	     S2	           ...
Defining Devicesdevice Resistor {	            attr REPREFIX= “R”;	            attr FOOTPRINT = “M0805”;	            attr L...
Defining Devices: Multi-Bit Pinsdevice SevenSeg { 	         attr REFPREFIX = “LD”;	         attr FOOTPRINT = “SA08-21”;	  ...
Creating The Design                                                   R1	     120	     S1	  // Define the design and give ...
Creating The Design: Nets                                                   R1	     120	     S1	  // Define the design and...
Creating The Design: Nets                                                   R1	     120	     S1	  // Define the design and...
Creating The Design: Multi-Bit Nets                                                   R1	     120	     S1	                ...
Creating The Design: Multi-Bit Nets                                                   R1	     120	     S1	  // Define the ...
Creating The Design: Instancing Devices                                                R1	     120	     S1	               ...
Creating The Design: Instancing Devices                                                   R1	     120	     S1	            ...
Creating The Design: Instance Array                                                    R1	     120	     S1	  inst(1:8) swA...
Creating a Design: Wiring Up Pins                                                   R1	     120	     S1	  inst(1:8) swArra...
Creating a Design: Setting Inst Attributes                                                 R1	     100	     S1	  inst(1:8)...
Creating a Design: Wiring Up Pins                                                       R1	     100	     S1	              ...
The Complete Example Design (a)device Resistor {	                   device Battery {	        attr REFPREFIX = "R";	       ...
The Complete Example Design (b)design ssControl {	        net gnd, vcc;	        net[1:8] segs, r2sw;	   	        inst sour...
Compilation Flow$java –jar phdlcomp.jar srcFolder [switches]                        Command line                          ...
A Netlist!PADS-POWERPCB-V9.0-MILS! NETLIST FILE FROM PADS LOGIC V9.3*PART*                        !                       ...
A Bill of Materials•  A comma-separated file   –  Import into Excel to view   –  One column for each unique attribute     ...
Targeted Design FlowsMentor Graphics PADS                   EAGLE PCB                       Others coming                 ...
2.1Part 3PHDL:DIGGING A LITTLE DEEPER…           37
Array indexingnet[1:8] segs;	  // Leftmost wire is “segs[1]”	                                                •  Can instan...
Wiring Up Ports and Nets (1)net gnd;	  net[1:8] net1, net2;	   	                                                          ...
Wiring Up Ports and Nets (2)net gnd, vcc;	  net[1:8] net1, net2;	   	  inst(1:8) res of Resistor {	   	                   ...
Wiring Up Ports and Nets (3)                                                             R1	                              ...
PHDL Packages (1)package myParts {	   	                                             •  Declare devices to be in      devic...
PHDL Packages (2)package myParts {	     	                                     •    Declare devices to be in a        devic...
PHDL Subdesigns (1)subdesign rc {	                               design myCircuit {	        port gnd, in, out;	           ...
PHDL Subdesigns (2)                                             design myCircuit {	                                       ...
PHDL Subdesigns (3)                                                design myCircuit {	                                    ...
2.1Part 4A REAL PHDL BOARD:FPGA-BASED MOTOR CONTROL           47
BYU Proof of Concept BoardFPGA-based motor controller (2-axes)  –  Spartan3 400K 144-pin QFP implements:    •  32-bit posi...
Motor Controller Board   Final	  Layout	                                Design Entry:                              ~1200 l...
Motor Controller Board     Back From Manufacturing               50
Motor Controller Board        Assembled Top                Bottom
Motor Controller Board                               JTAGPower Supply 12VDC IN:                               Motor Power ...
2.1Part 5SOURCE CODE CONTROLSYSTEMS (SCCS)          53
Motivation•  SCCS provides a remote repository  –  Collaborate between users  –  Saves all design versions     •  Document...
The Old Binary File Way•    PowerSupp.sch•    PowerSupp_new.sch                                   Each is a different vers...
The SCCS Way (CVS)"% cvs diff"cvs diff: Diffing ."Index: a.phdl"============================================="RCS file: /f...
The SCCS Way (Eclipse IDE)              This shows that line 31 has changed.     Comparison between local copy and archive...
2.1Part 6THE ECLIPSE PLUG-IN FORPHDL            58
Eclipse PHDL Plug-In                                                 An outlineThe files in my project                    ...
Real-Time Syntax Checking (1)Error mark shows up instantlyMouse hover gives popup error message                           ...
Real-Time Syntax Checking (2)When possible, IDE proposes“Quick Fixes”.                              61
Content Assist (1)                 Key click brings up                 context-specific content                 suggestion...
Content Assist (2)                 Template has been inserted.                 Tab between fields to fill it in.          ...
Content Interrogation                 Hovering over a named element                 will give its definition              ...
Integration with SCCS (SVN)        Project navigator screen shows    which files are out of date with repository.         ...
SVN Synchronize Screen                       Click icons to check files into repositoryList of files thathave been modifie...
2.1Part 73RD PARTY TOOLS            67
Example: FPGA Pin Generation (csv2phdl)     FPGA VHDL                               Synthesis, PAR,               PHDL Dev...
Example: Automatic Device Generation                         (DeviceGen)  •  Eagle device files are in XML format        –...
2.1Part 8PHDL IS OPEN SOURCEAND AVAILABLE           70
phdl.sourceforge.net          71
phdl.sourceforge.net          72
Acknowledgements•  Sandia National Laboratories  –  Supported the work  –  Provided technical direction and management  – ...
2.1Part 8FUTURE WORK          74
Future Tasks•  Library integration•  Hierarchical refdes generation  –  Provide natural grouping mechanism•  Connectivity ...
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Transcript of "PCBWest presentation 2012"

  1. 1. 2.1 2.1USING A CUSTOM-BUILT HDL FORPRINTED CIRCUIT BOARD DESIGN CAPTURE Brent Nelson Brad Riching Josh Mangelson Dept. of Electrical and Computer Engineering Brigham Young University August 2012
  2. 2. Sponsorship Sandia National Laboratories is a multi- program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation,for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000. SAND Number : 2012-6638 C 2
  3. 3. Who Are We?•  Dr. Brent Nelson (Professor)•  Brad Riching (MS student)•  Richard Black (BS student)•  Joshua Mangelson (BS student) –  Dept. of Electrical and Computer Engineering –  Brigham Young University 3
  4. 4. Overview•  Why HDL’s for PCB design capture?•  PHDL – An HDL for PCB design capture –  The language –  The tool flow•  Examples of PHDL board designs•  Examples of 3rd party support tools and utilities•  Links to PHDL open source community•  Future Work 4
  5. 5. 2.1Part 1MOTIVATION: HDL’S FORPCB DESIGN 5
  6. 6. Graphical Schematic Entry•  Imitates manual drawing –  Intuitive –  Spatial information + human visual system è understanding –  Current industrial practive•  Would seem to be the best method ! QED… 6
  7. 7. HDL’s for PCB Design netlist•  Design capture •  Physical design –  Capture designer’s intent –  Physical design rules –  Define design –  Electrical considerations components and (voltage, current, connectivity capacitance, inductance) –  Best done using HDL’s –  Best done using current layout tools & methods 7
  8. 8. Schematic Scalability Note: this entire page is mainly the symbol for a single 784 pin FPGA It is one of 20-30 such pages. 8
  9. 9. Drawing a Schematic Net•  subroutine drawSchematicNet() { foreach pin in net { 1. pan to page and area of pin 2. zoom in on pin 3. attach wire stub to pin 4. add textual name to wire stub 5. zoom back out 6. repeat }•  How many mouse clicks per pin? –  5? 10? 20? 30? (many)•  How many nets in a design?•  How do you do a design review? –  From printed schematics… –  From a schematic design tools… So, just how again is this graphical approach helping me? 9
  10. 10. Design File Management Need a mechanism for naming and•  PowerSupp.sch managing design versions.•  PowerSupp_new.sch Need a mechanism for storing all design•  PowerSupp_newer.sch versions•  PowerSupp_june15.sch Need a mechanism for allowing for checking•  PowerSupp_v1_3.sch in and checking out of design versions•  … 10
  11. 11. Design Change Tracking •  Design changes between two versions? % diff a.sch b.sch
 Binary files a.sch and b.sch differ
 %" Need a mechanism for comparing design versions and documenting Individual design changesThat’s not very helpful… Source code control systems (SCCS’s) have done this for years for software 11
  12. 12. Design Sharing•  Sharing a design amongst a team –  Divide and conquer•  Design reuse –  How do you reuse portions of a schematic between designs? 12
  13. 13. Schematic Tools: Proprietary Source•  Schematic design files: –  Traditionally in protected, binary formats –  Specialized tools just to view source… •  Edit, manipulate, analyze?•  Wrong version of proprietary CAD tool? –  Cannot even open the schematic•  Discourages/prevents 3rd party tools 13
  14. 14. 2.1Part 2INTRO TO PHDL 14
  15. 15. What is PHDL? Schematic Capture PCB Layout produces netlist interprets netlist netlist PHDL Bill ofPHDL compiler Material,Source other Code ancillary data 15
  16. 16. PHDL: A First Example•  Our example circuit: R1   120   S1   R2   120   S2   LD1   R3   120   S3   2   15   R4   120   S4   13   11   R5   120   S5   5   3   4   R6   120   S6   14   12   10   17   R7   120   S7   SA08-­‐21   R8   120   S8   +   G1   -­‐   16
  17. 17. PHDL: A First Example•  Four types of devices R1   120   S1   R2   120   S2   LD1   R3   120   S3   2   15   R4   120   S4   13   11   R5   120   S5   5   3   4   R6   120   S6   14   12   10   17   R7   120   S7   SA08-­‐21   R8   120   S8   +   G1   -­‐  •  Plus some wires 17
  18. 18. Defining Devicesdevice Resistor {   attr REPREFIX= “R”;   attr FOOTPRINT = “M0805”;   attr LIBRARY = “complib”;   attr VALUE= “120”;   pin a = {1};   1 pin b = {2};  }     R?// Comments are allowed.   M0805// Compiler will auto-assign full refDes’s    // REFPREFIX, FOOTPRINT, and LIBRARY required.// Other attributes optional.  // May include manufacturer, cost, part #, …   value=120// Used for bill of materials    // In this case, there is an additional 2// user-defined “VALUE” attribute of “120”// Pin mappings are “logicalName” = “physicalName”;   18
  19. 19. Defining Devices: Multi-Bit Pinsdevice SevenSeg {   attr REFPREFIX = “LD”;   attr FOOTPRINT = “SA08-21”;   LD? attr LIBRARY = "myLib";       2   // Multi-bit pins are allowed   pin[1:8] segments = {2,15,13,11,5,3,14,10};   15   pin[1:3] anode = {4,12,17};     13  }   11  /*   For multi-bit pins, the indices could   5   be any of [1:8] or [8:1] or [7:0]   or even [0:7].   3   4   The bits are matched up left-to-right   12   14   with the physical pin numbers.   Thus, segments[1] = {2} and   10   17   segments[8] = {10}  */   SA08-21 19
  20. 20. Creating The Design R1   120   S1  // Define the design and give it a name   LD1   R2   120   S2  design sevenSeg {     R3   120   S3   2   // Define the wires   15   net gnd, vcc;   R4   120   S4   13     11   // Define a multi-bit wire   R5   120   S5   5   net[1:8] segs, r2sw;   3   4   R6   120   S6   14   12   10   17   R7   120   S7   SA08-­‐21   R8   120   S8   +   G1   -­‐   20
  21. 21. Creating The Design: Nets R1   120   S1  // Define the design and give it a name   R2   120   S2   LD1  design sevenSeg {     R3   120   S3   2   // Define the wires   15   net gnd, vcc;   R4   120   S4   13     11   // Define a multi-bit wire   R5   120   S5   5   net[1:8] segs, r2sw;   3   4   R6   120   S6   14   12   10   17   R7   120   S7   SA08-­‐21   R8   120   S8   +   G1   -­‐   21
  22. 22. Creating The Design: Nets R1   120   S1  // Define the design and give it a name   R2   120   S2   LD1  design sevenSeg {     R3   120   S3   2   // Define the wires   15   net gnd, vcc;   R4   120   S4   13     11   // Define a multi-bit wire   R5   120   S5   5   net[1:8] segs, r2sw;   3   4   R6   120   S6   14   12   10   17   R7   120   S7   SA08-­‐21   R8   120   S8   +   G1   -­‐   22
  23. 23. Creating The Design: Multi-Bit Nets R1   120   S1   R2   120   S2   LD1  // Define the design and give it a name  design sevenSeg {   R3   120   S3   2     15   // Define the wires   R4   120   S4   13   net gnd, vcc;   11     R5   120   S5   5   // Define a multi-bit wire   3   net[1:8] segs, r2sw;   4   R6   120   S6   14   12   10   17   R7   120   S7   SA08-­‐21   R8   120   S8   +   G1   -­‐   23
  24. 24. Creating The Design: Multi-Bit Nets R1   120   S1  // Define the design and give it a name   R2   120   S2   LD1  design sevenSeg {     R3   120   S3   2   // Define the wires   15   net gnd, vcc;   R4   120   S4   13   11     R5   120   S5   5   // Define a multi-bit wire   net[1:8] segs, r2sw;   3   4   R6   120   S6   14   12   10   17   R7   120   S7   SA08-­‐21   R8   120   S8   +   G1   -­‐   24
  25. 25. Creating The Design: Instancing Devices R1   120   S1   R2   120   S2   LD1   R3   120   S3   2  inst source of Battery {   15   pos = vcc;   R4   120   S4   13   neg = gnd;   11  }   R5   120   S5   5     3   4  // Create an instance of the “Battery” R6   120   S6   14   12  device   10   17  // Wire its individual ports to nets   R7   120   S7  // Port “pos” -> net “vcc”   SA08-­‐21  // Port “neg” -> net “gnd” R8   120   S8   +   G1   -­‐   25
  26. 26. Creating The Design: Instancing Devices R1   120   S1   R2   120   S2   LD1   inst segment of SevenSeg {   R3   120   S3   2   segments = segs;   15   anode = <vcc>;   R4   120   S4   13   }   11   R5   120   S5   5     3   // Instance the seven segment chip 4   R6   120   S6   14   12   10   17   // Tie pins segments[1:8] -> net segs[1:8] R7   120   S7   SA08-­‐21   // Tie all the “anode” pins (anode[1:3]) // to “vcc”. R8   120   S8   +   // <…> notation = make as many copies of G1   -­‐   // “vcc” as needed to match the width of // the “anode” pin. 26
  27. 27. Creating The Design: Instance Array R1   120   S1  inst(1:8) swArray of Switch {   combine(a) = r2sw;   R2   120   S2   LD1   combine(b) = segs;  };   R3   120   S3   2     15     R4   120   S4   13   11  // Make an array of 8 “Switch” instances   R5   120   S5   5    // The instances will be numbered from 3   4   R6   120   S6  // 1 to 8   14   12     10   17   R7   120   S7  // Since this is an instance array, SA08-­‐21  // you use (…)’s   R8   120   S8   +  // For multi-bit nets and pins, G1   -­‐  // you use […]’s 27
  28. 28. Creating a Design: Wiring Up Pins R1   120   S1  inst(1:8) swArray of Switch { combine(a) = r2sw; LD1   R2   120   S2   combine(b) = segs;} R3   120   S3   2     15     R4   120   S4   13  // Take all the “a” pins on the “Switch” 11  // instances, combine them left to right R5   120   S5   5  // into a bus, and wire them to the bits of 3   4  // the “r2sw” net   R6   120   S6   14   12     10   17  // Remember, the “r2sw” net is 8 bits wide. R7   120   S7   SA08-­‐21  // Thus, swArray(1:8).a -> r2sw[1:8] R8   120   S8   +   G1   -­‐   28
  29. 29. Creating a Design: Setting Inst Attributes R1   100   S1  inst(1:8) rArray of Resistor {   R2   100   S2   LD1   this(1:7).VALUE = “100”;   this(8).VALUE = “75”; R3   100   S3   2   combine(a) = r2sw;   15   b = gnd;   R4   100   S4   13  }   11     R5   100   S5   5     3   4  // Set some “value” attributes R6   100   S6   14   12  // to “100”.  That is, over-ride their 10   17   R7   100   S7  // resistance values from the default// of 120 to 100. Set one of the SA08-­‐21  // “value” attributes to “75”.   R8   75   S8   +     G1   -­‐  // This shows how you can over-ride// predefined attribute values when you// instance a device.   29
  30. 30. Creating a Design: Wiring Up Pins R1   100   S1   R2   100   S2   LD1  inst(1:8) rArray of Resistor {   VALUE = “120”;   R3   100   S3   2   combine(a) = r2sw;   15   b = gnd;   R4   100   S4   13  }   11     R5   100   S5   5  // Take each “b” pin and 3   4  // individually tie it to the  “gnd” net.   R6   100   S6   14   12   10   17   R7   100   S7   SA08-­‐21   R8   100   S8   +   G1   -­‐   30
  31. 31. The Complete Example Design (a)device Resistor {   device Battery {   attr REFPREFIX = "R";   attr REFPREFIX = "G";   attr FOOTPRINT= "M0805";   attr FOOTPRINT= "1V60R";   attr LIBRARY = "complib";   attr LIBRARY = "complib";   attr VALUE = "120";   attr VALUE = "9V";   pin a = {1};   pin pos = {2};   pin b = {2};   pin neg = {1};  }   }  device Switch {   device SevenSeg {   attr REFPREFIX = "SW";   attr REFPREFIX = "LD";   attr FOOTPRINT= "MS243";   attr FOOTPRINT= “SA08-21";   attr LIBRARY = "complib";   attr LIBRARY = “myLib";   pin a = {1};   pin[1:8] segments = {2,15,13,11,5,3,14,10};   pin b = {2};   pin[1:3] anode = {4,12,17};  }   }   31
  32. 32. The Complete Example Design (b)design ssControl {   net gnd, vcc;   net[1:8] segs, r2sw;     inst source of Battery {   pos = vcc; R1   100   S1   neg = gnd;   }   R2   100   S2   LD1     inst segment of SevenSeg {   R3   100   S3   2   segments = segs; 15   anode = <vcc>;   R4   100   S4   13   }   11     R5   100   S5   5   inst(1:8) swArray of Switch {   3   4   combine(a) = r2sw; R6   100   S6   14   12   combine(b)=segs;   10   17   }   R7   100   S7     SA08-­‐21   inst(1:8) rArray of Resistor {   R8   75   S8   +   this(1:7).VALUE = “100”;   G1   this(8).VALUE = “75”;   -­‐   combine(a) = r2sw; b = gnd;   }  }   32
  33. 33. Compilation Flow$java –jar phdlcomp.jar srcFolder [switches] Command line flow •  Netlist •  Bill of MaterialsPHDL PHDL   Output •  Component List filessource Compiler   •  Layout Directions •  XML •  Tool-specific ScriptsCommand line switches Eclipse flow: Compiler runs every time you save your design. 33
  34. 34. A Netlist!PADS-POWERPCB-V9.0-MILS! NETLIST FILE FROM PADS LOGIC V9.3*PART* ! *CONNECTION* *SIGNAL* SEGS[1]G1 complib@1V60R *SIGNAL* GND LD1.2 SW1.2LD1 complib@MS243 G1.1 R1.2 *SIGNAL* SEGS[2]R1 complib@M0805 R1.2 R2.2 LD1.15 SW2.2R2 complib@M0805 R2.2 R3.2 *SIGNAL* SEGS[3]R3 complib@M0805 R3.2 R4.2 LD1.13 SW3.2R4 complib@M0805 R4.2 R5.2 *SIGNAL* SEGS[4] R5.2 R6.2 LD1.11 SW4.2R5 complib@M0805 R6.2 R7.2 *SIGNAL* SEGS[5]R6 complib@M0805 R7.2 R8.2 LD1.5 SW5.2R7 complib@M0805 *SIGNAL* R2SW[1] *SIGNAL* SEGS[6]R8 complib@M0805 SW1.1 R1.1 LD1.3 SW6.2SW1 complib@MS243 *SIGNAL* R2SW[2] *SIGNAL* SEGS[7]SW2 complib@MS243 SW2.1 R2.1 LD1.14 SW7.2 *SIGNAL* R2SW[3] *SIGNAL* SEGS[8]SW3 complib@MS243 SW3.1 R3.1 LD1.10 SW8.2SW4 complib@MS243 *SIGNAL* R2SW[4] *SIGNAL* VCCSW5 complib@MS243 SW4.1 R4.1 G1.2 LD1.4SW6 complib@MS243 *SIGNAL* R2SW[5] LD1.4 LD1.12SW7 complib@MS243 SW5.1 R5.1 LD1.12 LD1.17SW8 complib@MS243 *SIGNAL* R2SW[6] SW6.1 R6.1 *END* *SIGNAL* R2SW[7] SW7.1 R7.1 *SIGNAL* R2SW[8] SW8.1 R8.1 34
  35. 35. A Bill of Materials•  A comma-separated file –  Import into Excel to view –  One column for each unique attribute •  Mandatory and user-defined QUANTITY, NAME, REFDES, LIBRARY, FOOTPRINT, VALUE 1, Battery, G1, complib, 1V60R, 9V 1, SevenSeg, LD1, complib, MS243, 8, Switch, SW1; SW2; SW3; SW4; SW5; SW6; SW7; SW8, complib, MS243, 8, Resistor, R1; R2; R3; R4; R5; R6; R7; R8, complib, M0805, 100 35
  36. 36. Targeted Design FlowsMentor Graphics PADS EAGLE PCB Others coming soon… 36
  37. 37. 2.1Part 3PHDL:DIGGING A LITTLE DEEPER… 37
  38. 38. Array indexingnet[1:8] segs;  // Leftmost wire is “segs[1]”   •  Can instantiate using// Rightmost wire is “segs[8]”     any indexing desiredinst(1:8) swArray of Switch {   …  }  // Leftmost Switch known as “this(1)”  // Rightmost Switch known as “this(8)”   •  Uses notion of left-to-     right ordering<OR>    inst(7:0) swArray of Switch {   …  }  // Leftmost Switch known as “this(7)”  // Rightmost Switch known as “this(0)”   38
  39. 39. Wiring Up Ports and Nets (1)net gnd;  net[1:8] net1, net2;     R1   net1[1]  inst(1:8) res of Resistor {     R2   net1[2]   // Each ‘a’ port on each resistor is tied R3   // to ‘gnd’ net1[3]   a = gnd;   R4     net1[4]   // Each ‘b’ port on each resistor is R5   // tied to the corresponding bit in the net1[5]   // ‘net1’ wire   R6   // The ‘combine’ keyword means to gather up   net1[6]   // all the single-bit ‘b’ pins into a bus R7   net1[7]   // to match up with the bits of the // net1 bus.   R8   combine(b) = net1;   net1[8]  }   gnd 39
  40. 40. Wiring Up Ports and Nets (2)net gnd, vcc;  net[1:8] net1, net2;    inst(1:8) res of Resistor {     R1   net1[7]   // Half of the ‘a’ ports tied to ‘gnd’   this(1:4).a = gnd;   R2   net2[2]     // Other half of the ‘a’ ports tied to ‘vcc’   R3   net1[5]   this(5:8).a = vcc;   R4     net2[3]   // Half of the ‘b’ ports tied to net1   R5   // Matching: 1-7, 3-5, 5-3, 7-1   net1[3]   combine(this(1,3,5,7).b) =net1[7,5,3,1];   R6     net2[4]   // Other half tied to net2   R7   net1[1]   // Matching: 8-1, 2-2, 4-3, 6-4   combine(this(8,2,4,6).b) = net2[1:4]   R8   net2[1]  }    // In all cases, indexing is viewed left-to-right   gnd vcc 40
  41. 41. Wiring Up Ports and Nets (3) R1   n1  net n1, n2, x1, x2;     R2  inst(1:8) res of Resistor {   x2     R3   x1   // Create bus made up of arbitrary collection // of nets R4   n2   // and wire to 4 of the ‘b’ ports.   // This is called a ‘concatenation’.   R5   combine(this(1:4).b) = n1 & x2 & x1 & n2;   R6  }   R7   R8   41
  42. 42. PHDL Packages (1)package myParts {     •  Declare devices to be in device Resistor {   attr REFPREFIX = “R”;   a package …   }    }     •  Must use package namedesign sevenSeg {   when instantiating.   inst(1:8) rArray of myParts.Resistor {   …  }   }   •  Allows same device in multiple device library files without name collision. 42
  43. 43. PHDL Packages (2)package myParts {     •  Declare devices to be in a device Resistor {   package attr REFPREFIX = “R”;   …   }   •  Import the package   contents.}    import myParts.*;   •  Avoids having to usedesign sevenSeg {     qualified names. inst(1:8) rArray of Resistor {   …   }   •  Compiler will flag using   unqualified device name}   instance where two imports could satisfy it. 43
  44. 44. PHDL Subdesigns (1)subdesign rc {   design myCircuit {   port gnd, in, out;   net i, o, gnd, vcc;       subinst rc1 of rc {   inst res of Resistor {   in = i; a = in; out = o;   b = out;   gnd = gnd;   }   }       inst cap of Capacitor {   inst P1 of Connector {   pos = out; p[0:2] = i & gnd & o;   p[3] = open;   neg = gnd; }   } }}     Subdesigns have port definitions. in Subdesigns can be instanced like out a device but with ‘subinst’ keyword. rc1   gnd P1   Subdesigns can be array instanced open just like devices. 44
  45. 45. PHDL Subdesigns (2) design myCircuit {   net i, o, gnd, vcc;  subdesign rc {     port gnd, in, out;   subinst rc1 of rc {     in = i; inst res of Resistor {   out = o;   a = in; gnd = gnd;   b = out; res.VALUE = ”66”;   }   }       inst cap of Capacitor {   inst P1 of Connector {   pos = out; p[0:2] = i & gnd & o;   neg = gnd;   p[3] = open;   }   }  }   }   in You can reach down into hierarchy out using “.” notation to change lower rc1   gnd P1   level attributes. open No limit to levels deep you can go. 45
  46. 46. PHDL Subdesigns (3) design myCircuit {   net[0:1] i, o;  subdesign rc {   net gnd, vcc;   port gnd, in, out;     subinst(0:1) rc1 of rc { inst res of Resistor {   combine(in) = i;   a = in; combine(out) = o;   b = out; }   gnd = gnd;     inst cap of Capacitor {   this(0).res.VALUE = ”66”;   pos = out; this(1).res.VALUE = ”100”;   neg = gnd; }   }   inst P1 of Connector {  }   p[0:2] = i[0] & gnd & o[1];   p[3] = open;   }   }   With array of subdesigns, use the in “this” and “combine” notation to wire out them up and change lower level rc1   gnd P1   attributes… rc1   open 46
  47. 47. 2.1Part 4A REAL PHDL BOARD:FPGA-BASED MOTOR CONTROL 47
  48. 48. BYU Proof of Concept BoardFPGA-based motor controller (2-axes) –  Spartan3 400K 144-pin QFP implements: •  32-bit position, vel. and accel. registers per axis •  Programmable PID filters, sampling intervals •  Trapezoidal velocity profile generators •  Packet router over RS232 to host PC application –  Supporting hardware •  500+ CPR encoder feedback resolution •  PWM brushless and brushed motor drives •  The usual JTAG, Flash ROM, GPIO, etc. 48
  49. 49. Motor Controller Board Final  Layout   Design Entry: ~1200 lines of PHDL 30 device decls 672 nets 49
  50. 50. Motor Controller Board Back From Manufacturing 50
  51. 51. Motor Controller Board Assembled Top Bottom
  52. 52. Motor Controller Board JTAGPower Supply 12VDC IN: Motor Power To 5V, 3.3V, 58VDC MAX 2.5V, 1.2V BrushlessFPGA / SRAM Drive (x2) RS232 Brushed Drive (x2) Encoder Feedback
  53. 53. 2.1Part 5SOURCE CODE CONTROLSYSTEMS (SCCS) 53
  54. 54. Motivation•  SCCS provides a remote repository –  Collaborate between users –  Saves all design versions •  Document every design change •  Compare versions –  Tag release file sets•  CVS and SVN are commonly used –  Command line versions for Linux –  GUI programs for Windows (ex: Tortoise) 54
  55. 55. The Old Binary File Way•  PowerSupp.sch•  PowerSupp_new.sch Each is a different version of the design.•  PowerSupp_newer.sch No enforced naming or•  PowerSupp_june15.sch numbering system.•  PowerSupp_v1.3 User must keep track of them.•  What changed between two versions? % diff a.sch b.sch
 Binary files a.sch and b.sch differ
 %" Not very helpful… How do we know what really changed? 55
  56. 56. The SCCS Way (CVS)"% cvs diff"cvs diff: Diffing ."Index: a.phdl"============================================="RCS file: /fpga2/cvsroot/users/nelson/test/a.phdl,v"retrieving revision 1.2"diff -r1.2 a.phdl" This shows that31c31" line 31 has changed.< "attr FOOTPRINT = "1V60R-5";" Comparison between local copy and---" most recent archived> "attr FOOTPRINT = "1V60R";" version (v1.2). Can compare any two" arbitrarily chosen versions. 56
  57. 57. The SCCS Way (Eclipse IDE) This shows that line 31 has changed. Comparison between local copy and archived version 7674. 57
  58. 58. 2.1Part 6THE ECLIPSE PLUG-IN FORPHDL 58
  59. 59. Eclipse PHDL Plug-In An outlineThe files in my project of the structure of the projectThe file being editedSyntax coloring helpsunderstand structure andfind simple errors (ex: no closingquote on a string) 59
  60. 60. Real-Time Syntax Checking (1)Error mark shows up instantlyMouse hover gives popup error message 60
  61. 61. Real-Time Syntax Checking (2)When possible, IDE proposes“Quick Fixes”. 61
  62. 62. Content Assist (1) Key click brings up context-specific content suggestions 62
  63. 63. Content Assist (2) Template has been inserted. Tab between fields to fill it in. In body of subinstance, will suggest what you can do based on what has been defined thus far in the project and insert template if selected. 63
  64. 64. Content Interrogation Hovering over a named element will give its definition ALT-clicking it will take you to that definition, even if in another file 64
  65. 65. Integration with SCCS (SVN) Project navigator screen shows which files are out of date with repository. Clicking takes you to repository synchronization screen 65
  66. 66. SVN Synchronize Screen Click icons to check files into repositoryList of files thathave been modifiedDouble click a fileto bring up side-by-side comparisonwindow 66
  67. 67. 2.1Part 73RD PARTY TOOLS 67
  68. 68. Example: FPGA Pin Generation (csv2phdl) FPGA VHDL Synthesis, PAR, PHDL Device Declaration Design csv2phdllibrary ieee; device fpga isuse ieee.numeric_std.all; attr REFPREFIX = "U";use ieee.std_logic_1164.all; attr FOOTPRINT = "tq144";entity fpga is attr LIBRARY = ”XILINX"; port( attr mfgr = "XILINX"; clk : in std_logic; rst : in std_logic; attr partNumber = "xc3s400-4tq144"; -- RS232 serial ports // User I/O pins. rxd : in std_logic; pin clk = {P52}; txd : out std_logic; pin rst = {P40}; rxd_a : in std_logic; pin rxd = {P47}; #fpga.ucf txd_a : out std_logic; pin rxd_a = {P41}; LOC “clk” = P52; pin txd = {P46}; -- 12-bit DAC pin txd_a = {P44}; LOC “rst” = P40: sclk : out std_logic; pin sclk = {P86}; LOC “rxd” = P47; sync : out std_logic; LOC “rxd_a” = P41; pin sdata = {P87}; sdata : out std_logic . pin sync = {P85}; . pin[7:0] data = {P23,P21,P20,P18...}; data : out . .std_logic_vector(7 downto 0) . . . Location . . end; ); Constraintsend entity fpga; Thanks to Pete Dudley… 68
  69. 69. Example: Automatic Device Generation (DeviceGen) •  Eagle device files are in XML format –  3rd party Java GUI program –  Easily browse, select, convert to PHDL Name of Eagle libraryBrowsable list of devicesand packages in libraryList of selected devices Click to generateand packages for PHDL PHDL devicedevice generation declarations 69 Thanks to Richard Black…
  70. 70. 2.1Part 8PHDL IS OPEN SOURCEAND AVAILABLE 70
  71. 71. phdl.sourceforge.net 71
  72. 72. phdl.sourceforge.net 72
  73. 73. Acknowledgements•  Sandia National Laboratories –  Supported the work –  Provided technical direction and management –  Chuck Graham and Wes Landaker•  Pete Dudley –  Formerly of Sandia, now of hdlguy.com, an FPGA & PCB board design consultancy –  Proposed the PHDL concept –  Authored the csv2phdl tool 73
  74. 74. 2.1Part 8FUTURE WORK 74
  75. 75. Future Tasks•  Library integration•  Hierarchical refdes generation –  Provide natural grouping mechanism•  Connectivity ERC•  Design visualization tools –  Hierarchy browsing –  Cross-probing –  Graphical viewing 75
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