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Power electronics

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Power Electronics full both lecture and notes of IIT Professors (NPTEL).

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  • 1. Module 1Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1
  • 2. Lesson 1Power Electronics Version 2 EE IIT, Kharagpur 2
  • 3. IntroductionThis lesson provides the reader the following: (i) Create an awareness of the general nature of Power electronic equipment; (ii) Brief idea about topics of study involved, (iii) The key features of the principal Power Electronic Devices; (iv) An idea about which device to choose for a particular application. (v) A few issues like base drive and protection of PE devices and equipment common to most varieties.Power Electronics is the art of converting electrical energy from one form to another in anefficient, clean, compact, and robust manner for convenient utilisation.A passenger lift in a modern building equipped with a Variable-Voltage-Variable-Speedinduction-machine drive offers a comfortable ride and stops exactly at the floor level. Behind thescene it consumes less power with reduced stresses on the motor and corruption of the utilitymains. Fig. 1.1 The block diagram of a typical Power Electronic converterPower Electronics involves the study of• Power semiconductor devices - their physics, characteristics, drive requirements and their protection for optimum utilisation of their capacities,• Power converter topologies involving them,• Control strategies of the converters,• Digital, analogue and microelectronics involved,• Capacitive and magnetic energy storage elements,• Rotating and static electrical devices,• Quality of waveforms generated,• Electro Magnetic and Radio Frequency Interference, Version 2 EE IIT, Kharagpur 3
  • 4. • Thermal ManagementThe typical converter in Fig. 1.1 illustrates the multidisciplinary nature of this subject.How is Power electronics distinct from linear electronics? It is not primarily in their power handling capacities. While power management ICs in mobile sets working on Power Electronic principles aremeant to handle only a few milliwatts, large linear audio amplifiers are rated at a few thousandwatts. The utilisation of the Bipolar junction transistor, Fig. 1.2 in the two types of amplifiers bestsymbolises the difference. In Power Electronics all devices are operated in the switching mode -either FULLY-ON or FULLY-OFF states. The linear amplifier concentrates on fidelity insignal amplification, requiring transistors to operate strictly in the linear (active) zone, Fig 1.3.Saturation and cutoff zones in the VCE - IC plane are avoided. In a Power electronic switchingamplifier, only those areas in the VCE - IC plane which have been skirted above, are suitable. On-state dissipation is minimum if the device is in saturation (or quasi-saturation for optimisingother losses). In the off-state also, losses are minimum if the BJT is reverse biased. A BJT switchwill try to traverse the active zone as fast as possible to minimise switching losses. Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage) amplifier stage and (b) switching (power) amplifier Version 2 EE IIT, Kharagpur 4
  • 5. Fig 1.3 Operating zones for operating a Bipolar Junction Transistor as a linear and a switching amplifier Linear operation Switching operationActive zone selected: Active zone avoided :Good linearity between input/output High losses, encountered only during transientsSaturation & cut-off zones avoided: poor Saturation & cut-off (negative bias) zoneslinearity selected: low lossesTransistor biased to operate around No concept of quiescent pointquiescent pointCommon emitter, Common collector, Transistor driven directly at base - emittercommon base modes and load either on collector or emitterOutput transistor barely protected Switching-Aid-Network (SAN) and other protection to main transistorUtilisation of transistor rating of secondary Utilisation of transistor rating optimisedimportance Version 2 EE IIT, Kharagpur 5
  • 6. An example illustrating the linear and switching solutions to a power supply specification willemphasise the difference. Spec: Input : 230 V, 50 Hz, Output: 12 V regulated DC, 20 W Ferrite core HF transfr: Light, efficient Series regulator - high losses 230 V 230 V Line freq transformer: (a) (b) heavy, lossy High-freq Duty-ratio (ON/OFF) control - low losses Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification above The linear solution, Fig. 1.4 (a), to this quite common specification would first step down thesupply voltage to 12-0-12 V through a power frequency transformer. The output would berectified using Power frequency diodes, electrolytic capacitor filter and then series regulatedusing a chip or a audio power transistor. The tantalum capacitor filter would follow. The balanceof the voltage between the output of the rectifier and the output drops across the regulator devicewhich also carries the full load current. The power loss is therefore considerable. Also, the step-down iron-core transformer is both heavy, and lossy. However, only twice-line-frequency ripplesappear at the output and material cost and technical know-how required is low. In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the linevoltage is rectified and then isolated, stepped-down and regulated. A ferrite-core high-frequency(HF) transformer is used. Losses are negligible compared to the first solution and the converter isextremely light. However significant high frequency (related to the switching frequency) noiseappear at the output which can only be minimised through the use of costly grass capacitors.Power Semiconductor device - history Power electronics and converters utilizing them made a head start when the first device theSilicon Controlled Rectifier was proposed by Bell Labs and commercially produced by GeneralElectric in the earlier fifties. The Mercury Arc Rectifiers were well in use by that time and therobust and compact SCR first started replacing it in the rectifiers and cycloconverters. Thenecessity arose of extending the application of the SCR beyond the line-commutated mode ofaction, which called for external measures to circumvent its turn-off incapability via its controlterminals. Various turn-off schemes were proposed and their classification was suggested but itbecame increasingly obvious that a device with turn-off capability was desirable, which wouldpermit it a wider application. The turn-off networks and aids were impractical at higher powers. The Bipolar transistor, which had by the sixties been developed to handle a few tens ofamperes and block a few hundred volts, arrived as the first competitor to the SCR. It is superiorto the SCR in its turn-off capability, which could be exercised via its control terminals. Thispermitted the replacement of the SCR in all forced-commutated inverters and choppers.However, the gain (power) of the SCR is a few decades superior to that of the Bipolar transistor Version 2 EE IIT, Kharagpur 6
  • 7. and the high base currents required to switch the Bipolar spawned the Darlington. Three or morestage Darlingtons are available as a single chip complete with accessories for its convenientdrive. Higher operating frequencies were obtainable with a discrete Bipolars compared to thefast inverter-grade SCRs permitting reduction of filter components. But the Darlingtonsoperating frequency had to be reduced to permit a sequential turn-off of the drivers and the maintransistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use. The Power MOSFET burst into the scene commercially near the end seventies. This devicealso represents the first successful marriage between modern integrated circuit and discretepower semiconductor manufacturing technologies. Its voltage drive capability – giving it again ahigher gain, the ease of its paralleling and most importantly the much higher operatingfrequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub-10 KW rangemainly for SMPS type of applications. Extension of VLSI manufacturing facilities for theMOSFET reduced its price vis-à-vis the Bipolar also. However, being a majority carrier deviceits on-state voltage is dictated by the RDS(ON) of the device, which in turn is proportional to aboutVDSS2.3 rating of the MOSFET. Consequently, high-voltage MOSFETS are not commerciallyviable. Improvements were being tried out on the SCR regarding its turn-off capability mostly byreducing the turn-on gain. Different versions of the Gate-turn-off device, the Gate turn-offThyristor (GTO), were proposed by various manufacturers - each advocating their own symbolfor the device. The requirement for an extremely high turn-off control current via the gate andthe comparatively higher cost of the device restricted its application only to inverters rated abovea few hundred KVA. The lookout for a more efficient, cheap, fast and robust turn-off-able device proceeded indifferent directions with MOS drives for both the basic thysistor and the Bipolar. The InsulatedGate Bipolar Transistor (IGBT) – basically a MOSFET driven Bipolar from its terminalcharacteristics has been a successful proposition with devices being made available at about 4KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive sawit totally removing the Bipolar from practically all applications. Industrially, only the MOSFEThas been able to continue in the sub – 10 KVA range primarily because of its high switchingfrequency. The IGBT has also pushed up the GTO to applications above 2-5 MVA. Subsequent developments in converter topologies – especially the three-level inverterpermitted use of the IGBT in converters of 5 MVA range. However at ratings above that theGTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR basedconverters are possible at the highest range where line-commutated or load-commutatedconverters were the only solution. The surge current, the peak repetition voltage and I2t ratingsare applicable only to the thyristors making them more robust, specially thermally, than thetransistors of all varieties. 1200V Version 3 ASIPMPresently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed bysome manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A Version 2 EE IIT, Kharagpur 7
  • 8. IEGT (injection-enhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (IntegratedGate Commutated Thyristors) of ABB which are promising at the higher power ranges.However these new devices must prove themselves before they are accepted by the industry atlarge. Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about2 eV that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbideis the only wide band gap semiconductor among gallium nitride (GaN, EG = 3.4 eV), aluminumnitride (AlN, EG = 6.2 eV), and silicon carbide that possesses a high-quality native oxide suitablefor use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 timeshigher than in silicon. This is important for high-voltage power switching transistors. Forexample, a device of a given size in SiC will have a blocking voltage 8 times higher than thesame device in silicon. More importantly, the on-resistance of the SiC device will be about twodecades lower than the silicon device. Consequently, the efficiency of the power converter ishigher. In addition, SiC-based semiconductor switches can operate at high temperatures(~600 C) without much change in their electrical properties. Thus the converter has a higherreliability. Reduced losses and allowable higher operating temperatures result in smaller heatsinksize. Moreover, the high frequency operating capability of SiC converters lowers the filteringrequirement and the filter size. As a result, they are compact, light, reliable, and efficient andhave a high power density. These qualities satisfy the requirements of power converters for mostapplications and they are expected to be the devices of the future. Ratings have been progressively increasing for all devices while the newer devices offersubstantially better performance. With the SCR and the pin-diodes, so called because of thesandwiched intrinsic ‘i’-layer between the ‘p’ and ‘n’ layers, having mostly line-commutatedconverter applications, emphasis was mostly on their static characteristics - forward and reversevoltage blocking, current carrying and over-current ratings, on-state forward voltage etc and alsoon issues like paralleling and series operation of the devices. As the operating speeds of thedevices increased, the dynamic (switching) characteristics of the devices assumed greaterimportance as most of the dissipation was during these transients. Attention turned to thedevelopment of efficient drive networks and protection techniques which were found to enhancethe performance of the devices and their peak power handling capacities. Issues related toparalleling were resolved by the system designer within the device itself like in MOSFETS,while the converter topology was required to take care of their series operation as in multi-levelconverters. The range of power devices thus developed over the last few decades can be represented as atree, Fig. 1.5, on the basis of their controllability and other dominant features. Version 2 EE IIT, Kharagpur 8
  • 9. POWER SEMICONDUCTOR DEVICES UNCONTROLLED CONTROLLED RECTIFIERS ACCESSORIES REGENERATIVE NON-REGENERATIVE INTEGRATED POWER SILICON SCR BJT IGCT DIAC TRIAC MOSFET PIC DIODES Zenner GTO IGBT INTELLIGENT FREDS MOV POWER MODULES SCHOTTKY Fig. 1.5 Power semiconductor device varietyPower Diodes diF /dt t0 t1 t2 SNAPPY SOFT Q1 Q2 Δ to IRM VRM Fig. 1.6 Typical turn-off dynamics of a soft and a snappy diode Silicon Power diodes are the successors of Selenium rectifiers having significantly improvedforward characteristics and voltage ratings. They are classified mainly by their turn-off(dynamic) characteristics Fig. 1.6. The minority carriers in the diodes require finite time - trr(reverse recovery time) to recombine with opposite charges and neutralise. Large values of Qrr (=Q1 + Q2) - the charge to be dissipated as a negative current when the and diode turns off and trr(= t2 - t0) - the time it takes to regain its blocking features, impose strong current stresses on thecontrolled device in series. Also a snappy type of recovery of the diode effects high di/dtvoltages on all associated power device in the converter because of load or stray inductancespresent in the network. There are broadly three types of diodes used in Power electronicapplications:Line-frequency diodes: These PIN diodes with general-purpose rectifier type applications, areavailable at the highest voltage (~5kV) and current ratings (~5kA) and have excellent over-current (surge rating about six times average current rating) and surge-voltage withstandcapability. They have relatively large Qrr and trr specifications. Version 2 EE IIT, Kharagpur 9
  • 10. Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FREDs,have significantly lower Qrr and trr (~ 1.0 sec). They are available at high powers and aremainly used in association with fast controlled-devices as free-wheeling or DC-DC choppers andrectifier applications. Fast recovery diodes also find application in induction heating, UPS andtraction.Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without anyQrr.. However, they are available with voltage ratings up to a hundred volts only though currentratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedomfrom minority carrier recovery permits reduced snubber requirements. Schottky diodes face nocompetition in low voltage SPMS applications and in instrumentation.Silicon Controlled Rectifier (SCR) The Silicon Controlled Rectifier is the most popular of the thyristor family of four layerregenerative devices. It is normally turned on by the application of a gate pulse when a forwardbias voltage is present at the main terminals. However, being regenerative or latching, it cannotbe turned off via the gate terminals specially at the extremely high amplification factor of thegate. There are two main types of SCRs. Converter grade or Phase Control thyristors These devices are the work horses of thePower Electronics. They are turned off by natural (line) commutation and are reverse biased atleast for a few milliseconds subsequent to a conduction period. No fast switching feature isdesired of these devices. They are available at voltage ratings in excess of 5 KV starting fromabout 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission arebuilt with series-parallel combination of these devices. Conduction voltages are device voltagerating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices areunsuitable for any forced-commutated circuit requiring unwieldy large commutationcomponents. The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the yearsborrowing emitter shorting and other techniques adopted for the faster variety. The requirementfor hard gate drives and di/dt limting inductors have been eliminated in the process. Inverter grade thyristors: Turn-off times of these thyristors range from about 5 to 50 μsecswhen hard switched. They are thus called fast or inverter grade SCRs. The SCRs are mainlyused in circuits that are operated on DC supplies and no alternating voltage is available to turnthem off. Commutation networks have to be added to the basic converter only to turn-off theSCRs. The efficiency, size and weight of these networks are directly related to the turn-off time,tq of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quitea few commutation networks were designed and some like the McMurray-Bedford becamewidely accepted. Asymmetrical, light-activated, reverse conducting SCRs Quite a few varieties of thebasic SCR have been proposed for specific applications. The Asymmetrical thyristor isconvenient when reactive powers are involved and the light activated SCR assists in parallelingor series operation. Version 2 EE IIT, Kharagpur 10
  • 11. MOSFET The Power MOSFET technology has mostly reached maturity and is the most popular devicefor SMPS, lighting ballast type of application where high switching frequencies are desired butoperating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour)with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising sharedmanufacturing processes, comparative costs of MOSFETs are attractive. For low frequencyapplications, where the currents drawn by the equivalent capacitances across its terminals aresmall, it can also be driven directly by integrated circuits. These capacitances are the mainhindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics ofits main terminals permit easy paralleling externally also. At high current low voltageapplications the MOSFET offers best conduction voltage specifications as the RDS(ON)specification is current rating dependent. However, the inferior features of the inherent anti-parallel diode and its higher conduction losses at power frequencies and voltage levels restrict itswider application.The IGBT It is a voltage controlled four-layer device with the advantages of the MOSFET driverand the Bipolar Main terminal. IGBTs can be classified as punch-through (PT) and non-punch-through (NPT) structures. In the punch-through IGBT, a better trade-off between the forwardvoltage drop and turn-off time can be achieved. Punch-through IGBTs are available up to about1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are morerobust than PT IGBTs particularly under short circuit conditions. However they have a higherforward voltage drop than the PT IGBTs. Its switching times can be controlled by suitablyshaping the drive signal. This gives the IGBT a number of advantages: it does not requireprotective circuits, it can be connected in parallel without difficulty, and series connection ispossible without dv/dt snubbers. The IGBT is presently one of the most popular device in viewof its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square SafeOperating Area devoid of a Second Breakdown region.The GTOThe GTO is a power switching device that can be turned on by a short pulse of gate current andturned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anodecurrent to be turned off. Hence there is no need for an external commutation circuit to turn it off.Because turn-off is provided by bypassing carriers directly to the gate circuit, its turn-off time isshort, thus giving it more capability for highfrequency operation than thyristors. The GTOsymbol and turn-off characteristics are shown in Fig. 30.3. GTOs have the I2t withstandcapability and hence can be protected by semiconductor fuses. For reliable operation of GTOs,the critical aspects are proper design of the gate turn-off circuit and the snubber circuit.Power Converter TopologiesA Power Electronic Converter processes the available form to another having a differentfrequency and/or voltage magnitude. There can be four basic types of converters depending uponthe function performed: Version 2 EE IIT, Kharagpur 11
  • 12. CONVERSION FROM/TO NAME FUNCTION SYMBOL DC to DC Chopper Constant to variable DC or variable to constant DC DC to AC Inverter DC to AC of desired voltage and frequency ~ AC to DC Rectifier AC to unipolar (DC) current ~ Cycloconverter, AC to AC AC-PAC, AC of desired frequency and/or ~ Matrix converter magnitude from generally line AC ~Base / gate drive circuitAll discrete controlled devices, regenerative or otherwise have three terminals. Two of these arethe Main Terminals. One of the Main Terminals and the third form the Control Terminal. Theamplification factor of all the devices (barring the now practically obsolete BJT) are quite high,though turn-on gain is not equal to turn-off gain. The drive circuit is required to satisfy thecontrol terminal characteristics to efficiently tun-on each of the devices of the converter, turnthem off, if possible, again optimally and also to protect the device against faults, mostly over-currents. Being driven by a common controller, the drives must also be isolated from each otheras the potentials of the Main Terminal which doubles as a Control terminal are different atvarious locations of the converter. Gate-turn-off-able devices require precise gate drivewaveform for optimal switching. This necessitates a wave-shaping amplifier. This amplifier islocated after the isolation stage. Thus separate isolated power supplies are also required for each Power device in theconverter (the ones having a common Control Terminal - say the Emitter in an IGBT - mayrequire a few less). There are functionally two types of isolators: the pulse transformer whichcan transmit after isolation, in a multi-device converter, both the un-shaped signal and power andoptical isolators which transmit only the signal. The former is sufficient for a SCR withoutisolated power supplies at the secondary. The latter is a must for practically all other devices.Fig. 1.7 illustrates to typical drive circuits for an IGBT and an SCR. Version 2 EE IIT, Kharagpur 12
  • 13. IGBT Vref COMPARATOR TIMER Fig. 1.7 Simple gate-drive and protection circuit for a stand-alone IGBT and a SCRProtection of Power devices and converters Power electronic converters often operate from the utility mains and are exposed to thedisturbances associated with it. Even otherwise, the transients associated with switching circuitsand faults that occur at the load point stress converters and devices. Consequently, severalprotection schemes must be incorporated in a converter. It is necessary to protect both the MainTerminals and the control terminals. Some of these techniques are common for all devices andconverters. However, differences in essential features of devices call for special protectionschemes particular for those devices. The IGBT must be protected against latching, and similarlythe GTOs turn-off drive is to be disabled if the Anode current exceeds the maximum permissibleturn-off-able current specification. Power semiconductor devices are commonly protectedagainst: 1. Over-current; 2. di/dt; 3. Voltage spike or over-voltage; 4. dv/dt ; 5. Gate-under voltage; 6. Over voltage at gate; 7. Excessive temperature rise; 8. Electro-static discharge; Semiconductor devices of all types exhibit similar responses to most of the stresses, howeverthere are marked differences. The SCR is the most robust device on practically all counts. That ithas an I2t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitablyselected, and in co-ordination with fast circuit breakers would mostly protect it. This sometimesbecomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJTand the IGBT is actively protected (without any operating cost!) by sensing the Main Terminalvoltage, as shown in Fig. 1.7. This voltage is related to the current carried by the device. Further,the transistors permit designed gate current waveforms to minimise voltage spikes as aconsequence of sharply rising Main terminal currents. Gate resistances have significant effect onturn-on and turn-off times of these devices - permitting optimisation of switching times for thereduction of switching losses and voltage spikes. Version 2 EE IIT, Kharagpur 13
  • 14. Protection schemes for over-voltages - the prolonged ones and those of short duration - areguided by the energy content of the surges. Metal Oxide Varistors (MOVs), capacitive dynamicvoltage-clamps and crow-bar circuits are some of the strategies commonly used. For high dv/dtstresses, which again have similar effect on all devices, R-C or R-C-D clamps are useddepending on the speed of the device. These snubbers or switching-aid-networks, additionallyminimise switching losses of the device - thus reducing its temperature rise. Gates of all devices are required to be protected against over-voltages (typically + 20 V)specially for the voltage driven ones. This is achieved with the help of Zener clamps - the zenerbeing also a very fast-acting device. Protection against issues like excessive case temperatures and ESD follow well-set practices.Forced-cooling techniques are very important for the higher rated converters and wholeenvironments are air-cooled to lower the ambient.Objective type questionsQs#1 Which is the Power semiconductor device having a) Highest switching speed; b) Highest voltage / current ratings; c) Easy drive features; d) Can be most effectively paralleled; e) Can be protected against over-currents with a fuse; f) Gate-turn off capability with regenerative features; g) Easy drive and High power handling capabilityAns: a) MOSFET; b) SCR; c) MOSFET; d) MOSFET; e) SCR ; (f) GTO; (g) IGBTQs#2 An SCR requires 50 mA gate current to switch it on. It has a resistive load and is suppliedfrom a 100 V DC supply. Specify the Pulse transformer details and the circuit following it, if thedriver circuit supply voltage is 10 V and the gate-cathode drop is about 1 V.Ans: The most important ratings of the Pulse transformer are its volt-secs rating, the isolationvoltage and the turns ratio.The volt-secs is decided by the product of the primary pulse-voltage multiplied by the period forwhich the pulse is applied to the windingIf the primary pulse voltage = (Supply voltage – drive transistor drop)The turn-on time of he SCR may be in the range 50 μsecs for an SCR of this rating.Consequently the volt secs may be in the range of 9 x 50 = 450 μvolt-secsThe Pulse transformer may be chosen as: 1:1, 450 μVs, Visol = 2.5 KV, IM = 150 mAThe circuit shown in Fig. 1.7 may be used. Diodes 1N4002Series resistance= (Supply voltage – drive transistor drop – gate-cathode drop)/100mA= (10 –1 –1) / 100 E-3= 80 Ohm= 49 or 57 Ohm (nearest available lower value) Version 2 EE IIT, Kharagpur 14
  • 15. Module 1Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1
  • 16. Lesson 2Constructional Features, Operating Principle, Characteristics and Specification of Power Semiconductor Diode Version 2 EE IIT, Kharagpur 2
  • 17. Instructional ObjectiveOn Completion the student will be able to 1. Draw the spatial distribution of charge density, electric field and electric potential in a step junction p-n diode. 2. Calculate the voltage drop across a forward biased diode for a given forward current and vice-verse. 3. Identify the constructional features that distinguish a power diode from a signal level diode. 4. Differentiate between different reverse voltage ratings found in a Power Diode speciation sheet. 5. Identify the difference between the forward characteristic of a power diode and a signal level diode and explain it. 6. Evaluate the forward current specifications of a diode for a given application. 7. Draw the “Turn On” and “Turn Off” characteristics of a power diode. 8. Define “Forward recovery voltage”, “Reverse recovery current” “Reverse Recovery charge” as applicable to a power diode. Version 2 EE IIT, Kharagpur 3
  • 18. Power Semiconductor Diodes2.1 IntroductionPower semiconductor diode is the “power level” counter part of the “low power signal diodes”with which most of us have some degree of familiarity. These power devices, however, arerequired to carry up to several KA of current under forward bias condition and block up toseveral KV under reverse biased condition. These extreme requirements call for importantstructural changes in a power diode which significantly affect their operating characteristics.These structural modifications are generic in the sense that the same basic modifications areapplied to all other low power semiconductor devices (all of which have one or more p-njunctions) to scale up their power capabilities. It is, therefore, important to understand the natureand implication of these modifications in relation to the simplest of the power devices, i.e., apower semiconductor diode.2.2 Review of Basic p-n Diode CharacteristicsA p-n junction diode is formed by placing p and n type semiconductor materials in intimatecontact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n typesilicon crystal or by the opposite sequence.In an open circuit p-n junction diode, majority carriers from either side will defuse across thejunction to the opposite side where they are in minority. These diffusing carriers will leavebehind a region of ionized atoms at the immediate vicinity of the metallurgical junction. Thisregion of immobile ionized atoms is called the space charge region. This process continues tillthe resultant electric field (created by the space charge density) and the potential barrier at thejunction builds up to sufficient level to prevent any further migration of carriers. At this point thep-n junction is said to be in thermal equilibrium condition. Variation of the space charge density,the electric field and the potential along the device is shown in Fig 2.1 (a). Version 2 EE IIT, Kharagpur 4
  • 19. (a) (b) (c)Fig 2.1: Space change density the electric field and the electric potential in side a p-n junction under (a) thermal equilibrium condition, (b) reverse biased condition, (c) forward biased condition.When an external voltage is applied with p side move negative then the n side the junction issaid to be under reverse bias condition. This reverse bias adds to the height of the potentialbarrier. The electric field strength at the junction and the width of the space change region (alsocalled “the depletion region” because of the absence of free carriers) also increases. On the otherhand, free minority carrier densities (np in the p side and pn in the n side) will be zero at the edgeof the depletion region on either side (Fig 2.1 (b)). This gradient in minority carrier densitycauses a small flux of minority carriers to defuse towards the deletion layer where they are sweptimmediately by the large electric field into the electrical neutral region of the opposite side. Thiswill constitute a small leakage current across the junction from the n side to the p side. Therewill also be a contribution to the leakage current by the electron hole pairs generated in the spacechange layer by the thermal ionization process. These two components of current together iscalled the “reverse saturation current Is” of the diode. Value of Is is independent of the reversevoltage magnitude (up to a certain level) but extremely sensitive to temperature variation.When the applied reverse voltage exceeds some threshold value (for a given diode) the reversecurrent increases rapidly. The diode is said to have undergone “reverse break down”.Reverse break down is caused by "impact ionization" as explained below. Electrons acceleratedby the large depletion layer electric field due to the applied reverse voltage may attain sufficientknick energy to liberate another electron from the covalent bonds when it strikes a silicon atom.The liberated electron in turn may repeat the process. This cascading effect (avalanche) mayproduce a large number of free electrons very quickly resulting in a large reverse current. Thepower dissipated in the device increases manifold and may cause its destruction. Therefore,operation of a diode in the reverse breakdown region must be avoided. Version 2 EE IIT, Kharagpur 5
  • 20. When the diode is forward biased (i.e., p side more positive than n side) the potential barrier islowered and a very large number of minority carriers are injected to both sides of the junction.The injected minority carriers eventually recombines with the majority carries as they defusefurther into the electrically neutral drift region. The excess free carrier density in both p and nside follows exponential decay characteristics. The characteristic decay length is called the"minority carrier diffusion length"Carrier density gradients on either side of the junction are supported by a forward current IF(flowing from p side to n side) which can be expressed as IF = IS ( exp ( qv/kT ) ) -1 (2.1)Where Is = Reverse saturation current ( Amps) v = Applied forward voltage across the device (volts) q = Change of an electron k = Boltzman’s constant T = Temperature in KelvinFrom the foregoing discussion the i-v characteristics of a p-n junction diode can be drawn asshown in Fig 2.2. While drawing this characteristics the ohmic drop in the bulk of thesemiconductor body has been neglected. Fig 2.2: Volt-Ampere ( i-v ) characteristics of a p-n junction diodeExercise 2.1(1) Fill in the blanks with the appropriate word(s). (i) The width of the space charge region increases as the applied ______________ voltage increases. (ii) The maximum electric field strength at the center of the depletion layer increases with _______________ in the reverse voltage. (iii) Reverse saturation current in a power diode is extremely sensitive to ___________ variation. Version 2 EE IIT, Kharagpur 6
  • 21. (iv) Donor atoms are _____________________ carrier providers in the p type and _________________ carrier providers in the n type semiconductor materials. (v) Forward current density in a diode is __________________________ proportional to the life time of carriers.Answer: (i) Reverse, (ii) increase, (iii) temperature, (iv) Minority Majority, (v) inversely(2) A p-n junction diode has a reverse saturation current rating of 50 nA at 32°C. Whatshould be the value of the forward current for a forward voltage drop of 0.5V. Assume VT =KT/q at 32°C = 26 mv.Answer ⎛ V ⎞ I F = I s ⎜ e VT - 1 ⎟ , Is = 5×10-8 A, VT = 26×10-3 V V = 0.5V ⎝ ⎠∴ I F = 11.24 Am ps. di(3) For the diode of Problem-2 calculate the dynamic ac resistance ra c = F d v F at 32°C and aforward voltage drop of 0.5V.Answer: ⎛ VF VT ⎞ diF Is VF iF = Is ⎜ e -1⎟ ∴ = e VT ⎝ ⎠ dVF VT N ow I s = 5 × 10 -8 A , V F = 0.5V , -3 VT = 26 ×10 V at 32o C V dVF V - F ∴ = ra c = T e V T = 2 .3 1 3 m Ω diF Is2.3 Construction and Characteristics of Power DiodesAs mention in the introduction Power Diodes of largest power rating are required to conductseveral kilo amps of current in the forward direction with very little power loss while blockingseveral kilo volts in the reverse direction. Large blocking voltage requires wide depletion layer inorder to restrict the maximum electric field strength below the “impact ionization” level. Spacecharge density in the depletion layer should also be low in order to yield a wide depletion layerfor a given maximum Electric fields strength. These two requirements will be satisfied in alightly doped p-n junction diode of sufficient width to accommodate the required depletion layer.Such a construction, however, will result in a device with high resistively in the forwarddirection. Consequently, the power loss at the required rated current will be unacceptably high.On the other hand if forward resistance (and hence power loss) is reduced by increasing thedoping level, reverse break down voltage will reduce. This apparent contradiction in therequirements of a power diode is resolved by introducing a lightly doped “drift layer” of required Version 2 EE IIT, Kharagpur 7
  • 22. thickness between two heavily doped p and n layers as shown in Fig 2.3(c). Fig 2.3 (a) and (b)shows the circuit symbol and the photograph of a typical power diode respectively. (b)Fig. 2.3: Diagram of a power; (a) circuit symbol (b) photograph; (c) schematic cross section.To arrive at the structure shown in Fig 2.3 (c) a lightly doped n- epitaxial layer of specified width(depending on the required break down voltage) and donor atom density (NdD) is grown on aheavily doped n+ substrate (NdK donor atoms.Cm -3) which acts as the cathode. Finally the p-njunction is formed by defusing a heavily doped (NaA acceptor atoms.Cm-3) p+ region into theepitaxial layer. This p type region acts as the anode.Impurity atom densities in the heavily doped cathode (Ndk .Cm -3) and anode (NaA.Cm -3) areapproximately of the same order of magnitude (10 19 Cm -3) while that of the epitaxial layer (alsocalled the drift region) is lower by several orders of magnitude (NdD ≈ 10 14 Cm-3). In a lowpower diode this drift region is absent. The Implication of introducing this drift region in a powerdiode is explained next.2.3.1 Power Diode under Reverse Bias Conditions BackAs in the case of a low power diode the applied reverse voltage is supported by the depletionlayer formed at the p+ n- metallurgical junction. Overall neutrality of the space change regiondictates that the number of ionized atoms in the p+ region should be same as that in the n- region.However, since NdD << NaA, the space charge region almost exclusively extends into the n- drift Version 2 EE IIT, Kharagpur 8
  • 23. region. Now the physical width of the drift region (WD) can be either larger or smaller than thedepletion layer width at the break down voltage. Consequently two type of diodes exist, (i) nonpunch through type, (ii) punch through type. In “non-punch through” diodes the depletion layerboundary doesn’t reach the end of the drift layer. On the other hand in “punch through” diodesthe depletion layer spans the entire drift region and is in contact with the n+ cathode. However,due to very large doping density of the cathode, penetration of drift region inside cathode isnegligible. Electric field strength inside the drift region of both these type of diodes at breakdown voltage is shown in Fig 2.4.Fig 2.4: Electric field strength in reverse biased power Diodes; (a) Non-punch through type; (b) punch through type.In non-punch through type diodes the electric field strength is maximum at the p+ n- junction anddecrease to zero at the end of the depletion region. Where as, in the punch through constructionthe field strength is more uniform. In fact, by choosing a very lightly doped n- drift region,Electric field strength in this region can be mode almost constant. Under the assumption ofuniform electric field strength it can be shown that for the same break down voltage, the “punchthrough” construction will require approximately half the drift region width of a comparable “non - punch through” construction.Lower drift region doping in a “punch through” diode does not carry the penalty of higherconduction lasses due to “conductivity modulation” to be discussed shortly. In fact, reducedwidth of the drift region in these diodes lowers the on-state voltage drop for the same forwardcurrent density compared to a non-punch through diode.Under reverse bias condition only a small leakage current (less than 100mA for a rated forwardcurrent in excess of 1000A) flows in the reverse direction (i.e from cathode to anode). Thisreverse current is independent of the applied reverse voltage but highly sensitive to junctiontemperature variation. When the applied reverse voltage reaches the break down voltage, reversecurrent increases very rapidly due to impact ionization and consequent avalanche multiplicationprocess. Voltage across the device dose not increase any further while the reverse current islimited by the external circuit. Excessive power loss and consequent increase in the junctiontemperature due to continued operation in the reverse brake down region quickly destroies thediode. Therefore, continued operation in the reverse break down region should be avoided. Atypical I-V characteristic of a power diode under reverse bias condition is shown in Fig 2.5. Version 2 EE IIT, Kharagpur 9
  • 24. Fig 2.5: Reverse bias i-v characteristics of a power Diode.A few other important specifications of a power Diode under reverse bias condition usuallyfound in manufacturer’s data sheet are explained below.DC Blocking Voltage (VRDC): Maximum direct voltage that can be applied in the reversedirection (i.e cathode positive with respect to anode) across the device for indefinite period oftime. It is useful for selecting free-wheeling diodes in DC-DC Choppers and DC-AC voltagesource inverter circuits.RMS Reverse Voltage (VRMS): It is the RMS value of the power frequency (50/60 HZ) sincewave voltage that can be directly applied across the device. Useful for selecting diodes forcontrolled / uncontrolled power frequency line commutated AC to DC rectifiers. It is given bythe manufacturer under the assumption that the supply voltage may rise by 10% at the most. Thisrating is different for resistive and capacitive loads.Peak Repetitive Reverse Voltage (VRRM): This is the maximum permissible value of theinstantiations reverse voltage appearing periodically across the device. The time period betweentwo consecutive appearances is assumed to be equal to half the power cycle (i.e 10ms for 50 HZsupply). This type of period reverse voltage may appear due to “commutation” in a converter.Peak Non-Repetitive Reverse Voltage (VRSM): It is the maximum allowable value of theinstantaneous reverse voltage across the device that must not recur. Such transient reversevoltage can be generated by power line switching (i.e circuit Breaker opening / closing) orlightning surges.Fig. 2.6 shows the relationship among these different reverse voltage specifications. Version 2 EE IIT, Kharagpur 10
  • 25. Fig. 2.6: Reverse Voltage ratings of a power diode; (a) Supply voltage wave form; (b) Reverse i-v characteristics2.3.2 Power Diode under Forward Bias ConditionIn the previous section it was shown how the introduction of a lightly doped drift region in the p-n structure of a diode boosts its blocking voltage capacity. It may appear that this lightly dopeddrift region will offer high resistance during forward conduction. However, the effectiveresistance of this region in the ON state is much less than the apparent ohmic resistancecalculated on the basis of the geometric size and the thermal equilibrium carrier densities. This isdue to substantial injection of excess carriers from both the p+ and the n+ regions in the driftregion as explained next.As the metallurgical p+ n- junction becomes forward biased there will be injection of excess ptype carrier into the n- side. At low level of injections (i.e δp << nno) all excess p type carriersrecombine with n type carriers in the n- drift region. However at high level of injection (i.e largeforward current density) the excess p type carrier density distribution reaches the n- n+ junctionand attracts electron from the n+ cathode. This leads to electron injection into the drift regionacross the n- n+ junction with carrier densities δn = δp. This mechanism is called “doubleinjection”Excess p and n type carriers defuse and recombine inside the drift region. If the width of the driftregion is less than the diffusion length of carries the spatial distribution of excess carrier densityin the drift region will be fairly flat and several orders of magnitude higher than the thermalequilibrium carrier density of this region. Conductivity of the drift region will be greatlyenhanced as a consequence (also called conductivity modulation).The voltage dropt across a forward conducting power diode has two components i.e Vak = Vj + VRD (2.2)Where Vj is the drop across the p+n- junction and can be calculated from equation (2.1) for agiven forward current jF. The component VRD is due to ohmic drop mostly in the drift region.Detailed calculation shows VRD ∞ JF WD (2.3)Where JF is the forword current density in the diode and WD is the width of the drift region.Therefore Vak = Vj + RON IF (2.3)The ohmic drop makes the forward i-v characteristic of a power diode more linear. Version 2 EE IIT, Kharagpur 11
  • 26. Fig 2.7: Characteristics of a forward biased power Diode; (a) Excess free carrier density distribution; (b) i-v characteristics.Both Vj and VAK have negative temperature coefficient as shown in the figure.Few other important specifications related to forward bias operation of power diode as found inmanufacturer’s data sheet are explained next.Maximum RMS Forward current (IFRMS): Due to predominantly resistive nature of theforward voltage drop across a forward biased power diode, RMS value of the forward currentdetermines the conduction power loss. The specification gives the maximum allowable RMSvalue of the forward current of a given wave shape (usually a half cycle sine wave of powerfrequency) and at a specified case temperature. However, this specification can be used as aguideline for almost all wave shapes of the forward current.Maximum Average Forward Current (IFAVM): Diodes are often used in rectifier circuitssupplying a DC (average) current to be load. In such cases the average load current and the diodeforward current usually have a simple relationship. Therefore, it will be of interest to know the Version 2 EE IIT, Kharagpur 12
  • 27. maximum average current a diode can conduct in the forward direction. This specification givesthe maximum average value of power frequency half cycle sine wave current allowed to flowthrough the diode in the forward direction. Average current rating of a diode decreases withreduction in conduction angle due to increase in current “form factor”.Both IFRMS and IFAVM ratings are given at a specified case temperature. If the case temperatureincreases beyond this limit these ratings has to be reduced correspondingly. “Derating curves”provide by the manufacturers give the relationship between IFAVM (IFRMS) with allowable casetemperature as shown in Fig. 2.8. Fig 2.8: Derating curves for the forward current of a Power Diode.Average Forward Power loss (PAVF): Almost all power loss in a diode occurs during forwardconduction state. The forward power loss is therefore an important parameter in designing thecooling arrangement. Average forward power loss over a full cycle is specified by themanufacturers as a function of the average forward current (IAVF) for different conduction anglesas shown in Fig 2.9. Fig 2.9: Average forward power loss vs. average forward current of a power Diode. Version 2 EE IIT, Kharagpur 13
  • 28. Surge and Fault Current: In some rectifier applications a diode may be required to conductforward currents far in excess of its RMS or average forward current rating for some duration(several cycles of the power frequency). This is called the repetitive surge forward current of adiode. A diode is expected to operate normally after the surge duration is over.On the other hand, fault current arising due to some abnormality in the power circuit may have ahigher peak valve but exists for shorter duration (usually less than an half cycle of the powerfrequency). A diode circuit is expected to be disconnected from the power line following a fault.Therefore, a fault current is a non repetitive surge current. Power diodes are capable ofwithstanding both types of surge currents and this capability is expressed in terms of two surgecurrent ratings as discussed next.Peak Repetitive surge current rating (IFRM): This is the peak valve of the repetitive surgecurrent that can be allowed to flow through the diode for a specific duration and for specifiedconditions before and after the surge. The surge current waveform is assumed to be halfsinusoidal of power frequency with current pulses separated by “OFF” periods of equal duration.The case temperature is usually specified at its maximum allowable valve before the surge. Thediode should be capable of withstanding maximum repetitive peak reverse voltage (VRRM) andMaximum allowable average forward current (IFAVM) following the surge. The surge currentspecification is usually given as a function of the surge duration in number of cycles of thepower frequency as shown in figure 2.10 Fig 2.10: Peak Repetitive surge current VS time curve of a power diode.In case the surge current is specified only for a fixed number of cycles ‘m’then the surge current specification applicable to some other cycle number ‘n’ can be found fromthe approximate formula. m I FRM n = I (2.4) n FRM mPeak Non-Repetitive surge current (IFRM): This specification is similar to the previous oneexcept that the current pulse duration is assumed to be within one half cycle of the power Version 2 EE IIT, Kharagpur 14
  • 29. frequency. This specification is given as a function of the current pulse duration as shown in Fig2.11.Maximum surge current Integral (∫i2dt): This is a surge current related specification and givesa measure of the heat energy generated inside the device during a non-repetitive surge. It isuseful for selecting the protective fuse to be connected in series with the diode. This specificationis also given as a function of the current pulse duration as shown Fig 2.11Fig. 2.11: Non-repetitive surge current and surge current integral vs. current pulse width characteristics of a power Diode.Exercise 2.2 (1) Fill in the blanks with the appropriate word(s). i. The ____________ region in a power diode increases its reverse voltage blocking capacity. ii. The maximum DC voltage rating (VRDC) of a power diode is useful for selecting ________________ diodes in a DC-DC chopper. iii. The reverse breakdown voltage of a Power Diode must be greater than ________________ . iv. The i-v characteristics of a power diode for large forward current is __________ . v. The average current rating of a power diode _______________ with reduction in the conduction angle due to increase in the current ___________________ . vi. The derating curves of a Power diode provides relationship between the ______________ and the _________________ . ∫ i dt rating of a power diode is useful for selecting the ________________ . 2vii.Answer: (i) drift, (ii) free wheeling, (iii) VRSM, (iv) linear, (v) decrease, form factor, (vi)IFAVM/IFRM, case temperature, (vii) protective fuse. Version 2 EE IIT, Kharagpur 15
  • 30. (2). (a) For the single phase half wove rectifier shown find out the VRRM rating of D. (b) Will the required VRRM rating change if a inductor is placed between the diode and n capacitor. (c) What will be the required VRRM rating if the capacitor is removed. Assume a resistive load. (d) The source of the single phase rectifier circuit has an internal resistance of 2 Ω. Find out the required Non repetitive peak surge current rating of the diode. Also find the i2t rating of the protective fuse to be connected in series with the diode.Answer: (a) During every positive half cycle of the supply the capacitor charges to the peakvalue of the supply voltage. If the load disconnected the capacitor voltage will not change whenthe supply goes through its negative peak as shown in the associated waveform. Therefore thediode will be subjected to a reverse voltage equal to the peak to peak supply voltage in eachcycle. Hence, the required VRRM rating will be VRRM = 2 × 2 × 230V = 650V(b) When an inductor is connected between the diode and the capacitor the inductor currentwill have some positive value at t = t1. If the load is disconnected the stored energy in theinductor will charge the capacitor beyond the peak supply voltage. Since there is no dischargepath for the capacitor this voltage across the capacitor will be maintained when the supplyvoltage goes through negative peak. Therefore, the diode will be subjected to a reverse voltagegreater than the peak to peak supply voltage. The required VRRM rating will increase. Version 2 EE IIT, Kharagpur 16
  • 31. (c) If the capacitor is removed and the load is resistive the voltage VKN during negative halfcycle of the supply will be zero since the load current will be zero. Therefore the reverse voltageacross the diode will be equal to the peak supply voltage. So the required VRRM rating will be VRRM = 2 × 230V = 325 Volts(d) Peak surge current will flow through the circuit when the load is accidentally short circuited.The peak surge current rating will be 2 × 230 I FSM = A = 162.64 A 2 The peak non repetitive surge current should not recur. Therefore, the protective fuse (tobe connected in series with the diode) must blow during the negative half cycle following thefault. Therefore the maximum i2t rating of the fuse is π ∫i 2 dt = ∫ I 2 F S M S in 2 w td w t = π I 2 F S m = 4 1 .5 5 × 1 0 3 A 2 s e c M ax o 22.3.3 Switching Characteristics of Power DiodesPower Diodes take finite time to make transition from reverse bias to forward bias condition(switch ON) and vice versa (switch OFF).Behavior of the diode current and voltage during these switching periods are important due to thefollowing reasons. • Severe over voltage / over current may be caused by a diode switching at different points in the circuit using the diode. • Voltage and current exist simultaneously during switching operation of a diode. Therefore, every switching of the diode is associated with some energy loss. At high switching frequency this may contribute significantly to the overall power loss in the diode.Observed Turn ON behavior of a power Diode: Diodes are often used in circuits with di/dtlimiting inductors. The rate of rise of the forward current through the diode during Turn ON hassignificant effect on the forward voltage drop characteristics. A typical turn on transient is shownin Fig. 2.12. Version 2 EE IIT, Kharagpur 17
  • 32. Fig. 2.12: Forward current and voltage waveforms of a power diode during Turn On operation.It is observed that the forward diode voltage during turn ON may transiently reach a significantlyhigher value Vfr compared to the steady slate voltage drop at the steady current IF.In some power converter circuits (e.g voltage source inverter) where a free wheeling diode isused across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may behigh enough to destroy the main power switch.Vfr (called forward recovery voltage) is given as a function of the forward di/dt in themanufacturer’s data sheet. Typical values lie within the range of 10-30V. Forward recovery time(tfr) is typically within 10 us.Observed Turn OFF behavior of a Power Diode: Figure 2.13 shows a typical turn offbehavior of a power diode assuming controlled rate of decrease of the forward current. Version 2 EE IIT, Kharagpur 18
  • 33. Fig. 2.13: Reverse Recovery characteristics of a power diodeSalient features of this characteristics are: • The diode current does not stop at zero, instead it grows in the negative direction to Irr called “peak reverse recovery current” which can be comparable to IF. In many power electronic circuits (e.g. choppers, inverters) this reverse current flows through the main power switch in addition to the load current. Therefore, this reverse recovery current has to be accounted for while selecting the main switch. • Voltage drop across the diode does not change appreciably from its steady state value till the diode current reaches reverse recovery level. In many power electric circuits (choppers, inverters) this may create an effective short circuit across the supply, current being limited only by the stray wiring inductance. Also in high frequency switching circuits (e.g, SMPS) if the time period t4 is comparable to switching cycle qualitative modification to the circuit behavior is possible. • Towards the end of the reverse recovery period if the reverse current falls too sharply, (low value of S), stray circuit inductance may cause dangerous over voltage (Vrr) across the device. It may be required to protect the diode using an RC snubber.During the period t5 large current and voltage exist simultaneously in the device. At highswitching frequency this may result in considerable increase in the total power loss.Important parameters defining the turn off characteristics are, peak reverse recovery current (Irr),reverse recovery time (trr), reverse recovery charge (Qrr) and the snappiness factor S.Of these parameters, the snappiness factor S depends mainly on the construction of the diode(e.g. drift region width, doping lever, carrier life time etc.). Other parameters are interrelated andalso depend on S. Manufacturers usually specify these parameters as functions of diF/dt fordifferent values of IF. Both Irr and Qrr increases with IF and diF/dt while trr increases with IF anddecreases with diF/dt. Version 2 EE IIT, Kharagpur 19
  • 34. The reverse recovery characteristics shown in Fig. 2.13 is typical of a particular type of diodescalled “normal recovery” or “soft recovery” diode (S>1). The total recovery time (trr) in this caseis a few tens of microseconds. While this is acceptable for line frequency rectifiers (these diodesare also called rectifier grade diodes) high frequency circuits (e.g PWM inverters, SMPS)demand faster diode recovery. Diode reverse recovery time can be reduce by increasing the rateof decrease of the forward current (i.e, by reducing stray circuit inductance) and by using“snappy” recovery (S<<1) diode. The problems with this approach are: i) Increase of diF/dt also increases the magnitude of Irr ii) Large recovery current coupled with ”snappy” recovery may give rise to current and voltage oscillation in the diode due to the resonant circuit formed by the stray circuit inductance and the diode depletion layer capacitance. A typical recovery characteristics of a “snappy” recovery diode is shown in Fig 2.14 (a).Fig. 2.14: Diode overvoltage protection circuit; (a) “Snappy recovery characteristics; (b) Capacitive snubber circuit; (c) snubber characteristics.Large reverse recovery current may lead to reverse voltage peak (Vrr) in excess of VRSM anddestroy the device. A capacitive protection circuit (also called a “snubber circuit) as shown inFig. 2.14 (b) may to used to restrict Vrr. Here the current flowing through Ll at the time of diodecurrent “snapping” is bypassed to Cs. Ll,Rs & Cs forms a damped resonance circuit and the initialenergy stored in Ll is partially dissipated in Rs, thereby, restricting Vrr . Normalized values of Vrras a function of the damping factor ξ with normalized Irr as a parameter is shown in Fig. 2.14(c).However, it is difficult to correctly estimate the value of Ll and hence design a proper snubbercircuit. Also snubber circuits increase the overall power loss in the circuit since the energy storedin the snubber capacitor is dissipated in the snubber resistance during turning ON of the diode.Therefore, in high frequency circuits other types of fast recovery diodes (Inverter grade) arepreferred. Fast recovery diodes offer significant reduction in both Irr and trr (10% - 20% of arectifier grade diode of comparable rating). This improvement in turn OFF performance,however, comes at the expense of the steady state performance. It can be shown that the forwardvoltage drop in a diode is directly proportion to the width of the drift region and inverselyproportional to the carrier life time in the drift region. On the other hand both Irr and trr increaseswith increase in carrier life time and drift region width. Therefore if Irr and trr are reduced byreducing the carrier life time, forward voltage drop increases. On the other hand, if the drift Version 2 EE IIT, Kharagpur 20
  • 35. region width is reduced the reverse break down voltage of the diode reduces. The performance ofa fast recovery diode is therefore, a compromise between the steady state performance and theswitching performance. In high voltage high frequency circuits switching loss is the dominantcomponent of the overall power loss. Therefore, some increase in the forward voltage drop in thediode (and hence conduction power lass) can be tolerated since the Turn OFF loss associatedwith reverse recovery is greatly reduced.In some very high frequency applications (fsw >100KHZ), improvement in the reverse recoveryperformance offered by normal fast recovery diode is not sufficient. If the required reverseblocking voltage is less (<100v) schottky diodes are preferred over fast recovery diodes.Compared to p-n junction diodes schottky diodes have very little Turn OFF transient and almostno Turn ON transient. On state voltage drop is also less compared to a p-n junction diode forequal forward current densities. However, reverse breakdown voltage of these diodes are less(below 200V) Power schottky diodes with forward current rating in excess of 100A areavailable.Exerciser 2.3 1. Fill in the blanks with appropriate word(s) i. Forward recovery voltage appears due to higher ohmic drop in the ______________ region of a power diode in the beginning of the Turn On process. ii. The magnitude of the forward recovery voltage is typically of the order of few ______________ of volts. iii. The magnitude of the forward recovery voltage also depends on the _______________ of the diode forward current. iv. The reverse recovery charge of a power diode increases with the _______________ of the diode forward current. v. For a given forward current the reverse recovery current of a Power Diode ______________ with the rate of decrease of the forward current. vi. For a given forward current the reverse recovery time of a Power diode ______________ with the rate of decrease of the forward current. vii. A “snappy” recovery diode is subjected to _________________ voltage over shoot on recovery.viii. A fast recovery diode has _______________________ reverse recovery current and time compared to a __________________ recovery diode. ix. A Schottky diode has _______________ forward voltage drop and ______________ reverse voltage blocking capacity. x. Schottky diodes have no __________________ transient and very little _________________ transient.Answer: (i) drift, (ii) tens, (iii) rate of rise, (iv) magnitude, (v) increases, (vi) decreases, (vii) large, (viii) lower, (ix) low, law, (x) Turn On, Turn Off. 2. In the buck converter shown the diode D has a lead inductance of 0.2μH and a reverse recovery change of 10μC at iF =10A. Find peak current through Q. Version 2 EE IIT, Kharagpur 21
  • 36. Answer: Assuming iL=10A (constant) the above waveforms can be drawnAs soon as Q is turned ON. a reverse voltage is applied across D and its lead inductance. diF 20 ∴ = A S ec = 10 7 A S ec dt .2 × 1 0 -6Assuming a snappy recovery diode (s ≈ o) 1 ⎛ diF ⎞ 2 Q rr = 1 I rr t rr = ⎜ ⎟ t rr 2 2 ⎝ dt ⎠ = 1 0 × 1 0 -6 C∴ t rr = 1 . 4 1 4 μ s diF∴ I rr = t rr = 1 4 . 1 4 A dt∴i =I +I = 24.14 A Q peak L rr Version 2 EE IIT, Kharagpur 22
  • 37. References 1. Ned Mohan, Tore M. Undeland, William P. Robbins, “Power Electronics, Converters, Application and Design” John Wiley & Sons(Asia), Publishers. Third Edition 2003. 2. P. C. Sen, “Power Electronics” Tata McGraw Hill Publishing Company Limited, New Delhi, 1987. 3. Jacob Millman, Christos C. Halkias, “Integrated Electronics, Analog and Digital Circuits and Systems”, Tata McGraw-Hill Publishing Company Limited, New Delhi, 1991. Version 2 EE IIT, Kharagpur 23
  • 38. Module Summary • A p-n junction diode is a minority carrier, unidirectional, uncontrolled switching device. • A power diode incorporates a lightly doped drift region between two heavily doped p type and n type regions. • Maximum reverse voltage withstanding capability of a power diode depends on the width and the doping level of the drift region. • A power diode should never be subjected to a reverse voltage greater than the reverse break down voltage. • The i-v characteristics of a forward biased power diode is comparatively more linear due to the voltage drop in the drift region. • The forward voltage drop across a conducting power diode depends on the width of the drift region but not affected significantly by its doping density. • For continuous forward biased operation the RMS value of the diode forward current should always be less than its rated RMS current at a given case temperature. • Surge forward current through a diode should be less than the applicable surge current rating. • During “Turn On” the instantaneous forward voltage drop across a diode may reach a level considerably higher than its steady state voltage drop for the given forward current. This is called forward recovery voltage. • During “Turn Off” the diode current goes negative first before reducing to zero. This is called reverse recovery of a diode. • The peak negative current flowing through a diode during Turn Off is called the “reverse recovery current” of the diode. • The total time for which the diode current remains negative during Turn Off is called “the reverse recovery time” of the diode. • A diode can not block reverse voltage till the reverse current through the diode reaches its peak value. • Both the “reverse recovery current” and the “reverse recovery time” of a diode depends on the forward current during Turn Off, rate of decrease of the forward current and the type of the diode. • Normal or slow recovery diodes have smaller reverse recovery current but longer reverse recovery time. They are suitable for line frequency rectifier operation. • Fast recovery diodes have faster switching times but comparatively lower break down voltages. They are suitable for high frequency rectifier or inverter free- wheeling operation. • Fast recovery diodes need to be protected against voltage transients during Turn Off” using R-C snubber circuit. Version 2 EE IIT, Kharagpur 24
  • 39. • Schottky diodes have lower forward voltage drop and faster switching times but comparatively lower break down voltage. They are suitable for low voltage very high frequency switching power supply applications. Version 2 EE IIT, Kharagpur 25
  • 40. Practice Problems and Answers Version 2 EE IIT, Kharagpur 26
  • 41. Practice Problems (Module-2) 1. If a number of p-n junction diodes with identical i-v characteristics are connected in parallel will they share current equally? Justify your answer. 2. A power diode have a reverse saturation current of 15μA at 32°C which doubles for every 10° rise in temperature. The dc resistance of the diode is 2.5 mΩ. Find the forward voltage drop and power loss for a forward current of 200 Amps. Assume that the maximum junction temperature is restricted to 102°C. VT = k T = 26 m v at 32 o C q 3. In the voltage commutated chopper T & TA are turned ON alternately at 400 HZ. C is initially charged to 200 V with polarity as shown. Find the IFRMS and VRRM ratings of DI & DF. 4. In the voltage commutated chopper of Problem 5 the voltage on C reduces by 1% due to reverse recovery of DI. Find out Irr & trr for DI. (Assume S = 1 for DI). 5. What precaution must be taken regarding the forward recovery voltage of the free wheeling diodes in a PWM voltage source inverter employing Bipolar Junction Transistors of the n-p-n type? Version 2 EE IIT, Kharagpur 27
  • 42. Answers to Practice Problems1. The reverse saturation current of a p-n junction diode increases rapidly with temperature. If follows then (from Eqn. 2.1) the voltage drop across a diode for a given forward current decreases with increase in temperature. In other words if the volt ampere characteristics of a diode is modeled as a non linear (current dependent) resistant it will have a negative temperature coefficient. Let us now consider the situation where a number of diodes are connected in parallel. If due to some transient disturbance the current in a diode increases momentarily the junction temperature of that diode will increase due increased power dissipation. The voltage drop across that particular diode will decrease as a result and more current will be diverted towards that diode. This “positive feedback mechanism” will continue to increase its current share till parasitic lead resistance drop becomes large enough to prevent farther voltage drop across that diode. Therefore, it can be concluded that a number of p-n junction diodes conned in parallel will not, in general, share current equally even if it is assumed that they have identical i-v characteristics. However, equal current sharing can be forced by connecting suitable resistances in series with the diodes so that the total resistance of each branch has positive temperature coefficient.2. Since the reverse saturation current double with every 10°C rise in junction temperature. 1 0 2 -3 2 Is 102o C = 2 10 × Is 32o C = 1 .9 2 m A KT Vt = = 26mv at 32 o C ∴ Vt at 102 o = 31.97mv q ∴ V j fo r i F = 2 0 0 A is iF V j = Vt o 102 C × ln = 0 .3 7 V Is 102o C Voltage drop across drift region VR = iF ×RD = 0.5V Therefore, the total voltage drop across the diode is VD = VR + V j = 0.87V Version 2 EE IIT, Kharagpur 28
  • 43. 3. Important wave forms of the system are shown in the figure. As soon as T is turned ON the capacitor voltage starts reversing due to the L-C resenant circuit formed by C-T-L & DI. Neglecting all the capacitor voltage reaches a -200V. The current idi is given by i D I = I D IP S in ω n 0 ≤ ωn ≤ 7 w here I D IP = 200 C = 89.44 A L 1 & ωn = = 22.36×103 LC Version 2 EE IIT, Kharagpur 29
  • 44. ∴ Capacitor voltage reversal time Tn 1 π = = = = 140μs. 2 2 fn ωnCapacitor voltage remains at -200 V till TA is turned ON when it is charged linearly towards+200 V. Time taken for charging is 2 × 200 × C TC = = 400μs ILAt the end of charging DF turns ON and remains on till T is turned on again. I DIP 140 ∴ I FRMS For D I is = 10.58 Amps 2 5000 2100 I FRMS For D F is 20 = 12.96 Amps 5000 From figure VRRM for D I is 200 V VRRM for D F is 400 V 4. Since the Capacitor voltage reduces by 1% Q rr = 0.01× C × 200 = 40μc d i dI w ith S = 1 Q rr = I rr t rr = t rr 2 dt Now id I = I DIP Sin ω n t di dI ∴ = ω n I D IP C osω n t dt di dI 1 C at ω n t = π, = ω n I DIP = , 200 = 2A dt LC L μs ∴ t rr 2 = 20 ×10-12 sec 2 or t rr = 4.472 μs ∴ I rr = 8.94 Am ps5. Figure shows one leg of a PWM VSI using n-p-n transistor and freewheeling diode. Version 2 EE IIT, Kharagpur 30
  • 45. Consider turning off operation of Q1. As the current through Q1 reduces D1 turns On. Theforward recovery voltage of D1 appears as a reverse voltage across the n-p-n transistor whosebase emitter junction must with stand this reverse voltage. Therefore, the forward recoveryvoltage of the free wheel diodes must be less them the reverse break down voltage of the base-emitter junction of the n-p-n transistors for safe operation of the inverter. Version 2 EE IIT, Kharagpur 31
  • 46. Module 1Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1
  • 47. Lesson 3Power Bipolar Junction Transistor (BJT) Version 2 EE IIT, Kharagpur 2
  • 48. Constructional Features, Operating Principles, Characteristics and specifications of PowerBipolar Junction transistors.Objective: On completion the student will be able to 1. Distinguish between, cut off, active, and saturation region operation of a Bipolar Junction Transistor. 2. Draw the input and output characteristics of a junction transistor and explain their nature. 3. List the salient constructional features of a power BJT and explain their importance. 4. Draw the output characteristics of a Power BJT and explain the applicable operating limits under Forward and Reverse bias conditions. 5. Interpret manufacturer’s data sheet ratings for a Power BJT. 6. Differentiate between the characteristics of an ideal switch and a BJT. 7. Draw and explain the Turn On characteristics of a BJT. 8. Draw and explain the Turn Off characteristics of a BJT. 9. Calculate switching and conduction losses of a Power BJT. 10. Design a BJT base drive circuit. Version 2 EE IIT, Kharagpur 3
  • 49. 3.1 IntroductionPower Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full controlover its Turn on and Turn off operations. It simplified the design of a large number of PowerElectronic circuits that used forced commutated thyristors at that time and also helped realize anumber of new circuits. Subsequently, many other devices that can broadly be classified as“Transistors” have been developed. Many of them have superior performance compared to theBJT in some respects. They have, by now, almost completely replaced BJTs. However, it shouldbe emphasized that the BJT was the first semiconductor device to closely approximate an idealfully controlled Power switch. Other “transistors” have characteristics that are qualitativelysimilar to those of the BJT (although the physics of operation may differ). Hence, it will beworthwhile studying the characteristics and operation a BJT in some depth. From the point ofview of construction and operation BJT is a bipolar (i.e. minority carrier) current controlleddevice. It has been used at signal level power for a long time. However, the construction andoperating characteristics of a Power BJT differs significantly from its signal level counterpartdue to the requirement for a large blocking voltage in the “OFF” state and a high current carryingcapacity in the “ON” state. In this module, the construction, operating principle andcharacteristics of a Power BJT will be explored.3.2 Basic Operating Principle of a Bipolar Junction TransistorA junction transistor consists of a semiconductor crystal in which a p type region is sandwichedbetween two n type regions. This is called an n-p-n transistor. Alternatively an n type regionmay be placed in between two p type regions to give a p-n-p transistor. Fig 3.1 shows the circuitsymbols and schematic representations of an n-p-n and a p-n-p transistor. The terminals of atransistor are called Emitter (E), Base (B) & Collector (C) as shown in the figure. VCE VCE E (n) C (n) E (p) C (p) - iE VBE + i iC C iE VBE iB B (p) B (n) RC RC VBB RB VBB iB VCC VCC Version 2 EE IIT, Kharagpur 4
  • 50. (Emitter) (Base) (Collector) (Emitter) (Base) (Collector) n p n n p n (E) (B) (C) (E) (B) (C) S WBE 0 A φCB A φBE A 0 φCB S S φCB φ φBE S φBE φCB BE S x A φCB 0 φ 0 x WS CB S WBE φBE BE S φCB A WCB WCB A WBE A WBE 0 WCB 0 0 0 WCB WBE A WBE WCB JBE JCB JBE JCB nS pB pS nB pS pS nC nS nS pC nE pE n poB p noB pA nE p noE p noC nA pE n poE n poC A n A pB p nC p A nB nA pC x x (a) (b) Fig. 3.1: Bipolar junction transistor under different biasing condition. (a) n – p – n transistor ; (b) p – n – p transistor.If no external biasing voltages are applied (i.e.; VBB and VCC are open circuited) all transistorcurrents must be zero. The transistor will be in thermal equilibrium condition with potentialbarriers φο and φCB at the base emitter and the base collector functions respectively. ΒΕ o O OCorresponding depletion layer widths will be WBE and WCB . It is clear from the diagram that ptype carriers in the base region of an n-p-n transistor are trapped in a “potential well” and cannotescape. Similarly, in a p-n-p transistor p type carriers in the emitter and collector regions areseparated by a “potential hill”.When biasing voltages are applied as shown in the figure, the base emitter junction (JBE)becomes forward biased where as the base collector junction is reverse biased. Potential barrier Αand depletion layer width at JBE reduces to φΒΕ and WBE respectively. Both these quantities Aincrease at JCB ( φA , WCB ) . As the potential barrier at JBE is reduced a large number of minority CB Acarriers are introduced in to Base and the Emitter regions as shown in Fig. 3.1 ( PnE , n A for n-p-n A pB Version 2 EE IIT, Kharagpur 5
  • 51. transistor and n A , p A for p-n-p transistor). A portion of the minority carriers reaching the base pE nBrecombines with majority carriers. The rest, defuse to the edge of the depletion region at JCBwhere they are swept away to the collector region by the large electric field. Under this conditionthe transistor is said to be in the Active region.As VBE is increased injected minority charge into the base region increases and so does the basecurrent and the collector current. For a fixed collector bias voltage VCC, the voltage VCB reduceswith increase in collector current due to increasing drop in the external resistance RC. Therefore,the potential barrier at JCB starts reducing. At one point JCB becomes forward biased. Thepotential barriers and depletion layer widths under this condition are indicated in Fig. 3.1 byvariables with a super script “s”. Due to forward biasing of JCB there will be minority carrierinjection into the base from this junction also as shown in Fig. 3.1. The total voltage dropbetween collector and emitter will be the difference between the forward bias voltage drops atJBE and JCB. Under this condition the transistor is said to be in the saturation region.From the operating principle described above one can form a qualitative idea about the input (iB Bvs VBE) and output (iC Vs VCE) characteristics of a transistor. In the following section thesecharacteristics of an n-p-n transistor will be discussed qualitatively. Similar explanation appliesto a p-n-p transistor.When a biasing voltage VBB of appropriate polarity is applied across the junction JBE thepotential barrier at this junction reduces and at one point the junction becomes forward biased.The current crossing this junction is governed by the forward biased p-n junction equation fora given collector emitter voltage. The base current iB is related to the recombination of minority Bcarriers injected into the base from the emitter. The rate of recombination is directly proportionalto the amount of excess minority carrier stored in the base. Since, in a normal transistor theemitter is much more heavily doped compared to the base the current crossing JBE is almostentirely determined by the excess minority carrier distribution in the base. Thus, it can beconcluded that the relationship between iB and VBE will be similar to the i-v characteristics of a Bp-n junction diode. VCE, however have some effect on this characteristic. As VCE increasesreverse bias of JCB increases and the depletion region at JCB moves deeper into the base. Theeffective base width thus reduces, reducing the rate of recombination in the base region andhence the base current. Therefore iB for a given VBE reduces with increasing VCE as shown in BFig. 3.2(a).It has been mentioned before that only a fraction (denoted by the letter “∝”) of the total minoritycarriers injected into the base reaches junction JCB where they are swept in to the collector regionby the large electric field at JCB. These minority carriers constitute the major component of thetotal collector current. The other component of the collector current consists of the small reversesaturation current of the reverse biased junction JCB. Therefore IC = ∝IE + Ics (3.1) Where Ics is the reverse saturation current of junction JCB But IE = IB + IC B (3.2) Version 2 EE IIT, Kharagpur 6
  • 52. ICS ∝ ∴ IC = + IB 1- ∝ 1- ∝ (3.3) ∝ By defining β 1− ∝ IC = βIB + (β+1) Ics (3.4)β is called the large signal common emitter current gain of the transistor and remains fairlyconstant for a large range of IC, as shown in Fig. 3.2 (c). Fig: 3 (b) shows the complete out putcharacteristics (ic vs VCE) of an n-p-n transistor. With VBB = 0 or negative there is little injected minority carrier into the base from theemitter side. Therefore, iB = 0 and iC is negligibly small. The transistor is said to be in the “cut Boff” region under this condition. As VBB is increased from zero, base current starts flowing. From equation (3.4) it will beexpected that the collector current should increase proportionately independent of VCE. HoweverFig 3.2 (b) does indicate a slight increase in iC with VCE for a given iB. This is expected because Bwith increasing VCE a larger value of VBE will be required to maintain a given iB (Fig. 3.2 (a)). BTherefore, the component “∝IE” of collector current will increase. ICS is ,for all practicalpurpose, independent of VCE. This is the active or “amplifier mode” of operation of a transistor.In the active region as iB increases iC also increases. For a given value of VCC, VCE reduces with Bincreasing iC due to increased drop in an external load (i.e., Rc in Fig 3.1). At one point thejunction JCB becomes forward biased. VCE, now is just the difference between the voltages acrosstwo forward biased junction JBE and JCB (a few handed milli volts). This is when the transistorenters the saturation mode of operation. The ratio iC/iB at the onset of saturation is called βMin and Bis an important parameter for a power transistor. In saturation iC is almost entirely determined bythe external load and further increase in iB changes iC or VCE very little. Version 2 EE IIT, Kharagpur 7
  • 53. iC iB6 iB5 iB4 iB iB3 iB Saturation vCE Active increasing iB2 increasing iB1 iB = 0 vBE Cut off vCE (a) (b) β (c) Fig. 3.2: Input and output characteristics of an n – p – n transistor. (a) Input characteristics; (b) Output characteristics; (c) Current gain[β] characteristicsExercise 3.1Fill in the blank(s) with the appropriate word(s) a) Under forward bias condition a large number of ___________________ carriers are introduced in the base region. b) Some minority charge carriers reaching base __________________ with majority carriers there and the rest of them ___________________ to the collector. c) When the base-emitter junction of a BJT is forward biased while the base-collector junction is reverse biased the BJT is said to be in the _______________ region. d) When both B-E & C-B junction of a BJT are reverse biased it is said to be in the _________________ region. e) When both B-E & C-B junction of a BJT are forward biased it is said to be in the _______________ region. Version 2 EE IIT, Kharagpur 8
  • 54. Answer: (a) minority; (b) recombine, diffuse; (c) active; (d) cut-off; (e) saturation.Exercise 3.2Why does the collector current of a BJT in the active region increases with increasing collectorvoltage for a given base current.Answer: In the active region as the VCE voltage is increased the depletion layer width at the CB junction increases and the effective base width reduces. Therefore, for a given VBE recombination of minority carriers in the base region reduces and base current also reduces. In order to main constant base current with increasing VCE, VBE must increased. Therefore, for a constant base current the number of minority carriers in the base region will increase and consequently, collector current will increase.Exercise 3.3A power BJT has IC = 20 A at IB = 2.5 A. Ics = 15 mA. Find out β & ∝. BAnswer: Ic = β IB + (β + 1) Ics = β( IB + Ics) + Ics. B B ∴ β = 7.95,3.3 Constructional Features of a Power BJTPower transistors face the same conflicting design requirements (i.e. large off state blockingvoltage and large on state current density) as that of a power diode. Therefore, it is only naturalto extend some of the constructional features of power diodes to power BJT. Following Sectionsummarizes some of the constructional features of a Power BJT. Since Power Transistors arepredominantly of the n-p-n type, in this section and subsequently only this type of transistor willbe discussed. • A power BJT has a vertically oriented alternating layers of n type and p type semiconductor materials as shown in Fig 3.3(a). The vertical structure is preferred for power transistors because it maximizes the cross sectional area through which the on state current flows. Thus, on state resistance and power lass is minimized. • In order to maintain a large current gain “β” (and hence reduce base drive current) the emitter doping density is made several orders of magnitude higher than the base region. The thickness of the base region is also made as small as possible. • In order to block large voltage during “OFF” state a lightly doped “collector drift region” is introduced between the moderately doped base region and the heavily doped collector region. The function of this drift region is similar to that in a Power Diode. However, the doping density donation of the base region being “moderate” the depletion region does penetrate considerably into the base. Therefore, the width of the base region in a power transistor can not be made as small as that in a signal level transistor. This comparatively larger base width has adverse effect on the current gain (β) of a Power transistor which Version 2 EE IIT, Kharagpur 9
  • 55. typically varies within 5-20. As will be discusses later the collector drift region has significant effect on the out put characteristics of a Power BJT. • Practical Power transistors have their emitters and bases interleaved as narrow fingers. This is necessary to prevent “current crowding” and consequent “second break down”. In addition multiple emitter structure also reduces parasitic ohmic resistance in the base current path. These constructional features of a Power BJT are shown schematically in Fig 3.3(a). Fig.3.3 (b) shows the photograph of some community available Power transistors in different packages. Emitter contactBasecontact n+ (emitter) n+ n+ p (Base) n- (Collector Drift) n+ (Collector) (a) Collector contact Version 2 EE IIT, Kharagpur 10
  • 56. (b)Fig. 3.3: Constructional Features of a Power Bipolar Junction Transistor (a) Schematic of Construction, (b) Photograph of commercial packages.Exercise 3.4Fill in the blank(s) with the appropriate word(s) a) Doping density of the emitter of a Power BJT is several orders of magnitude ______________ than the base doping density. b) Collector drift region is introduced in a Power BJT to block _______________ voltage. c) Doping density of the base region in a power BJT is ________________. d) Power BJT has ________________ DC current gain compared to signal level transistors. e) In a Power BJT multiple, narrow finger like distributed emitter structure is used to avoid emitter ___________________.Answer: (a) higher; (b) high reverse; (c) moderate; (d) low; (e) current crowding.Exercise 3.5What are the constructional features of a power transistor that affect the dc current gain? • Large doping density of the emitter increases dc current gain. • Moderately doped base regain of relatively larger width tend to reduce the dc current gain. The base width in a power transistor cannot be reduced below a certain level in order to avoid “reach through” of the base region under large applied voltage. • Multiple, narrow emitter regions distributed uniformly over the entire device cross section also tends to improve dc current gain by minimizing “current crowding”.3.4 Output i-v characteristics of a Power Transistor A typical output (iC vs VCE) characteristics of an n-p-n type power transistor is shown inFig 3.4 A power transistor exhibits “Cut off”, “Active” and “Saturation regions” of operation inits output characteristics similar to a signal level transistor. In fact output characteristics of a Version 2 EE IIT, Kharagpur 11
  • 57. Power Transistor in the “Cut off” and “Active” regions are qualitatively identical to a signallevel transistor. Certain quantitative restrictions apply, however, which are discussed next. iC Hard Saturation Quasi Saturation iB10 Second break down limit iB9 iB8 iB7 Active iB6 Total Power dissipation limit iB5 iB4 iB3 iB2 Increasing iB Primary break down voltage iB1 iB ≤ 0 ϑCE Cut off VSUS VCE0 VCB0 (iB = 0) (iB < 0) Fig. 3.4 Output ( ic – vCE ) characteristics of an n – p – n type Power TransistorIn the cut off region (iB ≤ 0) the collector current is almost zero. The maximum voltage between Bcollector and emitter under this condition is termed “Maximum forward blocking voltage withbase terminal open (iB = 0)” and is denoted by VCEO. For all practical purpose this is the Bmaximum voltage that can be applied in the forward direction (C positive with respect to E)across a power transistor since a power transistor is expected to see any significant forwardvoltage only with iB = 0. This blocking voltage can however be increased to a value VCBO by Bkeeping the emitter terminal open. In this case iB < o. Actually VCBO is the breakdown voltage ofthe collector base junction. However, since the open base configuration is more common thevalue of VCEO is used by the manufacturers as the maximum voltage rating of a power transistor.Power transistors have poor reverse voltage withstanding capability due to low break downvoltage of the base-emitter junction. Therefore, reverse voltage (C negative with respect to E)should not appear across a power transistor.In the active region the ratio of collector current to base current (DC current Gain (β)) remainsfairly constant upto certain value of the collector current after which it falls off rapidly.Manufacturers usually provide a graph showing the variation of β as a function of the collectorcurrent for different junction temperatures and collector emitter voltages. This graph is useful fordesigning the base drive of a Power transistor. Typically, the value of the dc current gain of aPower transistor is much smaller compared to their signal level counterpart. Version 2 EE IIT, Kharagpur 12
  • 58. The maximum collector-emitter voltage that a power transistor can withstand in active region isdetermined by the Base collector avalanche break down voltage. This voltage, denoted by VSUSin Fig, 3.4 is usually smaller than VCEO. The voltage VSUS can be attained only for relativelylower values of collector current. At higher collector current the limit on the “total powerdissipation” defines the boundary of the allowable active region as shown in Fig 3.4.At still higher levels of collector currents the allowable active region is further restricted by apotential failure mode called “the Second Break down”. It appears on the output characteristicsof the BJT as a precipitous drop in the collector-emitter voltage at large collector currents. Thecollector voltage drop is often accompanied by significant rise in the collector current and asubstantial increase in the power dissipation. Most importantly this dissipation is not uniformlyspread over the entire volume of the device but is concentrated in highly localized regions. Thislocalized heating is a combined effect of the intrinsic non uniformity of the collector currentdensity distribution across the cross section of the device and the negative temperaturecoefficient of resistively of minority carrier devices which leads to the formation of “currentfilamements” (localized areas of very high current density) by a positive feed-back mechanism.Once current filaments are formed localized “thermal runaway” quickly takes the junctiontemperature beyond the safe limit and the device is destroyed.It is in the saturation region that the output characteristics of a Power transistor differssignificantly from its signal level counterpart. In fact the saturation region of a Power transistorcan be further subdivided into a quasi saturation region and a hard saturation region.Appearance of the quasi saturation region in the output characteristics of a power transistor is adirect consequence of introducing the drift region into the structure of a power transistor. In thequasi saturation region the base-collector junction is forward biased but the lightly doped driftregion is not completely shorted out by excess minority carrier injection from the base. Theresistivity of this region depends to some extent on the base current. Therefore, in the quasisaturation region, the base current still retains some control over the collector current althoughthe value of β decreases significantly. Also, since the resistivity of the drift region is stillsignificant the total voltage drop across the device in this mode of operation is higher for a givencollector current compared to what it will be in the hard saturation region.In the hard saturation region base current looses control over the collector current which isdetermined entirely by the collector load and the biasing voltage VCC. This behavior is similar towhat happens in a signal transistor except that the drift region of a power transistor continues tooffer a small resistance even when it is completely shorted out (by excess carrier injection fromthe base). Therefore, for larger collector currents the collector-emitter voltage drop is almostproportional to the collector current. Manufacturers usually provide the plots of the variation ofVCE (sat) vs. iC for different values of base current and junction temperature. Curves showingthe variation of VCE (sat) with iB for different values of iC and junction temperature are also Bprovided by certain manufacturers.Applicable operating limits on a power transistors are compactly represented in two diagramscalled the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe OperatingArea. (RBSOA) applicable to iB > 0 and iB ≤ 0 conditions respectively. Typical safe operating B Bareas of power transistors are shown in Fig 3.5. Version 2 EE IIT, Kharagpur 13
  • 59. iC iCICM ICM 10-5sec 10-4sec 10-3sec 10-2sec DC Log ϑCE ϑCE (a) VSUS (b) VCE0 VCB0 (VBE = 0) (VBE < 0) Fig. 3.5: Safe operating areas of a Power Transistor. (a) FBSOA; (b) RBSOA. The horizontal upper limit of the FBSOA is determined by the maximum allowable collector current (ICM) that should not be exceeded even as a pulse. Exceeding this current limit may cause bonding wire or metallization of the wafer to vaporize or otherwise fail. Since a power transistor does not have any appreciable reverse voltage blocking capacity they are usually not used in ac circuits. However, if the collector current, for some reason is not dc or a pulse, the rms value of the collector current waveform should not exceed this limit. The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the maximum allowable power dissipation and maximum junction temperature. Since FBSOA is shown on a log-log scale constant Power dissipation (Pd = VCE iC) limits appear as straight lines. This limit is different for dc and pulsed operation due to the thermal time constant of the device. The “DC” limit is applicable to the average power loss if the transistor remains continuously in the conduction state (active, quasi saturation or saturation). On the other hand the pulsed power dissipation limits are applicable to conduction duration up to the value marked on them (the figures on the right of Fig 3.5 (a)). Pulsed power dissipation limits are specified for a low value (1%-2%) of duty cycle and are useful for shaping the switching trajectory of the transistor as will be seen later. The third limit of the FBSOA (red line) arises due to the “second break down” failure mode of a Power transistor. It shows the limiting combinations of collector voltage and current so that second break down does not occur. On the log –log scale of the FBSOA this limit also appears as a straight limit. Like the maximum power dissipation limit, the second break down limit is also different for “DC” and “Pulsed” operation of different pulse durations. The interpretation of the pulse duration (marked on the right side of Fig 3.5 (a)) corresponding to a particular limit is also same. The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage (VSUS) of the transistor and appear as a vertical line in the FBSOA at VCE = VSuS Version 2 EE IIT, Kharagpur 14
  • 60. The FBSOA of a Power transistor is given at a specified case temperature. Both the maximumpower dissipation limit and the second break down limits are to be derated as per the deratingcharacteristics provided by the manufacturers when the case temperature exceeds the specifiedvalue.In contrast to the FBSOA, the RBSOA (Fig 3.5 (b)) is plotted on a linear scale and has a morerectangular shape. RBSOA is a switching SOA since a transistor can not conduct current for anyappreciable duration under reverse biased condition. It essentially shows the limiting permissiblecombinations of VCE & iC with base emitter junction reverse biased. The upper horizontal limitcorresponds to the maximum allowable collector current (ICM) and is same as that in the FBSOA.The right hand side vertical limit corresponds the avalanche break down voltage of the transistorwith reverse bias. If the base terminal is open (i,e, iB = 0) then this voltage is VCEO. If a negative Bvoltage is applied across the BE junction the right hand side limit of the RBSOA increasessomewhat to the value VCBO at low value of the collector current.In addition to the applicable limits on the output characteristics as represented in the FBSOA andthe RBSOA, limiting specification with respect to the base emitter junction is also provided bythe manufacturer. Typical specifications that are provided are VEBO : This is maximum allowable reverse bias voltage across the B-E junction IBB : Maximum allowable average base current at a given case temperature. IBM : Maximum allowable peak base current at a given case temperature and of specified pulse duration.The input characteristics (iB Vs VBE) at a given case temperature is also provided. BExercise 3.6Fill in the blank(s) with the appropriate word(s) a) In the “Cut off” region collector current of a Power Transistor is _____________. b) In the __________________ region of a Power Transistor the dc current gain remains fairly constant. c) Saturation region of a Power Transistor can be divided into _______________ region and ______________________ region. d) Active region operation of a Power BJT is limited mostly by _______________ consideration. e) “Second breakdown” in a Power BJT occurs due to ________________ of the collector current distribution. Answer: (a) negligible; (b) active; (c) Quasi saturation, hard saturation; (d) Power dissipation; (e) non uniformity.3.5 Switching characteristics of a Power TransistorIn a power electronic circuit the power transistor is usually employed as a switch i.e. it operatesin either “cut off” (switch OFF) or saturation (switch ON) regions. However, the operating Version 2 EE IIT, Kharagpur 15
  • 61. characteristics of a power transistor differs significantly from an ideal controlled switch in thefollowing respects. • It can conduct only finite amount of current in one direction when “ON” • It can block only a finite voltage in one direction. • It has a voltage drop during “ON” condition • It carries a small leakage current during OFF condition • Switching operation is not instantaneous • It requires non zero control power for switchingOf these the exact nature and implication of the first two has been discussed in some depth in theprevious section. The third and fourth non idealities give rise to power loss termed theconduction power loss. In this section the nature and implications of the last two non idealitieswill be discussed in detail.Exercise 3.7Fill in the blank(s) with the appropriate word(s) a) An ideal switch can conduct current in ______________ directions. While a power transistor conducts current in _______________ direction. b) In power transistor there will be power loss due to ON state ________________ and OFF state _________________. c) Unlike an ideal switch the switching of a power transistor is not ____________. Answer: (a) two, one; (b) voltage drop, leakage current; (c) instantaneous.3.5.1Turn On characteristics of a Power TransistorFrom the description of the basic operating principle of a power transistor presented in theprevious sections it is clear that minority carriers must be moved across different regions of apower transistor in order to make it switch between cut off and saturation regions of operation.The time delay in the switching operation of a power transistor is due to the time taken by theminority carriers to reach appropriate density levels in different regions. The exact level ofminority carrier densities (and depletion region widths) required for proper switching isdetermined by the collector current and biasing collector voltage during switching, both of whichare determined by external circuits. The rate at which these densities are attained is determinedby the base current waveform. Therefore, the switching characteristics of a power transistor isalways specified in relation to the external load circuit and the base current waveform as shownin Fig 3.6 which shows a clamped inductive switching circuit with a flat base drive. Version 2 EE IIT, Kharagpur 16
  • 62. VCC iD D IL iC + RB iB Q VCE VBE -VBB (a) Version 2 EE IIT, Kharagpur 17
  • 63. td tri tfv1 tfv2 VBB VBE VBE sat 0 t VBB - VBE(sat) RB iB t ic id IL IL t vCE VCC VCE (sat) t Pe VCC IL vCE (sat) IL t (b) Fig 3.6 Turn ON characteristics of a power transistor; (a) Switching circuit, (b) Switching wave formsThe switching wave forms shown in Fig 3.6 (b) are the expanded and to some extent “idealized”version of the actual waveforms that will be observed in a clamped inductive switching circuit asshown in Fig.3.6 (a). Some simplifying assumptions have been made to draw these waveforms.These are Version 2 EE IIT, Kharagpur 18
  • 64. • The load inductor has been assumed to be large enough so that the load current does not change during Turn ON period. • Reverse recovery characteristics of D has been ignored. • All parasitic elements have been ignored.Before t = 0, the transistor (Q) was in the “OFF” state. In order to utilize the increased breakdown voltage (VCBO) the base-emitter junction of a Power Transistor is usually reverse biasedduring OFF state. Under this condition only negligible leakage current flows through thetransistor. Power loss due to this leakage current is negligible compared to other components ofpower loss in a transistor. Therefore, it is not shown in Fig 3.6 (b). The entire load current flowsthrough the diode and VCE is clamped to VCC (approximately).To turn the transistor ON at t = 0, the base biasing voltage VBB changes to a suitable positivevalue. This starts the process of charge redistribution at the base-emitter junction. The process isakin to charging of a capacitor. Indeed, the reverse biased base emitter junction is oftenrepresented by a voltage dependent capacitor, the value of which is given by the manufacturer asa function of the base-emitter reverse bias voltage. The rising base current that flows during thisperiod can be thought of as this capacitor charging current. Finally at t = td the BE junction isforward biased. The junction voltage and the base current settles down to their steady statevalues. During this period, called the “Turn ON delay time” no appreciable collector currentflows. The values of iO and VCE remains essentially at their OFF state levels.At the end of the delay time (td ON) the minority carrier density at the base region quicklyapproaches its steady state distribution and the collector current starts rising while the diodecurrent (id) starts falling. At t = tdON + tri the collector current becomes equal to the load current(and id becomes zero) IL. At this point D starts blocking reverse voltage and VCE becomesunclamped. tri is called the current rise time of the transistor.At the end of the current rise time the diode D regains reverse blocking capacity. The collectorvoltage VCE which has so far been clamped to VCC because of the conducting diode “D” startsfalling towards its saturation voltage VCE (sat). The initial fall of VCE is rapid. During this periodthe switching trajectory traverses through the active region of the output characteristics of thetransistor. At the end of this rapid fall (tfv1) the transistor enters “quasi saturation region”. Thefall of VCE in the quasi saturation region is considerably slower. At the end of this slow fall (tfv2)the transistor enters “hard saturation” region and the collector voltage settles down to thesaturation voltage level VCE (sat) corresponding to the load current IL. Turn ON process endshere. The total turn on time is thus, TSW (ON) = td (ON) + tri + tfv1 + tfv2.Power loss occurs at all time during the operation of a power transistor. However, the collectorleakage current is usually negligibly small and power loss due it can be safely neglected incomparison to the power loss during ON condition. Power loss occurs during Turning ON aPower transistor due to simultaneous existence of non-zero VCE and ic during tri, tfv1, and tfv2. Theenergy lost during these periods is called the Turn ON loss and given by the area under the Plcurve in Fig 3.6 (b). The average Turn ON loss is obtained by dividing this area by (tri + tfv1 +tfv2). For safe Turn ON this average power loss must be less than the limit set on the maximum Version 2 EE IIT, Kharagpur 19
  • 65. power dissipation in the FBSOA corresponding to a pulse width greater than tri + tfv1 + tfv2.Similar restriction with respect to second break down should also be observed.Turn ON time can be reduced by increasing the base current. However large base currentincreases the quantity of excess carrier in the base and collector drift region which has to beremoved during Turn Off. As will be seen later this increases the Turn OFF time. The Turn ONdelay time can however be reduced by boosting the base current at the beginning of the Turn ONprocess. This can be achieved by connecting a small capacitance across RB. This increases the Brate of rise of VBE & iB. Therefore, Turn ON delay time decreases. However, in steady state iB B Bsettle downs to a value determined by RB & VBB and no adverse effect on the Turn OFF time is Bobserved.In figure 3.6 (b) the reverse recovery current of D has been neglected. If this current is notnegligible then for safe Turn ON operation the sum of the load current and the diode reverserecovery current must be less than the ICM rating of the transistor. Thermal and second breakdown limits must also be observed.It should be noted that there is some power loss at the BE junction as well. This power lossdepends on the current gain of the transistor during hard saturation. Since current gain reducesduring saturation (typically between 5 to 10) this power loss may become significant.Manufacturers usually provide the values of td (ON), tri, tfv as functions of ic for a given basecurrent and case temperature.Exercise 3.8Fill in the blank(s) with the appropriate word(s) a) For faster switching of a BJT _______________ carriers are to be swept quickly from the ________________ region. b) The reverse biased base emitter junction can be represented as a ______________ dependent __________________. c) In the quasi saturation region collector-emitter voltage falls at a ______________ rate. d) Turn ON delay can be reduced by __________________ the rate of rise of the base current. Answer: (a) minority, base; (b) voltage, capacitor; (c) slow; (d) increasing.3.5.2 Turn Off Characteristics of a Power TransistorDuring Turn OFF a power transistor makes transition from saturation to cut off region ofoperation. Just as in the case of Turn ON, substantial redistribution of minority charge carriersare involved in the Turn OFF process. Idealized waveforms of several important variables in theclamped inductive switching circuit of Fig. 3.6 (a) during the Turn OFF process of Q are shownin Fig 3.7 (a) Version 2 EE IIT, Kharagpur 20
  • 66. VBB VBE(sat) VBE tVBB iB t iC id IL IL t VCE VCE(Sat) VCC t Pe t ts trv1 trv2 tfi (a) Version 2 EE IIT, Kharagpur 21
  • 67. log iC Reverse recovery current of D ICM P’ FBSOA P RBSOA Forward recovery Voltage of D Turn off Turn on Trajectory Trajectory VCBO log vCE V(sus) VCEO (b) Fig. 3.7: Turn off, characteristics of a BJT. (a) Switching wave forms (b) Switching trajectoryThe “Turn OFF” process starts with the base drive voltage going negative to a value -VBB.The base-emitter voltage however does not change from its forward bias value of VBE(sat)immediately, due to the excess, minority carriers stored in the base region. A negative basecurrent starts removing this excess carrier at a rate determined by the negative base drive voltageand the base drive resistance. After a time “ts” called the storage time of the transistor, theremaining stored charge in the base becomes insufficient to support the transistor in the hardsaturation region. At this point the transistor enters quasi saturation region and the collectorvoltage starts rising with a small slope. After a further time interval “trv1” the transistor completestraversing through the quasi saturation region and enters the active region. The stored charge inthe base region at this point is insufficient to support the full negative base current. VBE startsfalling forward –VBB and the negative base current starts reducing. In the active region, VCEincreases rapidly towards VCC and at the end of the time interval “trv2” exceeds it to turn on D.VCE remains clamped at VCC, thereafter by the conducting diode D. At the end of trv2 the storedbase charge can no longer support the full load current through the collector and the collectorcurrent starts falling. At the end of the current fall time tfi the collector current becomes zero andthe load current freewheels through the diode D. Turn OFF process of the transistor ends at thispoint. The total Turn OFF time is given by Ts (OFF) = ts + trv1 + trv2 + tfiAs in the case of “Turn ON” considerable power loss takes place during Turn OFF due tosimultaneous existence of ic and VCE in the intervals trv1, trv2 and tfi. The last trace of Fig 3.7 (a)shows the instantaneous power loss profile during these intervals. The total energy last per turnoff operation is given by the area under this curve. For safe turn off the average powerdissipation during trv1 + trv2 + tfi should be less than the power dissipation limit set by the FBSOAcorresponding to a pulse width greater than trv1 + trv2 + tfi. Version 2 EE IIT, Kharagpur 22
  • 68. Turn OFF time intervals of a power transistor are strongly influenced by the operating conditionsand the base drive design. Manufacturers usually specify these values as functions of collectorcurrent for given positive and negative base current and case temperatures. Variations of thesetime intervals as function of the ratio of positive to negative base currents for different collectorcurrents are also specified.In this section and the precious one inductive load switching have been considered. However, ifthe load is resistive. The freewheeling diode D will not be used. In that case the collector voltage(VCE) and collector current (ic) will fall and rise respectively together during Turn ON and riseand fall respectively together during Turn OFF. Other characteristics of the switching processwill remain same. The switching Power loss in this case will also be substantially lower.Exercise 3.9Fill in the blank(s) with the appropriate word(s) a) Turn OFF process in a BJT is associated with transition from the _______________ region to the ______________ region. b) Negative _______________ current is required to remove excess charge carriers from the ______________ region of a BJT during Turn OFF process. c) VCE increases rapidly in the ________________ region. Answer: (a) Saturation, Cut-off; (b) base, base; (c) active.3.5.3 Switching Trajectory and Switching Losses in a Power TransistorIt has been mentioned in the earlier sections that energy loss takes place in a power transistorduring each switching operation. Instantaneous power loss during switching can be calculatedand plotted as shown in Fig 3.6 (b) and 3.7 (a). The areas under these curves indicate the energyloss during each switching operation (Turn ON and Turn OFF). Indicating these areas as EON andEOFF during Turn ON and Turn OFF operations respectively one can write. E ON = 1⎡ 2 ⎣ CC L ri ( ) V I t + ( VCC + VCEf1 ) I L t fv1 + VCEf1 + VCE (sat ) I L t fv2 ⎤ ( 3.5 ) ⎦Where VCEf1 is the value of VCE at the end of the interval tfv1Similarly E OFF = 1 ⎡( VCE ( sat ) + VCEr1 ) I L t rv1 + ( VCEr1 + VCC ) I L t rv2 + VCC I L t fi ⎤ ( 3.6 ) 2⎣ ⎦If the switching frequency of the transistor is fSW, then the average switching power loss is givenby PSW = ( E ON + E OFF ) fSW ( 3.7 ) Version 2 EE IIT, Kharagpur 23
  • 69. On the other hand the conduction energy loss is given by the area hatched black in Fig 3.6 (b)and 3.7(a). From these figures the conduction power loss is given by PC = VCE ( sat ) IL ( TON - t d ( ON ) - t ri - t fv1 - t fv2 + t s ) fSW ( 3.8)Where TON is the time period for which the base drive voltage remain positive. Usually ts –TSW(ON) << TON, Therefore PC = VCE ( sat ) IL TON fSW = VCE ( sat ) IL D ( 3.9)Where D is the switching duly cycle.For a given VCC and IL and base drive design, EON and EOFF are constant. Therefore, theswitching power loss is proportional to the switching frequency. Being a minority carrier devicea BJT has comparatively larger switching times (compared to some other devices broadlycategorized as transistors) and hence larger switching power loss for a given frequency. On theother hand a BJT has the lowest ON state voltage drop VCE (sat) among all fully controlledswitches. Therefore, a BJT is suitable for switching large current at moderate (around a fewKHZ) switching frequency. At high frequency BJT based circuits tend to become inefficient dueto increased switching power loss.Even without any restriction on the switching power loss the maximum switching frequency of aBJT is limited by its Turn ON and Turn OFF times. The value of the maximum switchingfrequency is given by 1 FSW ( Max ) = ( 3.10 ) TSW ( ON ) + TSW ( OFF )For a given collector current and base drive design.For safe switching operation, however it is not sufficient to merely restrict the switching powerloss. It will be necessary to restrict the switching trajectory (an instantaneous plot of ic vs VCEduring switching with time as a parameter) within the FBSOA /RBSOA region corresponding toa pulse width greater than TSW (ON) or TSW (OFF). Fig 3.7 (b) shows these switching trajectoriessuperimposed on the FBSOA /RBSOA. In this diagram the green line corresponds to the TurnON trajectory while the blue line corresponds to the Turn OFF trajectory. These trajectories arerectangular in nature. Clearly full voltage (VCEO) or current rating (ICM) of the transistor can notbe utilized in such a trajectory. The situation becomes worse a when the reverse recovery currentand forward recovery voltage of D is considered. Switching aid circuits or “snubbers” (as theyare popularly known) are used to enhance the switching performance of a power transistor. Theyserve two specific purpose. • Shape the switching trajectory such that the voltage and current rating of a transistor can be fully utilized. Version 2 EE IIT, Kharagpur 24
  • 70. • Reduce the switching power loss inside the device.Fig. 3.8 shows a typical snubber circuit for a power transistor and the corresponding switchingtrajectories. VCC D IL LS RS iC + DS Q VCE RB iB CS - VBB + (a) logic ICM IL RBSO FBSO A Turn VCBO on VCC Turn off log vCE VCE(sus) VCEO (b) Fig. 3.8: Switching characteristics of a BJT with Snubber (a) Clamped inductive switching circuit with snubber (b) Switching trajectory. Version 2 EE IIT, Kharagpur 25
  • 71. Fig 3.8 (a) shows the same clamped inductive switching circuit of Fig 3.6 (a) but with thesnubber elements. The inductor LS connected between the load and the collector is the Turn ONsnubber. In decouples the collector from the supply voltage during Turn ON. Therefore, as thejunction VBE becomes forward biased VCE starts falling. At the same time ic also starts risingtowards IL. The resultant switching trajectory is shown by the solid green line in Fig 3.8 (b). Thisshould be compared with the unsnubbed Turn ON trajectory (broken green line). In theunsnubbed case, the collector current rises to the maximum value before VCE starts falling fromVCC. VCC, therefore, must necessarily be smaller than VCE (SUS). In the snubber assistedtrajectory VCE falls substantially before ic rises to any appreciable value. Therefore, VCC can bemade larger than VCE(sat) and can be chosen closer to VCEO. Maximum collector current that canbe handled is also considerably higher (I L Max ) = ICM - Irr ( D ) . In the unsnubbed casemaximum IL is restricted essentially by the maximum power dissipation consideration and not byICM. LS also helps to reduce Irr (D) by restricting the rate of decrease of current through D. Thisalso helps to increase I L MaxRs-Cs-Ds constitute the Turn OFF snubber. This is popularly known as the “R-C-D snubber”.During Turn OFF as the base drive of Q is removed ic starts falling and the remaining loadcurrent is bypassed to Cs through Ds. Therefore, the collector voltage rises simultaneously givingrise to the Turn OFF trajectory shown by the solid blue line in Fig 3.8 (b). At the end of the TurnOFF process VCE shoots over VCC due to Ls-Cs oscillation. However, by proper design VCE Maxcan be restricted well below VCBO. Therefore, the turn OFF snubber circuit can effectively utilizethe enhanced voltage withstanding capability of a power transistor with base reverse biased.Comparison of the switching trajectories with and with out snubber circuit makes it evident thatthe snubber circuit can considerably enhance the voltage and current capacity utilization of aPower transistor.The area enclosed under the switching trajectories is a measure of the switching loss occurring inthe device at each switching. Therefore, it is evident from Fig 3.8 (b) that the snubber circuitreduces the switching power loss inside the device considerably. However, it should beemphasized that the total switching loss (device + snubber resistance) may not reduce. It is alsonecessary to place the snubber components very close to the transistor since any stray inductancein the Rs – Cs – Ds loop may give rise to an unacceptably large voltage spike across Q.Components should also be chosen very carefully. Rs must be non inductive and the leadinductances of Ds and Cs must be kept to a minimum Power loss in Rs can be considerably largeand its wattage should selected accordingly. To avoid excessive power loss in Rs, lossless(regenerate) snubber circuits have been proposed.Exercise 3.10Fill in the blank(s) with the appropriate word(s) a) BJT has large switching times, since it is a _________________ carrier device. b) BJT has _______________ ON state voltage drop. c) BJT is inefficient at ______________ switching frequencies. Version 2 EE IIT, Kharagpur 26
  • 72. d) Turn OFF snubber circuit is used to improve _______________ withstand capacity of a BJT. Answer: (a) minority; (b) low; (c) high; (d) voltage.Exercise 3.11What are the effects of introducing a drift region in the output i-v characteristics of a powertransistor?Answer: The drift region in a power transistor is introduced in order to block large forward voltage. However, one effect of introducing the drift region is the appearance of a “quasi saturation region” in the output i-v characteristics of a power transistor. In the quasi saturation state the drift region is not completely shorted out by “conductivity modulation” by excess carriers from the base region. In offers a resistance which is a function of the base current. Although the base current retain some control over collector current in this state the value of dc current gain reduces substantially due to increased effective base width. Another effect of introducing the drift region is to make the VCE saturation voltage depend linearly on the collector current in the hard saturation region due to the ohmic resistance of the “conductivity modulated” drift region.Exercise 3.12Explain the importance of the following manufacturer’s specifications (a) FBSOA, (b) β vs ic characteristics, (c) iB vs VBE characteristics BAnswer: (a) FBOSOA compactly represents the safe operating limits of a power transistor in terms of maximum forward current, maximum forward voltage, maximum average & instantaneous power dissipation and second break down limits. It is most useful in designing the switching trajectory of a power transistor. (b) This characteristics gives the amount of base current required so that the transistor can operate in the saturation mode for a given collector current. (c) After the base current is determined, this characteristics is used to design the base drive circuit for a given base power source.3.5.4 Base Drive Design and Power DarlingtonThe performance of a Power transistor depends largely on the base drive design.• The rate of rise of base current in the beginning of the turn on process determines the turn on delay time.• The magnitude of the base current during turn on decides the values of the voltage fall time, current rise time and VCE (sat) for a given collector current. Version 2 EE IIT, Kharagpur 27
  • 73. • The negative base current during turn off determines the storage time, voltage rise time and current fall time.• A negative bias at the base also enhances the voltage withstanding capacity of a power transistor. From the discussion of the switching characteristics of a BJT it is evident that the base drive voltage source should be bipolar and the base drive resistance should be different during turn on and turn off. The following step by step procedure can be followed to arrive at the values.• From the load current value (to be switched) and desired conduction power loss the desired value of VCE (sat) is determined.• Using the desired value of VCE (sat) for the given load current, the required value of forward base current (iBP) and the corresponding VBE (sat) is obtained from the manufacturer’s data sheet.• The forward and reverse base drive voltages (VBB + & VBB -) are decided on the basis of the availability of control power supply. These should be kept as low as possible in order to reduce base drive power requirement.• The forward base drive resistance RBP is given by VBB+ - VBE ( sat ) R BP = ( 3.11) i BP It has been mentioned earlier that the turn on delay time can be reduced by increasing the rate of rise of iBP at the beginning of the turn ON process. This is achieved by connecting a small capacitor across RBP.• Once iBP is known the turn on loss is fixed. The allowable turn off loss is determined by subtracting the turn on loss for the desired total switching loss. The required current fall and voltage rise times for the calculated turn off loss is determined for the given load current and VCC.• A suitable negative base current (iBN) to give the desired voltage rise time is determined from the manufacturer’s data sheet.• RBN is given VBB- + VBE ( sat ) R BN = ( 3.12 ) i BN Version 2 EE IIT, Kharagpur 28
  • 74. • Once iBN is fixed the storage time (ts) can be determined from the manufacturer’s data sheet.• The storage time can be reduced by connecting a small capacitor across RBN. The resulting base drive circuit can be realized as shown in Fig 3.9 VBB + RBP R1 R3 From Q Control circuit Optocoupler R2 RBN Electrical Isolation VBB - Fig 3.9: Typical base drive circuit of a power transistorPower transistors have low values of dc current gain (β) compared to their signal levelcounterpart. Particularly, if a low value of VCE (sat) is desired at full load current, β can be aslow as 5. With such low gain large current switching becomes difficult since the base drivecircuit is required to handle about 20% of the full load current, Monolithic, Darlington connectedtransistors can solve this problem. Fig 3.10 shows the circuit connection and the vertical crosssection of a Monolithic Darlington pair. The effective current gain of a Darlington pair is givenby β = β Mβ D + β M + β D ( 3.13)So that even when individual β’s are small effective β can still be quite large. Version 2 EE IIT, Kharagpur 29
  • 75. C iCD IL B IBD iCM QD iED QM iBM D E (a)B iED E n+ n+ iBD iBM p sio2 p’ n- iCD n- iCM n+ n+ C (b)Fig 3.10: Monolithic Darlington connected power transistor. (a) circuit diagram, (b) schematic cross section. Version 2 EE IIT, Kharagpur 30
  • 76. In the Darlington configuration the base drive current for the main transistor is derived from thecollector biasing power supply through a drive transistor. This drive transistor should have thesame voltage rating as the main transistor but lower current rating. In a monolithic design bothare fabricated from the same crystal. The silicon protrusion through the p layer (the base regionfor both transistors) isolates the two bases from each other. A discrete diode D is added (Fig 3.10(a)) to speed up the turn off time of the main transistor.The major quantitative difference in the operating characteristics of a Power Darlington is due tothe fact that the main transistor can not go into hard saturation. The ON state voltage drop of thedrive transistor prevents forward biasing of the C-B junction of the main transistor. Therefore,the ON state power dissipation of the main transistor will be larger than that of an otherwisecomparable single BJT. The switching times will also be somewhat larger for the Darlingtontransistor.Exercise 3.13 A Power BJT is used to switch an inductive load carrying 20 A. The supply voltage is 200V, switching frequency and duty cycle are 1 KHZ and 0.5 respectively. Switching times are as follows. td = 1μs, tri = tfv1 = 8 μs, tfv2 = 0, ts = 12 μs, tfi = trv2 = 8 μs, trv1 = 0. VCE sat = 1.0V at i c = 20 A Calculate switching and conduction losses in the transistor.Answer: Turn on energy loss is given by. 1 E ON = V I ( t + t ) = 32 mJ 2 CC L ri fv1 Turn off energy loss is given by E off = 1 VCC I L ( t fi + t rv2 ) = 32mJ 2 So total energy loss per switching = EON + E0ff = 64 mJ. ∴ Switching power loss = fsw (EON + Eoff) = 64 watts. Conducting loss per switching is given by E COND = I L VCE sat ( D fsw - t d ) - t ri - t fv + t s = 9.9 mJ ∴ Conduction power loss = 9.9 watts.Exercise 3.14With reference to Fig. 3.9 determine the values of the base resistors RBP & RBN for the followingdata VBB+ = 10 volts, VBB- = -10 V, IBP = 2.5 A, IBN = 1.5 A, VBE sat = 0.7 V , VCE sat (of drive transistors) = 0.3 V Version 2 EE IIT, Kharagpur 31
  • 77. VBB + - VBE sat - VCEAnswer: R BP = sat = 3.6 ohms. I BP VBE sat - VCE sat - VBB- R BN = = 6.93 ohms I BN Version 2 EE IIT, Kharagpur 32
  • 78. References 1) Jacob Millman, Christos C. Halkis, “Integrated Electronics, Analog and Digital circuit and systems”, Tata McGrow-Hill publishing Company Limited, New Delhi, 1991. 2) Ned Mohan, Tore M. Undeland, William P. Robbins, “Power Electronics, Converters, Application and Design”. John Willey & Sons (Asia) Publishers, Third Edition, 2003. Version 2 EE IIT, Kharagpur 33
  • 79. Lesson Summary • A Bipolar Junction Transistor is a minority carrier, current controlled unidirectional device. • A BJT can be of n-p-n or p-n-p type with three terminals called the collector, the base and the emitter. • A BJT can operate in cut-off, active or saturation regions. • In the cut-off region the base emitter junction is reverse biased and the collector current is almost zero. • In the active region the ratio of collector current to base current is fairly constant. This ratio is called the dc current gain (β). • A transistor can be driven into saturation by increasing the base current for a given collector current. In saturation the VCE voltage drop of a transistor is very low. • For power application normally, n-p-n type transistor in the common emitter configuration with the base as the control terminal is used. They operate either in the cut- off, or saturation mode. • For safe operation power transistors must observe maximum current, maximum voltage, maximum power dissipation and second break down limits. • Operating restrictions applicable to a power transistor under forward and reverse bias conditions are represented compactly in FBSOA & RBSOA diagrams respectively. • Power transistor output i-v characteristics exhibits a quasi saturation region not found in their signal level counterpart. It is the direct consequence of introducing a lightly doped n- drift region in the structure of a power transistor which enhances its forward voltage blocking capacity. • Switching of Power transistors from ON (saturation) to OFF (cut-off) state involves considerable redistribution of minority carriers. Therefore, switching operation is not instantaneous. • Switching characteristics of a power transistor is greatly influenced by the external load circuit and the base drive circuit. • Energy loss takes place during each switching operation of a power transistor due to simultaneous existence of collector current and voltage. This is called switching loss. • Energy loss taking place during ON condition of the transistor is called the conduction loss. Conduction loss during the OFF state of a Power transistor is negligibly small. • Switching power loss is proportional to the switching frequency while the conduction power loss is proportional to the duly cycle. • BJT being a minority carrier device have low on state voltage drop and longer switching delay times compared to some “majority” carrier “transistors”. Consequently, BJT has higher switching loss and lower conduction loss. • A Power transistor is suitable for large current switching at low to moderate (a few kHZ) frequency. Version 2 EE IIT, Kharagpur 34
  • 80. • Switching aid circuits (snubbers) are used for enhancing the capacity utilization of a power transistor. They also reduce switching loss internal to the device.• Ordinary L-R-C-D snubber circuits may not reduce total switching loss. For that purpose lossless (regenerative) snubber circuits are used.• Proper design of the base drive circuit helps to reduce both conduction and switching losses. For optimal operation, base drive voltage should be bipolar and have different output resistance for Turn ON and Turn OFF operations.• Power transistors have relatively small current gain (β) and hence require large base drive current.• Monolithic Power Darlingtons can solve the problem of low current gain. But they have larger ON state voltage drop and longer switching times. Version 2 EE IIT, Kharagpur 35
  • 81. Practice Problems and Answers Version 2 EE IIT, Kharagpur 36
  • 82. VCC = 200V RL = 20Ω RB + VBB = 12V -1. In the transistor switching circuit VBE sat = 0.75 V, VCE sat = 0.2 V 10 ≤ β ≤ 40 . Find out the value of RB and Power requirement of the base source. B VCC = 200V RL = 20Ω D3 RB + D1 D2 VBB = 12V -2. In the transistor switching circuit shown VBE sat = 0.75 v, VD1 = VD2 = VD3 = 0.7 v, 10 ≤ β ≤ 40 Find maximum allowable value of RB and power output of the base source. Also compare B conduction power loss with the circuit shown in Problem – 1.3. The transistor of Problem -1 has the following switching time specifications. td = 1μs, tri = tfv = 2.5 μs, ts = 5 μs, tfi = trv = 2.5 μs. The transistor is switched at a frequency of 10 KHZ with duty ratio d = 0.5. Find out, (i) conduction power loss, (ii) switching power loss. Version 2 EE IIT, Kharagpur 37
  • 83. VBB ∫∫ 50μs 50μs ∫∫ ∫∫ t iC ∫∫ 10 A ∫∫ ∫∫ t td t ts tfi ri VCE ∫∫ 200v 200v ∫∫ t tfv trv PSW (on) PSW (off) Ploss PCOND t4. Figure shows practical implementation of a power transistor base drive circuit. The comparator has an output voltage swing of ± 12 V. Also For QP VBE sat = 0.7V, VCE sat = 0.2V, For QN VBE sat = - 0.7 V, VCE sat = - 0.2 V, For Q VBE sat = 0.75 V. β Min = 10. Also it is desired that negative base current should be at least equal to positive base current. β Min of QP & QN are same. Find the values of RBP, RBN and R15. Explain why the dc current gain of a Power BJT is considerably lower compared to its Signal level counterpart. What adverse effect does it have on the switching performance of a BJT? Suggest one solution to this problem. Version 2 EE IIT, Kharagpur 38
  • 84. 6. Differentiate between the voltage ratings VSUS, VCEO & VCBO of a Power BJT. How can these three voltage ratings of a BJT be utilized in an inductive switching circuit.7. The pulsed FBSOA of a Power BJT is usually specified for a very low duty cycle. Then now does it help to extend the usable voltage and current rating of a BJT?Answer to Test Problems 200 - VCE sat1. The load current I L = i c = ≈ 10 Amps 20 VCE sat = 0.2V, which indicates that the transistor is in hard saturation. Therefore β = βmin = 10. ic So required base current = = 1 amps 10 VBE sat = 0.75 volts ∴ R B = VBB - VBE sat = 11.25 Ω Power drawn from base source is 12 × 1 = 12 watts.2. In this case VCE = VBE sat + VD2 + VD1 - VD3 = 1.45 volts . The transistor is not in saturation since VCB is positive. So β = βmax = 40 200 -1.45 IL = ic = = 9.93 Amps. 20 i ∴ i B = c = 0.25 Amps. β For maximum value of RB current through D3 will be zero B V -V -V -V So R B = BB D1 D2 BE sat = 39.4 Ω iB Power Drawn from base source is 12 × 0.25 = 3 watts. Conduction power lass in 1st problem was 10 × 0.2 = 2 watts Conduction power lass in this case is 9.93 × 1.45 = 14.4 watts Note: This circuit is known as the anti-saturation clamp or the “Baker’s clamp”. Version 2 EE IIT, Kharagpur 39
  • 85. + 15v + 12v VCC RBP IL = 50 A iC1 iB1 QP 10 KΩ Rl iE1 comp 0 A B QPTTL iB iE2Pulse E QN 1.5v iB2 iC2 RBN - 12v - 15v 3. Figure shows switching waveforms of the transistor. Major difference with clamped inductive switching waveform is that in this case rise and fall of ic & VCE are simultaneous. In the interval t ri ( or t fv ) t ic = 10 = 4×106 t t ri VCE ≈ 200 ⎛ 1- t ⎞ = 200 ( 4 × 105 t ) . ⎜ ⎝ t fv ⎟ ⎠ where VCE sat has been neglected. In the interval t fi ( or t rv ) i c = 10 ⎛1- t ⎞ = 10 (1 - 4 × 105 t ) ⎜ ⎝ t fi ⎟ ⎠ VCE = 200 t = 80 × 10 6 t t rv Version 2 EE IIT, Kharagpur 40
  • 86. t ri ∴ E SW ( ON ) = ∫ o VCE i c dt 2.5×106 8×108 t (1- 4×105t ) dt = ∫ o = 0.83 mJ t fi 2.5×106 8×108 t (1- 4×105 t ) dt E SW ( OFF ) = ∫ o VCE i c dt = ∫o = 0.83 mJ ∴ E SW = E SW ( ON ) + E SW ( OFF ) = 1.66 mJ ∴ PSW = E SW × f SW = 1.66×10-3 × 10 × 103 = 16.6 watts. Conduction loss occurs in the interval from the end of tri to the beginning of tfi ∴ E COND = VCE sat × I L × ( TON - td - t ri + t s ) = 0.103 mJ ∴ PCOND = E COND × f SW = 0.103 × 10 -3 × 10 × 103 = 1.03 watts.4. For the transistor Q, β Min = 10 , & ic = 50 A. ∴required positive i BP = 50 = 5 Amps 10 Now i BP = i E1 = i c1 + i B1 12 - VAB - VBE 10.55 Now i B1 = = R1 R1 15 - VCE sat - VBE 14.1 i C1 = = R BP R BP 10.55 14.1 So + = 5 R1 R BP Now iBN ≥ iBP = 5A i BN = i E2 = i B2 + i C2 VBE - VBA + 12 12.05 i B2 = = R1 R1 VBE - VEC2 + 15 15.55 i C2 = = R BN R BN 12.05 15.55 So + ≥ 5 R1 R BN Now βmin of QP & QN are same. Version 2 EE IIT, Kharagpur 41
  • 87. i C1 i So = C2 i B1 i B2 14.1 R 1 15.55 R 1 or = 10.55 R BP 12.05 R BN 14.1 R 1 5R 1 Now 1 + = 10.55 R BP 10.55 10.55 R 1 5R 1 1+ ≥ 12.05 R BN 12.05 ⎛ 1 1 ⎞ ∴ 0 ≥ 5R 1 ⎜ - ⎟ ⎝ 12.05 10.55 ⎠ or R 1 > 0 choose R 1 = 100 Ω ∴ R BP = 2.88 Ω R BN = 2.78 Ω5. The main reason for comparatively lower dc current gain in a power transistor is a relatively thicker base region (a few tens of μm compared to a fraction of a μm incase of a signal transistor). The thicker base region is required to withstand the large blocking voltage. Unlike a power diode the doping density of the base region cannot be made very much large compared to the lightly doped collector drift region since it will reduce “β” by increasing minority carrier injection into the emitter. As a result the depletion layer at the C-B junction penetrates considerably in to the base region. The base width has to be larger than this penetration depth. A thicker base leads to larger rate of recombination of minority carriers injected by the emitter. Therefore, for a given collector current the required base current is relatively high and the dc current gain is low. A second reason for lowering of β arises from the “emitter crowding” effect where by the collector current tends to “crowd” near specific regions of the emitter. In these localized high current density regions β tends to fall off very sharply reducing the effective dc current gain. Due to lower dc current gain the base current requirement of a power transistor switching circuit increases. This requires a large base drive power supply and increased base drive power loss. This problem can be solved to some extent by using two power transistors connected in the “Darlington configuration” as shown. Version 2 EE IIT, Kharagpur 42
  • 88. iCD iL iBD QD βD iCM βM QM iED For this configuration. i L = i CD + i CM But i CD = β D i BD i CM = β M i ED = β M ( i BD + i CD ) ∴ i L = β Di BD + β Mi BD + β Mβ Di BD = (β M + β D + β Mβ D ) i BD = β eqv i BD equivalent β (βeqv) can be increased considerably due to multiplication of βM & βD. Power Darlington has one problem, however. The main transistor (QM) does not go into hard saturation due to VCE drop of QD. Therefore, the conduction loss is higher.6. The voltage rating VSUS is the maximum allowable voltage across C & E when the transistor is in active region with iB > 0 and collector current above a minimum value. B With both iB and iC greater than zero, there is considerable supply of minority carriers which B are accelerated by the large CB junction electric field to start avalanche breakdown at a relatively lower voltage. Therefore, the voltage rating VSUS is the lowest of the three. The rating VCEO is the maximum allowable voltage between C & E terminals when the transistor is in cut off region with iB = 0 or iC is less than a specified value. Under this B condition the supply of minority carriers at the CB junction is much less compared to the previous case. Therefore, avalanche breakdown of the CB junction occurs at a higher voltage. Thus VCEO > VSUS. The rating VCBO is the maximum allowable voltage between C & E terminals when the transistor is in cut off with iB < 0 and iC less than a specified value. With iB = 0 the EB B B junction is still forward biased and there is small injection of minority carriers from the emitter to the CB junction. However, with iB < 0 base emitter junction is reverse biased and B there is no supply of minority carriers to the CB junction from the emitter. Thus avalanche Version 2 EE IIT, Kharagpur 43
  • 89. break down of this junction occurs at a relatively higher voltage making the rating VCBO largest of the three. Therefore, in general for a power transistor. VCBO > VCEO > VSUS In an inductive switching circuit using snubber the collector voltage falls considerably before iC builds up to any significant level. This can be utilized to increase the usable steady state blocking voltage of the transistor up to VCEO. Since VCE will go below VSUS before iC can build up to the level where the rating VSUS becomes applicable. Similarly during turn off, the overshoot in the VCE voltage can be accommodated in the difference between VCBO and VCEO. Since during turn off iB < 0 and the voltage. overshoot B occurs with iC = 0 the applicable voltage limit will be VCBO and not VCEO. However, precaution must be taken such that the voltage over shoot decays before iB becomes equal to B zero. However, if a snubber circuit is not used the applicable voltage limit will always be VSUS since in this case VCE does not fall till iC rises to its full value during turn ON. Similarly during turn off iC does not fall till VCE rises to steady state blocking voltage level. log iC ICM BP Pulsed CP CD DC BD O AD AP log vCE7. The main difference between the DC and pulsed FBOSA is in the boundary corresponding to maximum power dissipation and second break down. With only DC FBSOA the switching trajectory has to be restricted to something similar to AD BD CD. However, with pulsed FBSOA applicable limits of power dissipation and second break down increases considerably. Both these limits require simultaneous existence of nonzero VCE & iC which for a power transistor occurs only during switching. Therefore, the increases FBSOA can be utilized and the switching trajectory improved to AP BP CP provided total switching time is less than the pulse period for which the increased FBSOA is applicable. Version 2 EE IIT, Kharagpur 44
  • 90. In addition pulsed FBSOA s are usually specified for a very low duty ratio. This conditioncan be easily satisfied provided total turn on and turn off times of the transistor expressed asa percentage of total “ON” and “OFF” periods of the transistor is less than this duty ratiosince during ON or OFF period the transistor remain well within DC FBSOA. In practice thiscondition is satisfied by specifying a minimum ON and OFF period of the transistor. Version 2 EE IIT, Kharagpur 45
  • 91. Module 1Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1
  • 92. Lesson 4Thyristors and Triacs Version 2 EE IIT, Kharagpur 2
  • 93. Instructional objectsOn completion the student will be able to • Explain the operating principle of a thyristor in terms of the “two transistor analogy”. • Draw and explain the i-v characteristics of a thyristor. • Draw and explain the gate characteristics of a thyristor. • Interpret data sheet rating of a thyristor. • Draw and explain the switching characteristics of a thyristor. • Explain the operating principle of a Triac. Version 2 EE IIT, Kharagpur 3
  • 94. 4.1 IntroductionAlthough the large semiconductor diode was a predecessor to thyristors, the modern powerelectronics area truly began with advent of thyristors. One of the first developments was thepublication of the P-N-P-N transistor switch concept in 1956 by J.L. Moll and others at BellLaboratories, probably for use in Bell’s Signal application. However, engineers at GeneralElectric quickly recognized its significance to power conversion and control and within ninemonths announced the first commercial Silicon Controlled Rectifier in 1957. This had acontinuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (alsoknown as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modestbeginning and now high power light triggered thyristors with blocking voltage in excess of 6kvand continuous current rating in excess of 4kA are available. They have reigned supreme for twoentire decades in the history of power electronics. Along the way a large number of other deviceswith broad similarity with the basic thyristor (invented originally as a phase control type device)have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch(SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse ConductingThyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO).From the construction and operational point of view a thyristor is a four layer, three terminal,minority carrier semi-controlled device. It can be turned on by a current signal but can not beturned off without interrupting the main current. It can block voltage in both directions but canconduct current only in one direction. During conduction it offers very low forward voltage dropdue to an internal latch-up mechanism. Thyristors have longer switching times (measured in tensof μs) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off usinga control input, have all but eliminated thyristors in high frequency switching applicationsinvolving a DC input (i.e, choppers, inverters). However in power frequency ac applicationswhere the current naturally goes through zero, thyristor remain popular due to its low conductionloss its reverse voltage blocking capability and very low control power requirement. In fact, invery high power (in excess of 50 MW) AC – DC (phase controlled converters) or AC – AC(cyclo-converters) converters, thyristors still remain the device of choice.4.2 Constructional Features of a ThyristorFig 4.1 shows the circuit symbol, schematic construction and the photograph of a typicalthyristor. Version 2 EE IIT, Kharagpur 4
  • 95. A A p n- G p K n+ n+ (a) G (c) K (b) Fig. 4.1: Constructional features of a thysistor (a) Circuit Symbol, (b) Schematic Construction, (c) Photograph As shown in Fig 4.1 (b) the primary crystal is of lightly doped n- type on either side ofwhich two p type layers with doping levels higher by two orders of magnitude are grown. As inthe case of power diodes and transistors depletion layer spreads mainly into the lightly doped n-region. The thickness of this layer is therefore determined by the required blocking voltage of thedevice. However, due to conductivity modulation by carriers from the heavily doped p regionson both side during ON condition the “ON state” voltage drop is less. The outer n+ layers areformed with doping levels higher then both the p type layers. The top p layer acls as the “Anode”terminal while the bottom n+ layers acts as the “Cathode”. The “Gate” terminal connections aremade to the bottom p layer. As it will be shown later, that for better switching performance it is required to maximizethe peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions arefinely distributed between gate contacts of the p type layer. An “Involute” structure for both thegate and the cathode regions is a preferred design structure.4.3 Basic operating principle of a thyristorThe underlying operating principle of a thyristor is best understood in terms of the “twotransistor analogy” as explained below. Version 2 EE IIT, Kharagpur 5
  • 96. A A A IA p p Q1 (α1) J1 iC2 iC1 - - n n IG J2 (α2) Q2 G p p n- G J2 n+ n+ J3 p J3 IK n+ KG K K (a) (b) (c) Fig. 4.2: Two transistor analogy of a thyristor construction. (a) Schematic Construction, (b) Schematic division in component transistor (c) Equivalent circuit in terms of two transistors. a) Schematic construction, b) Schematic division in component transistor c) Equivalent circuit in terms of two transistors. Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode positive with respect to the cathode and the gate terminal open. With this voltage polarity J1 & J3 are forward biased while J2 reverse biased. Under this condition. ic1 = ∝1 I A + I co1 ( 4.1) ic 2 = ∝ 2 I K + I co2 ( 4.2 ) Where ∝1 & ∝2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse saturation currents of the CB junctions of Q1 & Q2 respectively. Now from Fig 4.2 (c). i c1 + i c2 = I A ( 4.3) & IA = IK ( 4.4 ) (∵ I G = 0 ) Combining Eq 4.1 & 4.4 I co1 + I co2 I co IA = = 1- ( ∝1 + ∝ 2 ) 1- ( ∝1 + ∝ 2 ) ( 4.5 ) Version 2 EE IIT, Kharagpur 6
  • 97. Where I co I co1 + I co2 is the total reverse leakage current of J2Now as long as VAK is small Ico is very low and both ∝1 & ∝2 are much lower than unity.Therefore, total anode current IA is only slightly greater than Ico. However, as VAK is increasedup to the avalanche break down voltage of J2, Ico starts increasing rapidly due to avalanchemultiplication process. As Ico increases both ∝1 & ∝2 increase and ∝1 + ∝2 approaches unity.Under this condition large anode current starts flowing, restricted only by the external loadresistance. However, voltage drop in the external resistance causes a collapse of voltage acrossthe thyristor. The CB junctions of both Q1 & Q2 become forward biased and the total voltagedrop across the device settles down to approximately equivalent to a diode drop. The thyristor issaid to be in “ON” state.Just after turn ON if Ia is larger than a specified current called the Latching Current IL, ∝1 and∝2 remain high enough to keep the thyristor in ON state. The only way the thyristor can beturned OFF is by bringing IA below a specified current called the holding current (IH) whereupon ∝1 & ∝2 starts reducing. The thyristor can regain forward blocking capacity once excessstored charge at J2 is removed by application of a reverse voltage across A & K (ie, K positivewith respect A).It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate tocathode) without increasing the forward voltage across the device up to the forward break-overlevel. With a positive gate current equation 4.4 can be written as IK = IA + IG ( 4.6 ) ∝ 2 I G + I coCombining with Eqns. 4.1 to 4.3 I A = 1- ( ∝1 + ∝ 2 ) ( 4.7 )Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and henceVAK). This is called gate assisted turn on of a Thyristor. This is the usual method by which athyristor is turned ON.When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.)junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the junction J3 has avery low reverse break down voltage since both the n+ and p regions on either side of thisjunction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported byjunction J1. The maximum value of the reverse voltage is restricted by a) The maximum field strength at junction J1 (avalanche break down) b) Punch through of the lightly doped n- layer.Since the p layers on either side of the n- region have almost equal doping levels the avalanchebreak down voltage of J1 & J2 are almost same. Therefore, the forward and the reverse breakdown voltage of a thyristor are almost equal.Up to the break down voltage of J1 the reversecurrent of the thyristor remains practically constant and increases sharply after this voltage.Thus, the reverse characteristics of a thyristor is similar to that of a single diode. Version 2 EE IIT, Kharagpur 7
  • 98. If a positive gate current is applied during reverse bias condition, the junction J3 becomesforward biased. In fact, the transistors Q1 & Q2 now work in the reverse direction with the rolesof their respective emitters and collectors interchanged. However, the reverse ∝1 & ∝2 beingsignificantly smaller than their forward counterparts latching of the thyristor does not occur.However, reverse leakage current of the thyristor increases considerably increasing the OFF statepower loss of the device.If a forward voltage is suddenly applied across a reverse biased thyristor, there will beconsiderable redistribution of charges across all three junctions. The resulting current canbecome large enough to satisfy the condition ∝1 + ∝2 = 1 and consequently turn on the thyristor.This is called dv turn on of a thyristor and should be avoided. dtExercise 4.11) Fill in the blank(s) with the appropriate word(s) i. A thyristor is a ________________ carrier semi controlled device. ii. A thyristor can conduct current in ________________ direction and block voltage in ________________ direction. iii. A thyristor can be turned ON by applying a forward voltage greater than forward ________________ voltage or by injecting a positive ________________ current pulse under forward bias condition. iv. To turn OFF a thyristor the anode current must be brought below ________________ current and a reverse voltage must be applied for a time larger than ________________ time of the device. v. A thyristor may turn ON due to large forward ________________.Answers: (i) minority; (ii) one, both; (iii) break over, gate; (iv) holding, turn off; (v) dv dt2. Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse biascondition (i. e cathode positive with respect to anode)?Answer: The two transistor analogy of thyristor shown in Fig 4.2 (c) indicates that when areverse voltage is applied across the device the roles of the emitters and collectors of theconstituent transistors will reverse. With a positive gate pulse applied it may appear that thedevice should turn ON as in the forward direction. However, the constituent transistors have verylow current gain in the reverse direction. Therefore no reasonable value of the gate current willsatisfy the turn ON condition (i.e.∝1 + ∝2 = 1). Hence the device will not turn ON. Version 2 EE IIT, Kharagpur 8
  • 99. 4.4 Steady State Characteristics of a Thyristor4.4.1 Static output i-v characteristics of a thyristor IA VBRF + VAK - A IA K ig Ig ig1 ig2 ig3 ig4 VBRR VBRF IL Is IH VAK ig4 > ig3 > ig2 > ig1 > ig = 0 VH ig4 > ig3 > ig2 > ig1 > ig = 0 Fig. 4.3: Static output characteristics of a ThyristorThe circuit symbol in the left hand side inset defines the polarity conventions of the variablesused in this figure.With ig = 0, VAK has to increase up to forward break over voltage VBRF before significant anodecurrent starts flowing. However, at VBRF forward break over takes place and the voltage acrossthe thyristor drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK)remains almost constant at VH (1-1.5v) while the anode current is determined by the externalload.The magnitude of gate current has a very strong effect on the value of the break over voltage asshown in the figure. The right hand side figure in the inset shows a typical plot of the forwardbreak over voltage (VBRF) as a function of the gate current (Ig)After “Turn ON” the thyristor is no more affected by the gate current. Hence, any current pulse(of required magnitude) which is longer than the minimum needed for “Turn ON” is sufficient toeffect control. The minimum gate pulse width is decided by the external circuit and should belong enough to allow the anode current to rise above the latching current (IL) level. Version 2 EE IIT, Kharagpur 9
  • 100. The left hand side of Fig 4.3 shows the reverse i-v characteristics of the thyristor. Once thethyristor is ON the only way to turn it OFF is by bringing the thyristor current below holdingcurrent (IH). The gate terminal has no control over the turn OFF process. In ac circuits withresistive load this happens automatically during negative zero crossing of the supply voltage.This is called “natural commutation” or “line commutation”. However, in dc circuits somearrangement has to be made to ensure this condition. This process is called “forcedcommutation.”During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reversevoltage reaches reverse break down voltage (VBRR). At this point current starts rising sharply.Large reverse voltage and current generates excessive heat and destroys the device. If ig > 0during reverse bias condition the reverse saturation current rises as explained in the previoussection. This can be avoided by removing the gate current while the thyristor is reverse biased.The static output i-v characteristics of a thyristor depends strongly on the junction temperature asshown in Fig 4.4. VBRF IA Tj = 150° 135° 25° 75° 125° 25° 75° 125° 150° Tj VAK Tj = 125° 75° 25° 135° 150° Fig. 4.4: Effect of junction temperature (Tj) on the output i – v characteristics of a thyristor.4.4.2 Thyristor Gate CharacteristicsThe gate circuit of a thyristor behaves like a poor quality diode with high on state voltage dropand low reverse break down voltage. This characteristic usually is not unique even within thesame family of devices and shows considerable variation from device to device. Therefore,manufacturer’s data sheet provides the upper and lower limit of this characteristic as shown inFig 4.5. Version 2 EE IIT, Kharagpur 10
  • 101. Vg Vg max A E c d Rg ig • S2 E Vg Pgav ⎜Max Load line Pgm K Vg min b e h S1 Vng • f g Ig max Ig min Ig Fig. 4.5: Gate characteristics of a thyristor.Each thyristor has maximum gate voltage limit (Vgmax), gate current limit (Igmax) and maximumaverage gate power dissipation limit ( Pgav Max ) . These limits should not be exceeded in order toavoid permanent damage to the gate cathode junction. There are also minimum limits of Vg(Vgmin) and Ig (Igmin) for reliable turn on of the thyristor. A gate non triggering voltage (Vng) isalso specified by the manufacturers of thyristors. All spurious noise signals should be less thanthis voltage Vng in order to prevent unwanted turn on of the thyristor. The useful gate drive areaof a thyristor is then b c d e f g h.Referring to the gate drive circuit in the inset the equation of the load line is given by Vg = E - RgigA typical load line is shown in Fig 4.5 by the line S1 S2.The actual operating point will be some where between S1 & S2 depending on the particulardevice.For optimum utilization of the gate ratings the load line should be shifted forwards the Pgav Maxcurve without violating Vg Max or IgMax ratings. Therefore, for a dc source E c f represents theoptimum load line from which optimum values of E & Rg can be determined.It is however customary to trigger a thyristor using pulsed voltage & current. Maximum powerdissipation curves for pulsed operation (Pgm) allows higher gate current to flow which in turnreduces the turn on time of the thyristor. The value of Pgm depends on the pulse width (TON) ofthe gate current pulse. TON should be larger than the turn on time of the thyristor. For TON larger Version 2 EE IIT, Kharagpur 11
  • 102. than 100 μs, average power dissipation curve should be used. For TON less than 100 μs thefollowing relationship should be maintained. δ Pgm ≤ Pgav Max ( 4.9 ) Where δ = TON f p, f p = pulse frequency.The magnitude of the gate voltage and current required for triggering a thyristor is inverselyproportional to the junction temperature.The gate cathode junction also has a maximum reverse (i.e, gate negative with respect to thecathode) voltage specification. If there is a possibility of the reverse gate cathode voltageexceeding this limit a reverse voltage protection using diode as shown in Fig 4.6 should be used. A A Rg G E E K K (a) (b) Fig. 4.6: Gate Cathode reverse voltage protection circuit.Exercise 4.21) Fill in the blank(s) with the appropriate word(s) i. Forward break over voltage of a thyristor decreases with increase in the ________________ current. ii. Reverse ________________ voltage of a thyristor is ________________ of the gate current. iii. Reverse saturation current of a thyristor ________________ with gate current. iv. In the pulsed gate current triggering of a thyristor the gate current pulse width should be larger than the ________________ time of the device. v. To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate and the cathode must be less than the gate ________________ voltage. Version 2 EE IIT, Kharagpur 12
  • 103. Answer: (i) gate; (ii) break down, independent; (iii) increases; (iv) Turn ON; (v) non- trigger.2) A thyristor has a maximum average gate power dissipation limit of 0.2 watts. It is triggeredwith pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.4. Assuming the gatecathode voltage drop to be 1 volt. Find out the allowable peak gate current magnitude.Answer: On period of the gate current pulse is 0.4 TON = δ TS = δ = sec = 40 μs < 100 μs. fs 10 4Therefore, pulsed gate power dissipation limit Pgm can be used. From Equation 4.9 δ Pgm ≤ Pgav ( Max ) 0.2 or Pgm ≤ watts = .5watts δ .5But Pgm = Ig Vg; Vg = 1V ∴ I g Max = = 0.5Amps. 14.5 Thyristor ratingsSome useful specifications of a thyristor related to its steady state characteristics as found in atypical “manufacturer’s data sheet” will be discussed in this section.4.5.1 Voltage ratingsPeak Working Forward OFF state voltage (VDWM): It specifics the maximum forward (i.e,anode positive with respect to the cathode) blocking state voltage that a thyristor can withstandduring working. It is useful for calculating the maximum RMS voltage of the ac network inwhich the thyristor can be used. A margin for 10% increase in the ac network voltage should beconsidered during calculation.Peak repetitive off state forward voltage (VDRM): It refers to the peak forward transientvoltage that a thyristor can block repeatedly in the OFF state. This rating is specified at amaximum allowable junction temperature with gate circuit open or with a specified biasingresistance between gate and cathode. This type of repetitive transient voltage may appear acrossa thyristor due to “commutation” of other thyristors or diodes in a converter circuit.Peak non-repetitive off state forward voltage (VDSM): It refers to the allowable peak value ofthe forward transient voltage that does not repeat. This type of over voltage may be caused due toswitching operation (i.e, circuit breaker opening or closing or lightning surge) in a supplynetwork. Its value is about 130% of VDRM. However, VDSM is less than the forward break overvoltage VBRF. Version 2 EE IIT, Kharagpur 13
  • 104. Peak working reverse voltage (VDWM): It is the maximum reverse voltage (i.e, anode negativewith respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to thepeak negative value of the ac supply voltage.Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that mayoccur repeatedly during reverse bias condition of the thyristor at the maximum junctiontemperature.Peak non-repetitive reverse voltage (VRSM): It represents the peak value of the reversetransient voltage that does not repeat. Its value is about 130% of VRRM. However, VRSM is lessthan reverse break down voltage VBRR.Fig 4.7 shows different thyristor voltage ratings on a comparative scale. IA VBRR VRSM VRRM VRWM VAK VDWM VDRM VDSM VBRF Fig. 4.7: Voltage ratings of a thyristor.4.5.2 Current ratingsMaximum RMS current (Irms): Heating of the resistive elements of a thyristor such as metallicjoints, leads and interfaces depends on the forward RMS current Irms. RMS current rating is usedas an upper limit for dc as well as pulsed current waveforms. This limit should not be exceededon a continuous basis.Maximum average current (Iav): It is the maximum allowable average value of the forwardcurrent such that i. Peak junction temperature is not exceeded ii. RMS current limit is not exceededManufacturers usually provide the “forward average current derating characteristics” whichshows Iav as a function of the case temperature (Tc ) with the current conduction angle φ as aparameter. The current wave form is assumed to be formed from a half cycle sine wave of powerfrequency as shown in Fig 4.8. Version 2 EE IIT, Kharagpur 14
  • 105. Iav φ = 180° Amps 120 φ = 120° 100 80 φ = 60° φ 60 φ = 30° 40 20 0 ∫∫ 60° 80° 100° 120° 140° TC (°C) Fig. 4.8: Average forward current derating characteristicsMaximum Surge current (ISM): It specifies the maximum allowable non repetitive current thedevice can withstand. The device is assumed to be operating under rated blocking voltage,forward current and junction temperation before the surge current occurs. Following the surgethe device should be disconnected from the circuit and allowed to cool down. Surge currents areassumed to be sine waves of power frequency with a minimum duration of ½ cycles.Manufacturers provide at least three different surge current ratings for different durations.For example I sM = 3000 A for 1 cycle 2 I sM = 2100 A for 3 cycles I sM = 1800 A for 5 cyclesAlternatively a plot of IsM vs. applicable cycle numbers may also be provided.Maximum Squared Current integral (∫i2dt): This rating in terms of A2S is a measure of theenergy the device can absorb for a short time (less than one half cycle of power frequency). Thisrating is used in the choice of the protective fuse connected in series with the device.Latching Current (IL): After Turn ON the gate pulse must be maintained until the anodecurrent reaches this level. Otherwise, upon removal of gate pulse, the device will turn off.Holding Current (IH): The anode current must be reduced below this value to turn off thethyristor.Maximum Forward voltage drop (VF): Usually specified as a function of the instantaneousforward current at a given junction temperature. Version 2 EE IIT, Kharagpur 15
  • 106. Average power dissipation Pav): Specified as a function of the average forward current (Iav) fordifferent conduction angles as shown in the figure 4.9. The current wave form is assumed to behalf cycle sine wave (or square wave) for power frequency. Pav φ = 180° 90° 60° 30° iF ωt φ Iav Fig. 4.9: Average power dissipation vs average forward current in a thyristor.In the above diagram 1 φ I av = 2π ∫o F i dθ ( 4.10 ) 1 φ Pav = 2π ∫o F F v i dθ ( 4.11)4.5.3 Gate SpecificationsGate current to trigger (IGT): Minimum value of the gate current below which reliable turn onof the thyristor can not be guaranteed. Usually specified at a given forward break over voltage.Gate voltage to trigger (VGT): Minimum value of the gate cathode forward voltage belowwhich reliable turn on of the thyristor can not be guaranteed. It is specified at the same breakover voltage as IGT.Non triggering gate voltage (VGNT): Maximum value of the gate-cathode voltage below whichthe thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuitmust be below this level.Peak reverse gate voltage (VGRM): Maximum reverse voltage that can appear between the gateand the cathode terminals without damaging the junction. Version 2 EE IIT, Kharagpur 16
  • 107. Average Gate Power dissipation (PGAR): Average power dissipated in the gate-cathodejunction should not exceed this value for gate current pulses wider than 100 μs.Peak forward gate current (IGRM): The forward gate current should not exceed this limit evenon instantaneous basis.Exercise 4.31) Fill in the blank(s) with the appropriate word(s) i. Peak non-repetitive over voltage may appear across a thyristor due to ________________ or ________________ surges in a supply network. ii. VRSM rating of a thyristor is greater than the ________________ rating but less than the ________________ rating. iii. Maximum average current a thristor can carry depends on the ________________ of the thyristor and the ________________ of the current wave form. iv. The ISM rating of a thyristor applies to current waveforms of duration ________________ than half cycle of the power frequency where as the ∫i2dt rating applies to current durations ________________ than half cycle of the power frequency. v. The gate non-trigger voltage specification of a thyristor is useful for avoiding unwanted turn on of the thyristor due to ________________ voltage signals at the gate.Answer: (i) switching, lightning; (ii) VRRM, VBRR; (iii) case temperature, conduction angle; (iv) greater, less; (v) noise2. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180°.Find the corresponding rating for Φ = 60°. Assume the current waveforms to be half cycle sinewave.Answer: The form factor of half cycle sine waves for a conduction angle φ is given by IF.F = RMS = 1 2π φ ∫ Sin θ dθ o 2 = ( π φ - 1 Sin 2φ 2 ) Iav 1 φ 1- Cos φ 2π ∫ Sinθ dθ oFor φ = 180°, F.F = π 2∴RMS current rating of the thyristor = 1200 × π = 1885 Amps. 2For φ = 60°, F.F = 2 π ⎛ π - 3 ⎞ = 2.778 ⎜ 3 ⎝ 4⎟⎠Since RMS current rating should not exceeded Version 2 EE IIT, Kharagpur 17
  • 108. 1200 × πMaximum Iav for φ = 60° = = 679.00 Amps. 4 π ⎛π - ⎜ 3 3 ⎞ ⎝ 4⎟ ⎠4.6 Switching Characteristics of a ThyristorDuring Turn on and Turn off process a thyristor is subjected to different voltages across it anddifferent currents through it. The time variations of the voltage across a thyristor and the currentthrough it during Turn on and Turn off constitute the switching characteristics of a thyristor.4.6.1 Turn on Switching CharacteristicsA forward biased thyristor is turned on by applying a positive gate voltage between the gate andcathode as shown in Fig 4.10. + -ig vAK iA ig t Vi RiA 0.9 ION ION 0.1 ION Firing angle t α VivAK vAK iA 0.9 VON VON 0.1 VON Expanded scale t tON td tr tp Fig. 4.10: Turn on characteristics of a thyristor.Fig 4.10 shows the waveforms of the gate current (ig), anode current (iA) and anode cathodevoltage (VAK) in an expanded time scale during Turn on. The reference circuit and the associatedwaveforms are shown in the inset. The total switching period being much smaller compared tothe cycle time, iA and VAK before and after switching will appear flat.As shown in Fig 4.10 there is a transition time “tON” from forward off state to forward on state.This transition time is called the thyristor turn of time and can be divided into three separateintervals namely, (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). These times areshown in Fig 4.10 for a resistive load. Version 2 EE IIT, Kharagpur 18
  • 109. Delay time (td): After switching on the gate current the thyristor will start to conduct over theportion of the cathode which is closest to the gate. This conducting area starts spreading at afinite speed until the entire cathode region becomes conductive. Time taken by this processconstitute the turn on delay time of a thyristor. It is measured from the instant of application ofthe gate current to the instant when the anode current rises to 10% of its final value (or VAK fallsto 90% of its initial value). Typical value of “td” is a few micro seconds.Rise time (tr): For a resistive load, “rise time” is the time taken by the anode current to rise from10% of its final value to 90% of its final value. At the same time the voltage VAK falls from 90%of its initial value to 10% of its initial value. However, current rise and voltage fallcharacteristics are strongly influenced by the type of the load. For inductive load the voltage fallsfaster than the current. While for a capacitive load VAK falls rapidly in the beginning. However,as the current increases, rate of change of anode voltage substantially decreases.If the anode current rises too fast it tends to remain confined in a small area. This can give rise tolocal “hot spots” and damage the device. Therefore, it is necessary to limit the rate of rise of the ⎛ di ⎞ON state current ⎜ A ⎟ by using an inductor in series with the device. Usual values of maximum ⎝ dt ⎠allowable di A is in the range of 20-200 A/μs. dtSpread time (tp): It is the time taken by the anode current to rise from 90% of its final value to100%. During this time conduction spreads over the entire cross section of the cathode of thethyristor. The spreading interval depends on the area of the cathode and on the gate structure ofthe thyristor.4.6.2 Turn off Switching CharacteristicsOnce the thyristor is on, and its anode current is above the latching current level the gate losescontrol. It can be turned off only by reducing the anode current below holding current. The turnoff time tq of a thyristor is defined as the time between the instant anode current becomes zeroand the instant the thyristor regains forward blocking capability. If forward voltage is appliedacross the device during this period the thyristor turns on again.During turn off time, excess minority carriers from all the four layers of the thyristor must beremoved. Accordingly tq is divided in to two intervals, the reverse recovery time (trr) and the gaterecovery time (tqr). Fig 4.11 shows the variation of anode current and anode cathode voltage withtime during turn off operation on an expanded scale. Version 2 EE IIT, Kharagpur 19
  • 110. vAKiA iA di A dt ig Vi t Qrr IrrvAK vi iA t t vi Expanded Vrr scale trr tgr tq Fig. 4.11: Turn off characteristics of a thyristor.The anode current becomes zero at time t1 and starts growing in the negative direction with thesame di A till time t2. This negative current removes excess carriers from junctions J1 & J3. At dttime t2 excess carriers densities at these junctions are not sufficient to maintain the reversecurrent and the anode current starts decreasing. The value of the anode current at time t2 is calledthe reverse recovery current (Irr). The reverse anode current reduces to the level of reversesaturation current by t3. Total charge removed from the junctions between t1 & t3 is called thereverse recovery charge (Qrr). Fast decaying reverse current during the interval t2 t3 coupled withthe di limiting inductor may cause a large reverse voltage spike (Vrr) to appear across the dtdevice. This voltage must be limited below the VRRM rating of the device. Up to time t2 thevoltage across the device (VAK) does not change substantially from its on state value. However,after the reverse recovery time, the thyristor regains reverse blocking capacity and VAK startsfollowing supply voltage vi. At the end of the reverse recovery period (trr) trapped charges stillexist at the junction J2 which prevents the device from blocking forward voltage just after trr.These trapped charges are removed only by the process of recombination. The time taken for thisrecombination process to complete (between t3 & t4) is called the gate recovery time (tgr). Thetime interval tq = trr + tgr is called “device turn off time” of the thyristor.No forward voltage should appear across the device before the time tq to avoid its inadvertentturn on. A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltageis applied across the device. tc is called the “circuit turn off time”. Version 2 EE IIT, Kharagpur 20
  • 111. The reverse recovery charge Qrr is a function of the peak forward current before turn off and its dirate of decrease A . Manufacturers usually provide plots of Qrr as a function of di A for dt dtdifferent values of peak forward current. They also provide the value of the reverse recoverycurrent Irr for a given IA and di A . Alternatively Irr can be evaluated from the given Qrr dtcharacteristics following similar relationships as in the case of a diode.As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends onthe construction of the thyristor. In normal recovery “converter grade” thyristor they are almostequal for a specified forward current and reverse recovery current. However, in a fast recovery“inverter grade” thyristor the interval t2 t3 is negligible compared to the interval t1 t2. This helpsreduce the total turn off time tq of the thyristor (and hence allow them to operate at higherswitching frequency). However, large voltage spike due to this “snappy recovery” will appearacross the device after the device turns off. Typical turn off times of converter and invertergrade thyristors are in the range of 50-100 μs and 5-50 μs respectively.As has been mentioned in the introduction thyristor is the device of choice at the very highestpower levels. At these power levels (several hundreds of megawatts) reliability of the thyristorpower converter is of prime importance. Therefore, suitable protection arrangement must bemade against possible overvoltage, overcurrent and unintended turn on for each thyristor. At thehighest power level (HVDC transmission system) thyristor converters operate from networkvoltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo ampsof current. They usually employ a large number of thyristors connected in series parallelcombination. For maximum utilization of the device capacity it is important that each device inthis series parallel combination share the blocking voltage and on state current equally. Specialequalizing circuits are used for this purpose.Exercise 4.41) Fill in the blank(s) with the appropriate word(s) i. A thyristor is turned on by applying a ________________ gate current pulse when it is ________________ biased. ii. Total turn on time of a thyristor can be divided into ________________ time ________________ time and ________________ time. iii. During rise time the rate of rise of anode current should be limited to avoid creating local ________________. iv. A thyristor can be turned off by bringing its anode current below ________________ current and applying a reverse voltage across the device for duration larger than the ________________ time of the device. v. Reverse recovery charge of a thyristor depends on the ________________ of the forward current just before turn off and its ________________. Version 2 EE IIT, Kharagpur 21
  • 112. vi. Inverter grade thyristors have ________________ turn off time compared to a converter grade thyristor.Answer: (i) positive, forward; (ii) delay, rise, spread; (iii) hot spots (iv) holding, turn off; (v) magnitude, rate of decrease (vi) faster2. With reference to Fig 4.10 find expressions for (i) turn on power loss and (ii) conductionpower loss of the thyristor as a function of the firing angle ∝. Neglect turn on delay time andspread time and assume linear variation of voltage and current during turn on period. Alsoassume constant on state voltage VH across the thyristor.Answer: (i) For a firing angle ∝ the forward bias voltage across the thyristor just before turn onis VON = 2Vi Sin ∝ ; Vi = RMS value of supply voltage. Current after the thyristor turns on for a resistive load is VON Vi I ON = = 2 Sin ∝ R RNeglecting delay and spread time and assuming linear variation of voltage and current duringturn on Vak = 2 Vi Sin ∝ ⎛1 - t ⎜ ⎞ . where V has been neglected. ⎝ t ON ⎟ ⎠ H 2 Vi Sin ∝ t ia = R t ON∴ Total switching energy loss t ON 2Vi 2 t ON ⎛1 - t ⎞ t E ON = ∫ v ak i a dt =Sin 2 ∝ ∫ ⎜ dt o R o ⎝ t ON ⎟ t ON ⎠ 2Vi 2 t ⎛ 2⎞ Vi 2 = Sin 2 ∝ ON ⎜1 - ⎟ = Sin 2 ∝ t ON R 2 ⎝ 3⎠ 3REON occurs once every cycle. If the supply frequency is f then average turn on power loss isgiven by. Vi 2 PON = E ON f = Sin 2 ∝ t ON f 3R(ii) If the firing angle is ∝ the thyristor conducts for π-∝ angle. Instantaneous current through thedevice during this period is 2 Vi Sin ωt ia = R ∝ <ωt≤ π RWhere tON & VH have been neglected for simplicity.∴ total conduction energy loss over one cycle is Version 2 EE IIT, Kharagpur 22
  • 113. πω 1 π 2 Vi 2 Vi VH E C = ∫ ∝ Vak i a dt = ω ∫α H V R Sinθ dθ = ωR (1 + Cos ∝ ) ω 2 Vi VH∴ Average conduction power loss = PC = E cf = 2πR (1 + Cos ∝ ) Fuse i1 Vi if 220 V 50 HZ3. In the ideal single phase fully controlled converter T1 & T2 are fired at a firing angle ∝ afterthe positive going zero crossing of Vi while T3 & T4 are fired ∝ angle after the negative goingzero crossing of Vi, If all thyristors have a turn off time of 100 μs, find out maximum allowablevalue of ∝.Answer: As T1 & T2 are fired at an angle ∝ after positive going zero crossing of Vi, T3 & T4 aresubjected to a negative voltage of –Vi. Since this voltage remain negative for a duration (π-∝)angle (after which –Vi becomes positive) for safe commutation( π - Max) ≥ ωt off ∴ ∝ Max = 178.2 . 04.7 The TriacThe Triac is a member of the thyristor family. But unlike a thyristor which conducts only in onedirection (from anode to cathode) a triac can conduct in both directions. Thus a triac is similar totwo back to back (anti parallel) connected thyristosr but with only three terminals. As in the caseof a thyristor, the conduction of a triac is initiated by injecting a current pulse into the gateterminal. The gate looses control over conduction once the triac is turned on. The triac turns offonly when the current through the main terminals become zero. Therefore, a triac can becategorized as a minority carrier, a bidirectional semi-controlled device. They are extensivelyused in residential lamp dimmers, heater control and for speed control of small single phaseseries and induction motors.4.7.1 Construction and operating principleFig. 4.12 (a) and (b) show the circuit symbol and schematic cross section of a triac respective. Asthe Triac can conduct in both the directions the terms “anode” and “cathode” are not used forTriacs. The three terminals are marked as MT1 (Main Terminal 1), MT2 (Main Terminal 2) andthe gate by G. As shown in Fig 4.12 (b) the gate terminal is near MT1 and is connected to both Version 2 EE IIT, Kharagpur 23
  • 114. N3 and P2 regions by metallic contact. Similarly MT1 is connected to N2 and P2 regions whileMT2 is connected to N4 and P1 regions. MT1 N2 MT2 N2 P2 G P2 N3 N3 P2 N1 G P1 N1 MT1 N4 P1 (a) (b) MT2 Fig. 4.12: Circuit symbol and schematic construction of a Triac (a) Circuit symbol (b) Schematic construction.Since a Triac is a bidirectional device and can have its terminals at various combinations ofpositive and negative voltages, there are four possible electrode potential combinations as givenbelow 1. MT2 positive with respect to MT1, G positive with respect to MT1 2. MT2 positive with respect to MT1, G negative with respect to MT1 3. MT2 negative with respect to MT1, G negative with respect to MT1 4. MT2 negative with respect to MT1, G positive with respect to MT1The triggering sensitivity is highest with the combinations 1 and 3 and are generally used.However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2and 3 are used. Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conductionmechanism of a triac in trigger modes 1 & 3 respectively. Version 2 EE IIT, Kharagpur 24
  • 115. IG IG G MT1 MT1 (-) (+) IG N2 N3 IG P2 P2 N1 N1 P1 P1 N4 MT2 MT2 (+) (-) (a) (b) Fig. 4.13: Conduction mechanism of a triac in trigger modes 1 and 3 (a) Mode – 1 , (b) Mode – 3 .In trigger mode-1 the gate current flows mainly through the P2 N2 junction like an ordinarythyristor. When the gate current has injected sufficient charge into P2 layer the triac startsconducting through the P1 N1 P2 N2 layers like an ordinary thyristor.In the trigger mode-3 the gate current Ig forward biases the P2 P3 junction and a large number ofelectrons are introduced in the P2 region by N3. Finally the structure P2 N1 P1 N4 turns oncompletely. Version 2 EE IIT, Kharagpur 25
  • 116. 4.7.2 Steady State Output Characteristics and Ratings of a Triac I Ig3 > Ig2 > Ig1 > Ig = 0 -VBO VBO V Ig = 0 -Ig3 < Ig2 < Ig1 Fig. 4.14: Steady state V – I characteristics of a TriacFrom a functional point of view a triac is similar to two thyristors connected in anti parallel.Therefore, it is expected that the V-I characteristics of Triac in the 1st and 3rd quadrant of the V-Iplane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with nosignal to the gate the triac will block both half cycle of the applied ac voltage provided its peakvalue is lower than the break over voltage (VBO) of the device. However, the turning on of thetriac can be controlled by applying the gate trigger pulse at the desired instance. Mode-1triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant.As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current).However, in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interactwith each other in the structure of the triac. Therefore, the voltage, current and frequency ratingsof triacs are considerably lower than thyristors. At present triacs with voltage and current ratingsof 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop comparedto a thyristor. Manufacturers usually specify characteristics curves relating rms device currentand maximum allowable case temperature as shown in Fig 4.15. Curves relating the devicedissipation and RMS on state current are also provided for different conduction angles. Version 2 EE IIT, Kharagpur 26
  • 117. A Bidirectional ON state current 200 150 100 (RMS) For all conduction angles 50 0 °C 20° 40° 60° 80° 100° 120° Maximum allowable case temperature (TC) Fig. 4.15: RMS ON state current Vs maximum case temperature.4.7.3 Triac Switching and gate trigger circuitUnlike a thyristor a triac gets limited time to turn off due to bidirectional conduction. As a resultthe triacs are operated only at power frequency. Switching characteristics of a triac is similar tothat of a thyristor. However, turn off of a triac is extremely sensitive to temperature variation andmay not turn off at all if the junction temperature exceeds certain limit. Problem may arise whena triac is used to control a lagging power factor load. At the current zero instant (when the triacturns off) a reverse voltage will appear across the triac since the supply voltage is negative at thatinstant. The rate of rise of this voltage is restricted by the triac junction capacitance only. Theresulting dv may turn on the triac again. Similar problem occurs when a triac is used to dtcontrol the power to a resistive element which has a very low resistance before normal workingcondition is reached. If such a load (e.g. incandescent filament lamp) is switch on at full supplyvoltage very large junction capacitance charging current will turn ON the device. To preventsuch condition an R-C snubber is generally used across a triac.The triac should be triggered carefully to ensure safe operation. For phase control application,the triac is switched on and off in synchronism with the mains supply so that only a part of eachhalf cycle is applied across the load. To ensure ‘clean turn ON’ the trigger signal must riserapidly to provide the necessary charge. A rise time of about 1 μs will be desirable. Such a triacgate triggering circuit using a “diac” and an R-C timing network is shown in Fig 4.16. Version 2 EE IIT, Kharagpur 27
  • 118. LOAD R1 R D1 R2 V1 C1 C Fig. 4.16: Triac triggering circuit using a diac.In this circuit as Vi increases voltage across C1 increases due to current flowing through load, R1,R2 and C1. The voltage drop across diac D1 increases until it reaches its break over point. As D1conducts a large current pulse is injected into the gate of the triac. By varying R2 the firing canbe controlled from zero to virtually 100%.Exercise 4.51) Fill in the blank(s) with the appropriate word(s) i. A Triac is a ________________ minority carrier device ii. A Triac behaves like two ________________ connected thyristors. iii. The gate sensitivity of a triac is maximum when the gate is ________________ with respect to MT1 while MT2 is positive with respect to MT1 or the gate is ________________ with respect to MT1 while MT2 is negative with respect to MT1 iv. A Triac operates either in the ________________ or the ________________ quadrant of the i-v characteristics. v. In the ________________ quadrant the triac is fired with ________________ gate current while in the ________________ quadrant the gate current should be ________________. vi. The maximum possible voltage and current rating of a Triac is considerably ________________ compared to thyristor due to ________________ of the two current carrying paths inside the structure of the triac. Version 2 EE IIT, Kharagpur 28
  • 119. vii. To avoid unwanted turn on of a triac due to large dv ________________ are used dt across triacs.viii. For “clean turn ON” of a triac the ________________ of the gate current pulse should be as ________________ as possible.Answer: (i) bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first, positive, third, negative (vi) lower, interaction; (vii) R-C shubbers; (viii) rise time, small. Version 2 EE IIT, Kharagpur 29
  • 120. References 1. Dr. P.C. Sen, “Power Electronics”; Tata McGrow Hill Publishing Company Limited; New Delhi. 2. Dr. P.S. Bimbhra, “Power Electronics” Khanna Publishers Version 2 EE IIT, Kharagpur 30
  • 121. Lesson Summary • Thyristor is a four layer, three terminal, minority carrier, semi-controlled device. • The three terminals of a thyristor are called the anode, the cathode and the gate. • A thyristor can be turned on by increasing the voltage of the anode with respect to the cathode beyond a specified voltage called the forward break over voltage. • A thyristor can also be turned on by injecting a current pulse into the gate terminal when the anode voltage is positive with respect to the cathode. This is called gate triggering. • A thyristor can block voltage of both polarity but conducts current only from anode to cathode. • After a thyristor turns on the gate looses control. It can be turned off only by bringing the anode current below holding current. • After turn on the voltage across the thyristor drops to a very low value (around 1 volt). In the reverse direction a thyristor blocks voltage up to reverse break down voltage. • A thyristor has a very low conduction voltage drop but large switching times. For this reason thyristors are preferred for high power, low frequency line commutated application. • A thyristor is turned off by bringing the anode current below holding current and simultaneously applying a negative voltage (cathode positive with respect to anode) for a minimum time called “turn off time”. • A triac is functionally equivalent to two anti parallel connected thyristors. It can block voltages in both directions and conduct current in both directions. • A triac has three terminals like a thyristor. It can be turned on in either half cycle by either a positive on a negative current pulse at the gate terminal. • Triacs are extensively used at power frequency ac load (eg heater, light, motors) control applications. Version 2 EE IIT, Kharagpur 31
  • 122. Practice Problems and Answers Version 2 EE IIT, Kharagpur 32
  • 123. 1. Explain the effect of increasing the magnitude of the gate current and junction temperature on (i) forward and reverse break down voltages, (ii) forward and reverse leakage currents. Th 15 V R • • N1 N2 iB2. The thyristor Th is triggered using the pulse transformer shown in figure. The pulse transformer operates at 10 KHZ with a duty cycle of 40%. The thyristor has maximum average gate power dissipation limit of 0.5 watts and a maximum allow able gate voltage limit of 10 volts. Assuming ideal pulse transformer, find out the turns ratio N1/N2 and the value of R. Fuse i1 Vi if 220 V 50 HZ3. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. The thyristors are fired at a firing angle ∝ = 0° when motor runs at rated speed. The motor has on armature resistance of 0.2 Ω and negligible armature inductance. Find out the peak surge current rating of the thyristors such that they are not damaged due to sudden loss of field excitation to the motor. The protective fuse in series with the motor is designed to disconnect the motor within 1 cycle of fault. Find out the ∫ i 2 dt rating of the 2 thyristors.4. Why is it necessary to maximize the peripheral contact area of the gate and the cathode regions? A thyristor used to control the voltage applied to a load resistance from a 220v, Version 2 EE IIT, Kharagpur 33
  • 124. di a 50HZ single phase ac supply has a maximum rating of 50 A / μs. Find out the dt di a value of the limiting inductor to be connected in series with the load resistance. dt THM - 200V C + THA 20 A 200V5. In a voltage commutated dc – dc thyristor chopper the main thyristor THM is commutated by connecting a pre-charged capacitor directly across it through the auxiliary thyristor THA as shown in the figure. The main thyristor THM has a turn off time off 50μs and maximum dv rating of 500v/ μs. Find out a suitable value of C for safe dt commutation of THM. Version 2 EE IIT, Kharagpur 34
  • 125. Answers to Practice Problems Version 2 EE IIT, Kharagpur 35
  • 126. 1. i. Forward break down voltage reduces with increasing gate current. It increases with junction temperature up to certain value of the junction temperature and then falls rapidly with any further increase in temperature. Reverse break down voltage is independent of the gate current magnitude but decreases with increasing junction temperature. ii. Forward leakage current is independent of the gate current magnitude but increases with junction temperature. Reverse leakage current increases with both the junction temperature and the magnitude of the gate current. THM - 200V C + THA 20 A 200V2. Figure shows the equivalent gate drive circuit of the thyristor. For this circuit one can write E = R i g + Vg OR Vg = E - R i gThe diode D clamps the gate voltage to zero when E goes negative.Now for ig = O, Vg = E. Since Vg Max = 10 v E = 10 v N2 N2But E = 15 ∴ = 15 = 1.5 N1 N1 10Gate pulse width = 0.4 × 10-4 Sec = 40μs. <100μs.∴ instantaneous gate power dissipation limit can be used. Pav 0.2∴ Vg i g Max == = 0.5 watts δ Max 0.4For maximum utilization of the gate power dissipation limit the gate load line ie Vg = E – igR =10 – igR should be tangent to the maximum power dissipation curve Vg ig = 0.5Let the operating Vg and ig be Vgo & igo ∴ Vgo = 10 - i go R Vgo i go = 0.5 ∴ i go 2 R - 10 i go + 0.5 = 0 Version 2 EE IIT, Kharagpur 36
  • 127. Since Vg = 10 – ig R is tangent to Vg ig = 0.5 at Vgo, igo.Slope of the tangent of Vgig = 0.5 at (Vgo, igo) = -R dv g - vg v ∴ -R = = = - go di g ( vgo,igo ) i g ( vgo,igo ) i go v go v i 0.5 ∴R = = go 2go = 2 i go i go i go 0.5 ∴ i go 2 × - 10i go + 0.5 = 0 or 10i go = 1 or i go = 0.1 i go 2 0.5 ∴ R = 0.5 2 = = 50 Ω i go .01 Back emf. Va t ia (normal) t ia (with field loss) t3. Figure shows the armature voltage (firm line) and armature current of the motor under normaloperating condition at rated speed. If there is a sudden loss of field excitation back emf willbecome zero and armature current will be limited solely by the armature resistance. 220 2The peak magnitude of the fault current will be = 1556(Amps) . .2It the thyristors have to survive this fault at least for 1 cycle (after which the fuse blows) IsM > 21556 Amps.The fuse blows within 1 cycle of the fault occurring. Therefore the thyristors must withstand 2the fault for at least 1 cycle. 2 2Therefore, the i t rating of the thyristor should be Version 2 EE IIT, Kharagpur 37
  • 128. 10-2 ∫ i dt = ∫ (1556 Sin 100 π t ) 2 2 0 (1556 ) 2 10-2 = 2 ∫ 0 [1 - Cos 200 π t ] dt = 1 × 10 -2 (1556 ) = 1.21× 10 4 A 2 Sec 2 24. At the beginning of the turn on process the thyristor starts conducting through the areaadjacent to the gate. This area spreads at a finite speed. However, if rate of increase of anodecurrent is lager than the rate of increase of the current conduction are, the current densityincreases with time. This may lead to thyristor failure due to excessive local heating. However, ifthe contact area between the gate and the cathode is large a thyristor will be able to handle a direlatively large a without being damaged. dt di aThe maximum will occur when the thyristor is triggered at ∝ = 90°. Then dt di a L = 2 × 220 Sin 90 0 dt di aSince = 50 × 10 6 A Sec dt Max 2 × 220 L = = 6.22 × 10 -6 H = 6.22 μH min ⎛ di a ⎞ ⎜ dt ⎟ ⎝ ⎠ Max VC toff 200 V vTHM dv / dt t iC 20 Amps. t Version 2 EE IIT, Kharagpur 38
  • 129. 5. As soon as THA is turned on the load current transfer from THM to C. the voltage acrossTHM is the negative of the capacitance voltage. Figure shows the waveforms of voltage acrossthe capacitor (vc), voltage across the main thyristor (VTHM) and the capacitor current ic. From dv ifigure = c dt c dvNow ic = 20 Amps & = 500 v μs dt Max ic 20∴ C = = 6 = 4 × 10 -8 F = 0.04 μF Min dv 500×10 dt MaxThe circuit turn off time is the time taken by the capacitor voltage to reach zero from an initialvalue of 200v. This time must be greater than the turn off time of the device. dv cNow C = i c = 20 dt 20 × Δt ∴ Δv c = Δv = 200 - 0 = 200 c Δt = t off 20 × 50 × 10 -6 ∴ 200 = C 20 × 50 × 10 -6 ∴C = = 5 μF 200For safe commutation of THM the higher value of C must the chosen ∴ the required value of C = 5 μF. Version 2 EE IIT, Kharagpur 39
  • 130. Module 1Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1
  • 131. Lesson 5Gate Turn Off Thyristor (GTO) Version 2 EE IIT, Kharagpur 2
  • 132. Instructional objectiveOn completion the student will be able to • Differentiate between the constructional features of a GTO and a Thyristor. • Explain the turn off mechanism of a GTO. • Differentiate between the steady state output and gate characteristics of a GTO and a thyristor. • Draw and explain the switching characteristics of a GTO. • Draw the block diagram of a GTO gate drive unit and explain the functions of different blocks. • Interpret the manufacturer’s data sheet of a GTO. Version 2 EE IIT, Kharagpur 3
  • 133. IntroductionThe thyristor has reigned supreme for well over two decades in the power electronics industryand continues to do so at the very highest level of power. It, however, has always suffered fromthe disadvantage of being a semi-controlled device. Although it could be turned on by applying agate pulse but to turn it off the main current had to be interrupted. This proved to be particularlyinconvenient in DC to AC and DC to DC conversion circuits, where the main current does notnaturally becomes zero. A bulky and expensive “commutation circuit” had to be used to ensureproper turning off of the thyristor. The switching speed of the device was also comparativelyslow even with fast inverter grade thyristor. The development of the Gate Turn off thyristor(GTO) has addressed these disadvantages of a thyristor to a large extent. Although it has made arather late entry (1973) into the thyristor family the technology has matured quickly to producedevice comparable in rating (5000V, 4000Amp) with the largest available thyristor.Consequently it has replaced the forced commutated inverter grade thyristor in all DC to AC andDC to DC converter circuits.Like thyristor, the GTO is a current controlled minority carrier (i.e. bipolar) device. GTOs differfrom conventional thyristor in that, they are designed to turn off when a negative current is sentthrough the gate, thereby causing a reversal of the gate current. A relatively high gate current isneed to turn off the device with typical turn off gains in the range of 4-5. During conduction, onthe other hand, the device behaves just like a thyristor with very low ON state voltage drop.Several different varieties of GTOs have been manufactured. Devices with reverse blockingcapability equal to their forward voltage ratings are called “symmetric GTOs”. However, themost poplar variety of the GTO available in the market today has no appreciable reverse voltage(20-25v) blocking capacity. These are called “Asymmetric GTOs”. Reverse conducting GTOs(RC-GTO) constitute the third family of GTOs. Here, a GTO is integrated with an anti-parallelfreewheeling diode on to the same silicon wafer. This lesson will describe the construction,operating principle and characteristic of “Asymmetric GTOs” only.5.2 Constructional Features of a GTOFig 5.1 shows the circuit symbol and two different schematic cross section of a GTO. Version 2 EE IIT, Kharagpur 4
  • 134. Anode A Contact p+ n+ p+ n+ p+ p+ J1 n Anode Short. Buffer n Layer n- J2 p J3 pG K n+ n+ n+ n+ (a) G G C C (b) (c) Fig. 5.1: Circuit symbol and schematic cross section of a GTO (a) Circuit Symbol, (b) Anode shorted GTO structure, (c) Buffer layer GTO structure.Like a thyristor, a GTO is also a four layer three junction p-n-p-n device. In order to obtain highemitter efficiency at the cathode end, the n+ cathode layer is highly doped. Consequently, thebreak down voltage of the function J3 is low (typically 20-40V). The p type gate region hasconflicting doping requirement. To maintain good emitter efficiency the doping level of thislayer should be low, on the other hand, from the point of view of good turn off properties,resistively of this layer should be as low as possible requiring the doping level of this region tobe high. Therefore, the doping level of this layer is highly graded. Additionally, in order tooptimize current turn off capability, the gate cathode junction must be highly interdigitated. A3000 Amp GTO may be composed of upto 3000 individual cathode segments which are aaccessed via a common contact. The most popular design features multiple segments arranged inconcentric rings around the device center.The maximum forward blocking voltage of the device is determined by the doping level and thethickness of the n type base region next. In order to block several kv of forward voltage thedoping level of this layer is kept relatively low while its thickness is made considerably higher (afew hundred microns). Byond the maximum allowable forward voltage either the electric field atthe main junction (J2) exceeds a critical value (avalanche break down) or the n base fullydepletes, allowing its electric field to touch the anode emitter (punch through).The junction between the n base and p+ anode (J1) is called the “anode junction”. For good turnon properties the efficiency of this anode junction should be as high as possible requiring aheavily doped p+ anode region. However, turn off capability of such a GTO will be poor withvery low maximum turn off current and high losses. There are two basic approaches to solve thisproblem.In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They makecontact with the same anode metallic contact. Therefore, electrons traveling through the base candirectly reach the anode metal contact without causing hole injection from the p+ anode. This isthe classic “anode shorted GTO structure” as shown in Fig 5.1 (b). Due to presence of these“anode shorts” the reverse voltage blocking capacity of GTO reduces to the reverse break down Version 2 EE IIT, Kharagpur 5
  • 135. voltage of junction J3 (20-40 volts maximum). In addition a large number of “anode shorts”reduces the efficiency of the anode junction and degrades the turn on performance of the device.Therefore, the density of the “anode shorts” are to be chosen by a careful compromise betweenthe turn on and turn off performance.In the other method, a moderately doped n type buffer layer is juxtaposed between the n- typebase and the anode. As in the case of a power diode and BJT this relatively high density bufferlayer changes the shape of the electric field pattern in the n- base region from triangular totrapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer ina conventional “anode shorted” GTO structure would have increased the efficiency of the anodeshorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thinp+ type layer is introduce as the anode. The design of this layer is such that electrons have a highprobability of crossing this layer without stimulating hole injection. This is called the“Transparent emitter structure” and is shown in Fig 5.1 (c).Exercise 5.1Fill in the blank(s) with the appropriate word(s) i. A GTO is a _______________ controlled _______________ carrier device. ii. A GTO has _______________ layers and _______________ terminals. iii. A GTO can be turned on by injecting a _______________ gate current and turned off by injecting a _______________ gate current. iv. The anode shorts of a GTO improves the _______________ performance but degrades the _______________ performance. v. The reverse voltage blocking capacity of a GTO is small due to the presence of _______________.Answer: (i) current, minority; (ii) four, three; (iii) positive, negative; (iv) turn off, turn on; (v)anode shorts.5.3 Operating principle of a GTOGTO being a monolithic p-n-p-n structure just like a thryistor its basic operating principle can beexplained in a manner similar to that of a thyristor. In particular, the p-n-p-n structure of a GTOcan be though of consisting of one p-n-p and one n-p-n transistor connected in the regenerativeconfiguration as shown in Fig 5.2. Version 2 EE IIT, Kharagpur 6
  • 136. A A A G p IA p αp n p n iB n n iC1 iC2 p p n IG p p αn G G iB2 n pHole current n Hole currentElectron Electron IK current C Acurrent G C C (a) (b) Fig 5.2: Current distribution in a GTO (a) During turn on; (b) During turn off.From the “two transistor analogy” (Fig 5.2 (a)) of the GTO structure one can write. i C1 = ∝p I A + ICBO1 ( 5.1) i B1 = i C 2 = ∝n I k + ICBO2 ( 5.2 ) I k = I A + IG and IA = i B1 + i C1 ( 5.3) ∝n IG + ( iCBO1 + i CBO2 ) Combining I A = ( 5.4 ) 1- ( ∝n + ∝p )With applied forward voltage VAK less than the forward break over voltage both ICBO1 and ICBO2are small. Further if IG is zero IA is only slightly higher than (ICBO1 + ICBO2). Under this conditionboth ∝n and ∝p are small and (∝p + ∝n) <<1. The device is said to be in the forward blockingmode.To turn the device on either the anode voltage can be raised until ICBO1 and ICBO2 increases byavalanche multiplication process or by injecting a gate current. The current gain ∝ of silicontransistors rises rapidly as the emitter current increases. Therefore, any mechanism which causesa momentary increase in the emitter current can be used to turn on the device. Normally, this isdone by injecting current into the p base region via the external gate contract. As ∝n + ∝papproaches unity the anode current tends to infinity. Physically as ∝n + ∝p nears unity the devicestarts to regenerate and each transistor drives its companion into saturation. Once in saturation,all junctions assume a forward bias and total potential drop across the device becomesapproximately equal to that of a single p-n diode. The anode current is restricted only by theexternal circuit. Once the device has been turned on in this manner, the external gate current isno longer required to maintain conduction, since the regeneration process is self-sustaining.Reversion to the blocking mode occurs only when the anode current is brought below the“holding current” level. Version 2 EE IIT, Kharagpur 7
  • 137. To turn off a conducting GTO the gate terminal is biased negative with respect to the cathode.The holes injected from the anode are, therefore, extracted from the p base through the gatemetallization into the gate terminal (Fig 5.2 (b)). The resultant voltage drop in the p base abovethe n emitter starts reverse biasing the junction J3 and electron injection stops here. The processoriginates at the periphery of the p base and the n emitter segments and the area still injectingelectron shrinks. The anode current is crowded into higher and higher density filaments in mostremote areas from the gate contact. This is the most critical phase in the GTO turn off processsince highly localized high temperature regions can cause device failure unless these currentfilaments are quickly extinguished. When the last filament disappears, electron injection stopscompletely and depletion layer starts to grow on both J2 and J3. At this point the device onceagain starts blocking forward voltage. However, although the cathode current has ceased theanode to gate current continues to flow (Fig 5.2 (b)) as the n base excess carriers diffuse towardsJ1. This “tail current” then decays exponentially as the n base excess carriers reduce byrecombination. Once the tail current has completely disappeared does the device regain its steadystate blocking characteristics. “Anode Shorts” (or transparent emitter) helps reduce the tailcurrent faster by providing an alternate path to the n base electrons to reach the anode contactwithout causing appreciable hole injection from anode.Exercise 5.2Fill in the blank(s) with the appropriate word(s) i. After a GTO turns on the gate current can be _______________. ii. A conducting GTO reverts back to the blocking mode when the anode current falls below _______________ current. iii. To turn off a conducting GTO the gate terminal is biased _______________ with respect to the _______________. iv. “Current filaments” produced during the turn off process of a GTO can destroy the device by creating local _______________. v. “Anode shorts” help to reduce the _______________ current in a GTO.Answer: (i) removed; (ii) holding; (iii) negatively, cathode; (iv) hot spot; (v) tail. Version 2 EE IIT, Kharagpur 8
  • 138. 5.4 Steady state and dynamic characteristics of a GTO5.4.1Steady state output and gate characteristics + VAK - IA - IG IA vg Min Max IG + IL VBRR IL VAK VBRF vg (a) (b) Fig. 5.3: Steady state characteristics of a GTO (a) Output characteristics; (b) Gate characteristics.This characteristic in the first quadrant is very similar to that of a thyristor as shown in Fig. 5.3(a). However, the latching current of a GTO is considerably higher than a thyristor of similarrating. The forward leakage current is also considerably higher. In fact, if the gate current is notsufficient to turn on a GTO it operates as a high voltage low gain transistor with considerableanode current. It should be noted that a GTO can block rated forward voltage only when the gateis negatively biased with respect to the cathode during forward blocking state. At least, a lowvalue resistance must be connected across the gate cathode terminal. Increasing the value of thisresistance reduces the forward blocking voltage of the GTO. Asymmetric GTOs have small (20-30 V) reverse break down voltage. This may lead the device to operate in “reverse avalanche”under certain conditions. This condition is not dangerous for the GTO provided the avalanchetime and current are small. The gate voltage during this period must remain negative.Fig 5.3 (b) shows the gate characteristics of a GTO. The zone between the min and max curvesreflects parameter variation between individual GTOs. These characteristics are valid for DC andlow frequency AC gate currents. They do not give correct voltage when the GTO is turned on dIwith high dia and G . VG in this case is much higher. dt dt Version 2 EE IIT, Kharagpur 9
  • 139. 5.4.2 Dynamic characteristics of a GTO iA, VAK di dt VDM Vd VD IL0.9VD ∫∫ VD 0.9IL RL tON IL VT Itail di/dt 0.1IL0.1VD ∫∫ limiting ∫∫ t L td tr Ig Vg dig/dt ts tf ttail ig IGM IG vg ∫∫ t VgR QgQ IgQ digQ dt Fig. 5.4: Switching characteristics of a GTO. Fig 5.4 shows the switching characteristics of a GTO and refers to the resistive dc load switching circuit shown on the right hand side. When the GTO is off the anode current is zero and VAK = Vd. To turn on the GTO, a positive gate current pulse is injected through the gate terminal. A substantial gate current ensure that all GTO cathode segments are turned on simultaneously and within a short time. There is a delay between the application of the gate pulse and the fall of anode voltage, called the turn on delay time td. After this time the anode voltage starts falling while the anode current starts rising towards its steady value IL. Within a further time interval tr they reach 10% of their initial value and 90% of their final value respectively. tr is called the current rise time (voltage fall time). Both td and maximum permissible on state di A are very dt much gate current dependent. High value of I gM and dig at turn on reduces these times and dt di increases maximum permissible on state A . It should be noted that large value of ig (IgM) dt and dig are required during td and tr only. After this time period both vg and ig settles down to dt their steady value. A minimum ON time period tON (min) is required for homogeneous anode current conduction in the GTO. This time is also necessary for the GTO to be able to turn off its rated anode current. Version 2 EE IIT, Kharagpur 10
  • 140. To turn off a GTO the gate terminal is negatively biased with respect to the cathode. With theapplication of the negative bias the gate current starts growing in the negative direction.However, the anode voltage,current or the gate voltage does not change appreciably from theiron state levels for a further time period called the storage time (ts). The storage time increases diwith the turn off anode current and decrease with gQ . During storage time the load current at dtthe cathode end is gradually diverted to the gate terminal. At the end of the storage time gatecurrent reaches its negative maximum value IgQ. At this point both the junctions J2 & J3 of theGTO starts blocking voltage. Consequently, both the gate cathode and the anode cathode voltagestarts rising towards their final value while the anode current starts decreasing towards zero. Atthe end of current fall time “tf” the anode current reaches 10% of its initial value after which boththe anode current and the gate current continues to flow in the form of a current tail for a furtherduration of ttail. A GTO is normally used with a R-C turn off snubber. Therefore, VAK does notstart to rise appreciably till tf. At this point VAK starts rising rapidly and exceeds the dc voltageVd (VdM) (due to resonance of snubber capacitor with di limiting inductor) before setting dtdown at its steady value Vd . A GTO should not be retriggered within a minimum off period off(min) to avoid the risk of failure due to localized turn ON. GTOs have typically low turn off gainin the range of 4-5.5.4.3 GTO gate drive circuitA GTO gate drive has to fulfill the following functions. • Turn the GTO on by means of a high current pulse (IGM) • Maintain conduction through provision of a continuous gate current (IG, also known as the “back-porch current”). • Turn the GTO off with a high negative gate current pulse. • Reinforce the blocking state of the device by a negative gate voltage.A typical gate drive arrangement for a large power GTO is show in Fig 5.5. Version 2 EE IIT, Kharagpur 11
  • 141. H.F.DC to H.F. AC to DC Output AC INV. H.F TXF Rectifier Stage A B C D E F Optical Fiber optic Control cable Logic Electrical Optical - Electrical Converter (a) + A R1 R2 C2 + ON T1 - G OFF T2 - R3 - + K (b) Fig. 5.5: Gate drive circuit of a GTO. (a) Block diagram, (b) Circuit diagram of the output stageIn the block diagram of Fig 5.5 (a) it is assumed that there is a potential difference of several kVsbetween the master control and individual gate units.The ON and OFF pulses for a GTO is communicated to individual gate units through fiber opticcables. These optical signals are converted to electrical signals by a optical electrical converter.These electrical signals through the control logic then produces the ON and OFF signal for theout put stage which in turn sends positive and negative gate current to the GTO. Depending onthe requirement the control logic may also supervise GTO conduction by monitoring the gate-cathode voltage. Any fault is relayed back via fiber optic cable to the master control. Powersupply for the Gate drive units are derived from a common power supply through a highfrequency SMPS (Blocks A, B & C) arrangement.Fig 5.5 (b) shows the circuit implementation of the output stage. The top switch T1 sends positivegate pulse to the GTO gate. At the instant of turn on of T1 ,C2 acts almost as a short circuit and Version 2 EE IIT, Kharagpur 12
  • 142. the positive gate current is determined by the parallel combination of R1 and R2. However, atsteady state only R1 determines the gate current IG.The bottom switch T2 is used for biasing the GTO gate negative with respect to the cathode.Since, relatively large negative gate current flows during turn off, no external resistance is usedin series with T2. Instead, the ON state resistance of T2 is utilized for this purpose. In practice, alarge number of switches are connected in parallel to obtain the required current rating of T2. Alow value resistance R3 is connected between the gate and the cathode terminals of the GTO toensure minimum forward blocking voltage.Exercise 5.3Fill in the blank(s) with the appropriate word(s) i. The _______________ current and forward _______________ current of a GTO are considerably higher compared to a thyristor. ii. If the gate current is insufficient a GTO can operate as a low gain _______________. iii. Reverse blocking voltage of _______________ GTO is small. iv. To ensure that all GTO cathode segments are turned on simultaneously the magnitude of the _______________ current should be _______________. v. High value of gate current and dig/dt enhances the _______________ capability of a GTO during turn on. vi. During storage time the load current in a GTO is diverted from the _______________ to the _______________ terminal.vii. GTOs have low turn off _______________ gain.viii. After the current fall time during turn off of a GTO the anode current continuous for some more time in the form of a _______________. ix. The gate drive unit of a GTO should provide continuous positive gate _______________ during ON period and continuous negative gate _______________ during OFF period. x. In the gate drive unit of a GTO a low value resistance is connected between the gate and the cathode terminals to ensure minimum _______________ voltage.Answer: (i) latching, leakage; (ii) transistor; (iii) asymmetric; (iv) gate, high; (v) di/dt; (vi) cathode, gate; (vii) current; (viii) current tail; (ix) current, voltage; (x) forward blocking. Version 2 EE IIT, Kharagpur 13
  • 143. 5.5 GTO Ratings5.5.1Steady state voltage and current ratingVDRM: It is the maximum repetitive forward voltage the GTO can block in the forwarddirection assuming line frequency sinusoidal voltage waveform. It is important to note that GTOcan block rated voltage only if the gate is reverse biased or at least connected to the cathodethrough a low value resistance. Manufactures usually provide the forward voltage withstandingcapacity of the GTO as a functions of the gate cathode reverse voltage (and /or resistance) for agiven forward dv . dtVRRM: It is the maximum repetitive reverse voltage the GTO is able to withstand. For allasymmetric GTOs this value is in the range of 20-30 V, since it is determined by the gatecathode junction break down voltage. Due to the anode shorted structure of the GTO the anode –base junction (J1) does not block any reverse voltage. Unlike VDRM, VRRM rating may beexceeded for a short time without destroying the device. This “reverse avalanche” capability ofthe GTO is useful in certain situations as explained in Fig 5.6. VG1 IG1 IG1 VG1 IG1 IL VD G1 D1 VG1 t IL VD ID2 VG2 VD IL VG2 t G2 D2 ID2 Vfr > VRRM (a) (b) Fig. 5.6: Reverse avalanche capability of a GTO (a) Voltage source inverter phase leg; (b) Voltage, current waveforms.In the voltage source inverter phase leg shown in Fig 5.6 (a), as the GTO G1 is turned off thecurrent through it (IG1) starts reducing. The difference current (IL - IG1) is transferred to thesnubber capacitance of G1 and the voltage across G1 (VG1) starts increasing. When if becomesequal to the dc link voltage VD , D2 is forward biased. However, due to the forward recoveryvoltage of D2 (Vfr) the reverse voltage across G2 may exceed VRRM rating of G2 and drive it intoreverse avalanche. This condition is not dangerous for G2 provided the avalanche time andcurrent are small (typically within 10 μs and 1000 A respectively). However, the gate voltagemust remain negative during this time. Version 2 EE IIT, Kharagpur 14
  • 144. VDC: This is the maximum continuous DC voltage the device can withstand. Exceeding thisvoltage does not immediately lead to device failure, but the probability of a cosmic radiationfailure increases progressively with the applied dc voltage.IFAVM and IFRMS: These are maximum average and RMS on state current respectively. They arespecified at a given case temperature assuming half wave sinusoidal on state current at powerfrequency.IFSM: This is the maximum allowed peak value of a power frequency half sinusoidal non-repetitive surge current. The pulse is assumed to be applied at an instant when the GTO isoperating at its maximum junction temperature. The voltage across the device just after the surgeshould be zero.∫ i dt : This is the limiting value of the surge current integral assuming half cycle sine wave 2surge current. The junction temperature is assumed to be at the maximum value before the surgeand the voltage across the device following the surge is assumed to be zero. The i2t rating of asemiconductor fuse must be less than this value in order to protect the GTO. Plots of both IFSMand ∫ i 2 dt as functions of surge pulse width are usually provided by the manufacturer.VF : This is the plot of the instantaneous forward voltage drop vs instantaneous forwardcurrent at different junction temperatures.Pav : For some frequently encountered current waveforms (e.g. sine wave, square wave) theplot of the average on state power dissipation as a function of the average on state current isprovided by the manufacturers at a given junction temperature.IH: This is the holding current of the GTO. This current, in case of a GTO1 , is considerablyhigher compared to a similarly rated thyristor. Serious problem may arise due to anode currentvariation because the GTO may “un-latch” at an in appropriate moment. This problem can beavoided by feeding a continuous current into the gate (called the “back porch” current) duringON period of the device. This DC gate current should be about 20% higher than the gate triggercurrent (IGT) at the lowest expected junction temperature. di crit : This is the maximum permissible value of the rate of change of forward current during dtturn on. This value is very much dependent on the peak gate current magnitude and the rate ofincrease of the gate current. A substantial gate current ensures that all GTO cathode segments areturned ON simultaneously and within a short time so that no local hot spot is created. diThe g and IgM values specified in the operating conditions should, therefore, be considered as dtminimum values.5.5.2 Gate specificationIg vs Vg: It is a plot of instantaneous gate current as a function of the gate voltage. Thischaracteristic is valid for DC and low frequency AC gate currents. They do not define the gate Version 2 EE IIT, Kharagpur 15
  • 145. di gvoltage when the GTO is turned on from high anode voltage with high di/dt and . Vg in this dtcase is much higher. Generally the gate cathode impedance of a GTO is much lower than that ofa conventional thyristor.Vgt, Igt: Igt is the gate trigger current and Vgt , the instantaneous gate cathode voltage when Igt isflowing into the gate. Igt has a strong junction temperature dependence and increases very rapidlywith reduced junction temperature. Igt merely specifies the minimum back porch currentnecessary to turn on the GTO at a low di and maintain it in conduction. dtVgrm: It is the maximum repetitive reverse gate voltage, exceeding which drives the gatecathode junction into avalanche breakdown.Igrm: It is the peak repetitive reverse gate current at Vgrm and Tj (max).Igqm: It is the maximum negative turn off gate current. The gate unit should be designed to dideliver this current under any condition. It is a function of turn off anode current, g during dtturn off and the junction temperature.5.5.3 Specifications related to the switching performancetd, tr, :These are turn on delay time and anode voltage fall time respectively. Both of them can dibe reduced with higher g and IgM for a given turn on anode voltage, current and di . dt dtton (min) : This is the minimum time the GTO requires to establish homogeneous anode current.This time is also necessary for the GTO to be able to turn off its rated anode current.EON : It is the energy dissipated during each turn on operation. Manufacturers specify them asfunctions of turn on anode current for different turn on di/dt and anode voltage EON reduces withincreased IgM .IFgqm : It is the maximum anode current that can be repetitively turned off by a negative gatecurrent. It can be increased by increasing the value of the turn off snubber capacitance whichlimits the dv/dt at turn off. A large negative dig/dt during turn off also helps to increase IFgqm.ts : The storage time ts is defined as the time between the start of negative gate current andthe decrease in anode current. High value of the turn off anode current and junction temperatureincreases it while a large negative dig/dt during turn off decreases it.tf : This is the anode current fall time. It can not be influenced much by gate control.toff(min) : This is the minimum off time before the GTO may be triggered again by a positivegate current. If the device is re-triggered during this time, localized turn on may destroy it. Version 2 EE IIT, Kharagpur 16
  • 146. Eoff : This is the energy dissipated during each turn off operation of the GTO. Eoff increaseswith increase in the turn off anode current and junction temperature while it reduces with turn offsnubber capacitance.Exercise 5.4Fill in the blank(s) with the appropriate word(s) i. A GTO can block rated forward voltage only when the gate is _______________ biased with respect to the _______________. ii. A GTO can operate in the reverse _______________ region for a short time. iii. The holding current of a GTO is much _______________ compared to a thyristor. iv. After a current surge the voltage across a GTO should be reduced to _______________. v. The gate cathode impedance of a GTO is much _______________ compared to a thyristor. vi. The turn on di/dt capability of a GTO can be increased by in creasing the _______________ magnitude of the gate current and _______________ during turn on.vii. The turn on delay time and current rise time of a GTO can be reduced by increasing the gate current _______________ and _______________ during turn ON.viii. The maximum anode current that can be turned off repetitively can be increased by increasing the turn off snubber _______________ and negative _______________.Answer: (i) negatively, cathode; (ii) avalanche; (iii) larger; (iv) zero; (v) smaller; (vi) peak, dig/dt; (vii) magnitude, dig/dt; (viii) capacitance, dig/dt.Reference 1) “GTO and GCT product guide”, ABB semiconductors AG, 1997. 2) “GTO Thyristors” , Makoto Azuma and Mamora Kurata, Proceedings of the IEEE, Vol.76, No. 4, April 1988, pp 419-427. 3) “Power Electronics”, P. S. Bimbhra, Khanna Publlishers, 1993. Version 2 EE IIT, Kharagpur 17
  • 147. Lesson Summary • GTO is a four layer, three terminal current controlled minority carrier device. • A GTO can be turned on by applying a positive gate current pulse when it is forward biased and turned off by applying a negative gate current. • A GTO has a “shorted anode” and highly inter-digitized gate cathode structure to improve the gate turn off performance. • Due to the presence of “anode shorts” a GTO can block only a small reverse voltage. These are called “asymmetric GTOs”. • The forward i-v characteristics of a GTO is similar to that of a thyristor. However, they have relatively larger holding current and gate trigger current. • The turn on di/dt capability of a GTO is significantly enhanced by using higher peak gate current and large rate of rise of the gate current. • Due to relatively larger holding current of a GTO a continuous low value gate current (called the back porch current) should be injected through out the on period of the GTO. • GTOs have relatively low turn off current gain. • The GTO gate drive unit should be capable of injecting large positive and negative gate currents with large rate of rise for satisfactory switching of the device. • A GTO can block rated forward voltage only when the gate cathode junction is reverse biased. • A GTO can operate safely in the “reverse avalanche” region for a short time provided the gate cathode junction is reverse biased. • The switching delay times and energy loss of a GTO can be reduced by increasing the gate current magnitude and its rate of rise. • The maximum turn off anode current of a GTO can be increased by increasing the turn off snubber capacitance. Version 2 EE IIT, Kharagpur 18
  • 148. Practice Problems and Answers Version 2 EE IIT, Kharagpur 19
  • 149. 1. What are the constructional features of a GTO that bestows it with a gate turn off capability? How do they affect the turn on performance of the GTO?2. What are the main differences in the steady state output characteristics of a GTO and a thyristor? What effect do they have on the gate drive requirement of a GTO?3. What are the desirable characteristics of the gate drive circuit of a GTO? How do they influence the switching performance of a GTO?4. What is the significance of the specifications IFAVM and IFRMS in relation to a GTO? Is the specification IFgqm. Same as IFAVM / IFRMS? If not, then which current should one use in a particular application?5. Which paramers of the gate current waveform reduces the turn on energy loss (EON) of a GTO? How does one reduce the turn off energy lass of a GTO? Version 2 EE IIT, Kharagpur 20
  • 150. Answers to practice problems 1. Although a GTO is a four layer (p-n-p-n) three junction devices like a thyristor it has two important constructional differences with a thyristor which bestows it with the gate turn off capability. • The Gate-cathode junction of a GTO is far more inter digitized compared to a thyristor. Thousands of cathode segments, normally arranged in concentric rings around the device center, from the cathode structure of a GTO. This highly inter digitized structure of the GTO cathode ensures that any “current filament” formed during the turn off process of a GTO is quickly extinguished. • “Anode shorts” are introduced at the p+ type anode and n type base junction of a GTO. “Anode shorts” consists of heavily doped n+ type region introduced inside the p+ type anodes. They make direct contact with the anode metal plate and provide an alternate path for the electrons traveling through the n base to reach the anode metal contact without causing bole injection from the p+ anode. This helps to reduce the “tail current” during turn off of a GTO. • Highly inter digitized gate-cathode structure of a GTO helps to enhance the turn on di/dt capability of the device due to faster and more even spreading of the injected gate current to adjacent cathodes. • On the other hand, presence of anode shorts has adverse effect on the turn on performance of a GTO. Referring to Fig 5.2 (a), introduction of anode shorts effectively reduces the current gain ∝p of the top p-n-p transistor. This has the effect of increasing the latching and holding current of a GTO compared to a thyristor. The minimum gate current required to trigger a GTO also increases.2. In the first quadrant of the output i-v plane the steady state output characteristics of a GTO appears to be similar to that of a thyristor. There are some important differences however. • Both holding and latching current of a GTO are considerably higher compared to a similarly rated thyrisstor. • The minimum gate current require to trigger a GTO at a given forward blocking voltage is higher compared to a thyristor. • The forward leakage current of a GTO is considerably higher compared to a thyristor of equal rating. In fact, if the gate current is not sufficient to turn on a GTO it may operate as a high voltage low gain transistor with considerable anode current. • A GTO can block rated forward voltage only when the gate voltage is negative with respect to the cathode or at least the gate is connected to the cathode through a low value resistance. • In the reverse blocking region (i.e third quadrant of the output i-v plane) an asymmetric GTO has much lower reverse break down voltage (20-30V) compared to a thyristors. Exceeding this reverse voltage forces the GTO to operate in the “reverse avalanche” mode. Version 2 EE IIT, Kharagpur 21
  • 151. This mode of operation does not destroy the device provided the gate is negatively biased and the time of such operation is small. • Since the holding current of a GTO is considerably higher than that of a thyristor anode current variations can generate serious problem because the GTO might “unlatch” at an inappropriate moment. To avoid this problem the gate drive unit of a GTO must feed the gate terminal with a continuous “back porch” current during the entire on period of the GTO. This back porch current must be larger than the gate trigger current. • To avoid localized transistor operation during turn on from a high anode voltage with large di/dt, the gate drive unit must inject a peak gate current considerably larger (3-10 times) than the gate trigger current with fast rate of rise. • To ensure that the GTO blocks rated forward voltage and operates safely in the “reverse avalanche” mode the gate voltage must be maintained negative with respect to the cathode for the entire off duration of the GTO.3. The gate drive unit of a GTO should. • Turn the GTO on with a large (3-10 times the minimum gate trigger current) positive gate current pulse with high rate of rise. • Maintain conduction of the GTO through out the ON period by injecting a positive “back porch” gate current which is larger than the minimum gate trigger current. • Turn the GTO off with a large negative gate current with high rate of fall. The peak magnitude of the negative gate current should be at least 20-25% of the maximum anode current during turn off. • Reinforce the blocking state of the device by applying a negative voltage to the gate with respect to cathode for the entire off duration of the GTO. Both the turn on delay time (td) and the voltage fall time (tr) of a GTO can be reduced by increasing the peak positive gate current and its rate of rise during turn on. Energy loss per turn on (EON) also reduces. A large negative gate current during turn off with a stiff slope considerably reduces the storage time (ts) and enhances maximum anode current turn off (IFgqm) capability.4. The specifications of IFAVM and IFRMS are given with reference to power frequency half cycle sine wave anode current. If the GTO is employed in a line commutated phase controlled converter application then these specifications give the maximum allowable average and RMS current through the device respectively. However, in most GTO applications the current waveform is for removed from a sinusoidal shape and the switching losses are a considerable part of the total power losses. IFAVM / IFRMS ratings, in such cases, does not have any practical significance except for comparison of current carrying capacity of different devices. On the other hand, IFgqm rating of a GTO gives the maximum anode current that can be repetitively turned off by gate control. This rating is usually lower than IFAVM / IFRMS. In Version 2 EE IIT, Kharagpur 22
  • 152. high frequency switching application this specification gives the absolute peak value of any desired current waveform the GTO can conduct.5. Eon is reduced by increasing the peak magnitude of the positive gate current during turn on. Eoff is reduced by increasing the turn off snubber capacitance across the GTO. Version 2 EE IIT, Kharagpur 23
  • 153. Module 1Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1
  • 154. Lesson 6 Metal OxideSemiconductor Field Effect Transistor (MOSFET) Version 2 EE IIT, Kharagpur 2
  • 155. Constructional Features, operating principle and characteristics of Power Metal OxideSemiconductor Field Effect Transistor (MOSFET).Instructional ObjectivesOn completion the student will be able to • Differentiate between the conduction mechanism of a MOSFET and a BJT. • Explain the salient constructional features of a MOSFET. • Draw the output i-v characteristics of a MOSFET and explain it in terms of the operating principle of the device. • Explain the difference between the safe operating area of a MOSFET and a BJT. • Draw the switching characteristics of a MOSFET and explain it. • Design the gate drive circuit of a MOSFET. • Interpret the manufacturer’s data sheet rating of a MOSFET. Version 2 EE IIT, Kharagpur 3
  • 156. 6.1 IntroductionHistorically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc)have been the front runners in the quest for an ideal power electronic switch. Ever since theinvention of the transistor, the development of solid-state switches with increased powerhandling capability has been of interest for expending the application of these devices. The BJTand the GTO thyristor have been developed over the past 30 years to serve the need of the powerelectronic industry. Their primary advantage over the thyristors have been the superior switchingspeed and the ability to interrupt the current without reversal of the device voltage. All bipolardevices, however, suffer from a common set of disadvantages, namely, (i) limited switchingspeed due to considerable redistribution of minority charge carriers associated with everyswitching operation; (ii) relatively large control power requirement which complicates thecontrol circuit design. Besides, bipolar devices can not be paralleled easily.The reliance of the power electronics industry upon bipolar devices was challenged by theintroduction of a new MOS gate controlled power device technology in the 1980s. The powerMOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. Thenew device promised extremely low input power levels and no inherent limitation to theswitching speed. Thus, it opened up the possibility of increasing the operating frequency inpower electronic systems resulting in reduction in size and weight. The initial claims of infinitecurrent gain for the power MOSFET were, however, diluted by the need to design the gate drivecircuit to account for the pulse currents required to charge and discharge the high inputcapacitance of these devices. At high frequency of operation the required gate drive powerbecomes substantial. MOSFETs also have comparatively higher on state resistance per unit areaof the device cross section which increases with the blocking voltage rating of the device.Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts)applications where the ON state resistance reaches acceptable values. Inherently fast switchingspeed of these devices can be effectively utilized to increase the switching frequency beyondseveral hundred kHz. From the point of view of the operating principle a MOSFET is a voltage controlledmajority carrier device. As the name suggests, movement of majority carriers in a MOSFET iscontrolled by the voltage applied on the control electrode (called gate) which is insulated by athin metal oxide layer from the bulk semiconductor body. The electric field produced by the gatevoltage modulate the conductivity of the semiconductor material in the region between the maincurrent carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just liketheir integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancementtype. Both of these can be either n- channel type or p-channel type depending on the nature ofthe bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETsalong with their drain current vs gate-source voltage characteristics (transfer characteristics). Version 2 EE IIT, Kharagpur 4
  • 157. D D D D ID ID ID ID G G G G S S S S ID ID ID ID VGS VGS VGS VGSn-channel depletion type p-channel depletion type n-channel enhancement p-channel enhancement MOSFET MOSFET type MOSFET type MOSFET (a) (b) Fig 6.1: Different types of power MOSFET. (a) Circuit symbols and transfer characteristics (b) Photograph of n-channel enhancement type MOSFET. From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This is not convenient in many power electronic applications. Therefore, the enhancement type MOSFETs (particularly of the n-channel variety) is more popular for power electronics applications. This is the type of MOSFET which will be discussed in this lesson. Fig 6.1 (b) shows the photograph of some commercially available n-channel enhancement type Power MOSFETs. 6.2 Constructional Features of a Power MOSFET As mentioned in the introduction section, Power MOSFET is a device that evolved from MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs were by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting technology was called lateral double deffused MOS (DMOS). However it was soon realized that Version 2 EE IIT, Kharagpur 5
  • 158. much larger breakdown voltage and current ratings could be achieved by resorting to a verticallyoriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtuallyall manufacturers of Power MOSFET. A power MOSFET using VDMOS technology hasvertically oriented three layer structure of alternating p type and n type semiconductors as shownin Fig 6.2 (a) which is the schematic representation of a single MOSFET cell structure. A largenumber of such cells are connected in parallel (as shown in Fig 6.2 (b)) to form a completedevice. Source Gate conductor FIELD OXIDE Gate oxide n+ n+ n+ n+ p(body) p(body) n- (drain drift) n+ Drain (a) Contact to source Source Conductor Field oxide Gate Oxide Gate Conductor Single n- MOSFET Cell n+ p n+ n+ p n+ n+ n- n+ (b) Fig. 6.2: Schematic construction of a power MOSFET (a) Construction of a single cell. (b) Arrangement of cells in a device. Version 2 EE IIT, Kharagpur 6
  • 159. The two n+ end layers labeled “Source” and “Drain” are heavily doped to approximately the same level. The p type middle layer is termed the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than n+ regions on both sides). The n- drain drift region has the lowest doping density. Thickness of this region determines the breakdown voltage of the device. The gate terminal is placed over the n- and p type regions of the cell structure and is insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the Source and the Drain terminals of the complete device. Similarly all gate terminals are also connected together. The source is constructed of many (thousands) small polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source regions, to same extent, influences the ON state resistance of the MOSFET. D D S G MOSFET Parasitic BJT + + n p nBody spreading Parasitic BJTresistance n- G G n+ Body diode S S D Fig. 6.3: Parasitic BJT in a MOSFET cell. One interesting feature of the MOSFET cell is that the alternating n+ n- p n+ structure embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into each MOSFET cell as shown in Fig 6.3. The nonzero resistance between the base and the emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type substrate. In the design of the MOSFET cells special care is taken so that this resistance is minimized and switching operation of the parasitic BJT is suppressed. With an effective short circuit between the body and the source the BJT always remain in cut off and its collector-base junction is represented as an anti parallel diode (called the body diode) in the circuit symbol of a Power MOSFET. 6.3 Operating principle of a MOSFET At first glance it would appear that there is no path for any current to flow between the source and the drain terminals since at least one of the p n junctions (source – body and body-Drain) will be reverse biased for either polarity of the applied voltage between the source and the drain. There is no possibility of current injection from the gate terminal either since the gate oxide is a very good insulator. However, application of a positive voltage at the gate terminal with respect to the source will covert the silicon surface beneath the gate oxide into an n type layer or “channel”, thus connecting the Source to the Drain as explained next. Version 2 EE IIT, Kharagpur 7
  • 160. The gate region of a MOSFET which is composed of the gate metallization, the gate(silicon) oxide layer and the p-body silicon forms a high quality capacitor. When a smallvoltage is application to this capacitor structure with gate terminal positive with respect tothe source (note that body and source are shorted) a depletion region forms at the interfacebetween the SiO2 and the silicon as shown in Fig 6.4 (a). VGS1 Gate Electrode Source +++ ++++++++ Electrode Si02 n+ Ionized Depletion layer p acceptor boundary. n- (a) VGS2 VGS2 > VGS1 Gate Electrode Source +++ ++++++++ Electrode Si02 n+ Depletion layer p Ionized boundary. acceptor Free electron n- (b) Version 2 EE IIT, Kharagpur 8
  • 161. VGS3 VGS3 > VGS2 > VGS1 Gate Electrode Source +++ ++++++++ Electrode Si02 Inversion layer n+ with free electrons Depletion layer boundary. p Ionized n- acceptor (c) Fig. 6.4: Gate control of MOSFET conduction. (a) Depletion layer formation; (b) Free electron accumulation; (c) Formation of inversion layer.The positive charge induced on the gate metallization repels the majority hole carriers fromthe interface region between the gate oxide and the p type body. This exposes thenegatively charged acceptors and a depletion region is created.Further increase in VGS causes the depletion layer to grow in thickness. At the same timethe electric field at the oxide-silicon interface gets larger and begins to attract free electronsas shown in Fig 6.4 (b). The immediate source of electron is electron-hole generation bythermal ionization. The holes are repelled into the semiconductor bulk ahead of thedepletion region. The extra holes are neutralized by electrons from the source.As VGS increases further the density of free electrons at the interface becomes equal to thefree hole density in the bulk of the body region beyond the depletion layer. The layer offree electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). Theinversion layer has all the properties of an n type semiconductor and is a conductive path or“channel” between the drain and the source which permits flow of current between thedrain and the source. Since current conduction in this device takes place through an n- type“channel” created by the electric field due to gate source voltage it is called “Enhancementtype n-channel MOSFET”.The value of VGS at which the inversion layer is considered to have formed is called the“Gate – Source threshold voltage VGS (th)”. As VGS is increased beyond VGS(th) theinversion layer gets some what thicker and more conductive, since the density of freeelectrons increases further with increase in VGS. The inversion layer screens the depletionlayer adjacent to it from increasing VGS. The depletion layer thickness now remainsconstant. Version 2 EE IIT, Kharagpur 9
  • 162. Exercise 6.1 (after section 6.3)1. Fill in the blank(s) with the appropriate word(s) i. A MOSFET is a ________________ controlled ________________ carrier device. ii. Enhancement type MOSFETs are normally ________________devices while depletion type MOSFETs are normally ________________ devices. iii. The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of ________________. iv. The MOSFET cell embeds a parasitic ________________ in its structure. v. The gate-source voltage at which the ________________ layer in a MOSFET is formed is called the ________________ voltage. vi. The thickness of the ________________ layer remains constant as gate source voltage is increased byond the ________________ voltage.Answer: (i) voltage, majority; (ii) off, on; (iii) SiO2, (iv) BJT, (v) inversion, threshold; (vi) depletion, threshold.2. What are the main constructional differences between a MOSFET and a BJT? What effect do they have on the current conduction mechanism of a MOSFET? Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors. However, unlike BJT the p type body region of a MOSFET does not have an external electrical connection. The gate terminal is insulated for the semiconductor by a thin layer of SiO2. The body itself is shorted with n+ type source by the source metallization. Thus minority carrier injection across the source-body interface is prevented. Conduction in a MOSFET occurs due to formation of a high density n type channel in the p type body region due to the electric field produced by the gate-source voltage. This n type channel connects n+ type source and drain regions. Current conduction takes place between the drain and the source through this channel due to flow of electrons only (majority carriers). Where as in a BJT, current conduction occurs due to minority carrier injection across the Base-Emitter junction. Thus a MOSFET is a voltage controlled majority carrier device while a BJT is a minority carrier bipolar device.6.4 Steady state output i-v characteristics of a MOSFET The MOSFET, like the BJT is a three terminal device where the voltage on the gate terminal controls the flow of current between the output terminals, Source and Drain. The source terminal is common between the input and the output of a MOSFET. The output characteristics of a MOSFET is then a plot of drain current (iD) as a function of the Drain – Source voltage (vDS) with gate source voltage (vGS) as a parameter. Fig 6.5 (a) shows such a characteristics. Version 2 EE IIT, Kharagpur 10
  • 163. VGS – VGS (th) = VDS Electron Drift iD Velocity ohmic Increasing VGS VGS6 rDS(ON) Active VGS5 [VGS–VGS(th)]<VDS VGS4 VGS3 VGS2 vgs1 Cut off (VGS < VGS (th)) VDSS vDS Electric (a) (c) Field G S iD n+Source Channel Driftregion p resistance regionresistance iD resistance n- Drain n+ resistance VGS(th) VGS (b) D (d) Fig. 6.5: Output i-v characteristics of a Power MOSFET (a) i-v characteristics; (b) Components of ON-state resistance; (c) Electron drift velocity vs Electric field; (d) Transfer With gate-source voltage (VGS) below the threshold voltage (vGS (th)) the MOSFET operates in the cut-off mode. No drain current flows in this mode and the applied drain– source voltage (vDS) is supported by the body-collector p-n junction. Therefore, the maximum applied voltage should be below the avalanche break down voltage of this junction (VDSS) to avoid destruction of the device. When VGS is increased beyond vGS(th) drain current starts flowing. For small values of vDS (vDS < (vGS – vGS(th)) iD is almost proportional to vDS. Consequently this mode of operation is called “ohmic mode” of operation. In power electronic applications a MOSFET is operated either in the cut off or in the ohmic mode. The slope of the vDS – iD characteristics in this mode is called the ON state resistance of the MOSFET (rDS (ON)). Several physical resistances as shown in Fig 6.5 (b) contribute to rDS (ON). Note that rDS (ON) reduces with increase in vGS. This is mainly due to reduction of the channel resistance at higher value of Version 2 EE IIT, Kharagpur 11
  • 164. vGS. Hence, it is desirable in power electronic applications, to use as large a gate-sourcevoltage as possible subject to the dielectric break down limit of the gate-oxide layer.At still higher value of vDS (vDS > (vGS – vGS (th)) the iD – vDS characteristics deviates fromthe linear relationship of the ohmic region and for a given vGS, iD tends to saturate withincrease in vDS. The exact mechanism behind this is rather complex. It will suffice to statethat, at higher drain current the voltage drop across the channel resistance tends to decreasethe channel width at the drain drift layer end. In addition, at large value of the electric field,produced by the large Drain – Source voltage, the drift velocity of free electrons in thechannel tends to saturate as shown in Fig 6.5 (c). As a result the drain current becomesindependent of VDS and determined solely by the gate – source voltage vGS. This is theactive mode of operation of a MOSFET. Simple, first order theory predicts that in theactive region the drain current is given approximately by i D = K(vGS - vGS (th))2 (6.1)Where K is a constant determined by the device geometry.At the boundary between the ohmic and the active region vDS = vGS - vGS (th) (6.2) Therefore, i D = KvDS2 (6.3)Equation (6.3) is shown by a dotted line in Fig 6.5 (a). The relationship of Equation (6.1)applies reasonably well to logic level MOSFETs. However, for power MOSFETs thetransfer characteristics (iD vs vGS) is more linear as shown in Fig 6.5 (d).At this point the similarity of the output characteristics of a MOSFET with that of a BJTshould be apparent. Both of them have three distinct modes of operation, namely, (i)cut off,(ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some importantdifferences as well. • Unlike BJT a power MOSFET does not undergo second break down. • The primary break down voltage of a MOSFET remains same in the cut off and in the active modes. This should be contrasted with three different break down voltages (VSUS, VCEO & VCBO) of a BJT. • The ON state resistance of a MOSFET in the ohmic region has positive temperature coefficient which allows paralleling of MOSFET without any special arrangement for current sharing. On the other hand, vCE (sat) of a BJT has negative temperature coefficient making parallel connection of BJTs more complicated.As in the case of a BJT the operating limits of a MOSFET are compactly represented in aSafe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of a Version 2 EE IIT, Kharagpur 12
  • 165. BJT the SOA of a MOSFET is plotted on a log-log graph. On the top, the SOA is restricted by the absolute maximum permissible value of the drain current (IDM) which should not be exceeded even under pulsed operating condition. To the left, operating restriction arise due to the non zero value of rDS(ON) corresponding to vGS = vGS(Max). To the right, the first operating restriction is due to the limit on the maximum permissible junction temperature rise which depends on the power dissipation inside the MOSFET. This limit is different for DC (continuous) and pulsed operation of different pulse widths. As in the case of a BJT the pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. A MOSFET does not undergo “second break down” and no corresponding operating limit appears on the SOA. The final operation limit to the extreme right of the SOA arises due to the maximum permissible drain source voltage (VDSS) which is decided by the avalanche break down voltage of the drain -body p-n junction. This is an instantaneous limit. There is no distinction between the forward biased and the reverse biased SOAs for the MOSFET. They are identical. Log (iD) IDM 10-5sec rDS(ON) limit 10-4sec (VGS = VGS(max)) Max. 10-3sec Power Dissipation DC Limit (Timax) Primary voltage breakdown limit VDSS Log (vDS) Fig. 6.6: Safe operating area of a MOSFET. Due to the presence of the anti parallel “body diode”, a MOSFET can not block any reverse voltage. The body diode, however, can carry an RMS current equal to IDM. It also has a substantial surge current carrying capacity. When reverse biased it can block a voltage equal to VDSS. For safe operation of a MOSFET, the maximum limit on the gate source voltage (VGS (Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of the thin gate oxide layer and permanent failure of the device. It should be noted that even static charge inadvertently put on the gate oxide by careless handling may destroy it. The device user should ground himself before handling any MOSFET to avoid any static charge related problem.Exercise 6.2Fill in the blank(s) with the appropriate word(s) i. A MOSFET operates in the ________________ mode when vGS < vGS(th) Version 2 EE IIT, Kharagpur 13
  • 166. ii. In the ohmic region of operation of a MOSFET vGS – vGS (th) is greater than ________________. iii. rDS (ON) of a MOSFET ________________ with increasing vGS. iv. In the active region of operation the drain current iD is a function of ________________ alone and is independent of ________________. v. The primary break down voltage of MOSFET is ________________ of the drain current. vi. Unlike BJT a MOSFET does not undergo ________________. vii. ________________ temperature coefficient of rDS(ON) of MOSFETs facilitates easy ________________ of the devices. viii. In a Power MOSFET the relation ship between iD and vGS – vGS(th) is almost ________________ in the active mode of operation. ix. The safe operating area of a MOSFET is restricted on the left hand side by the ________________ limit. Answer: (i) Cut off; (ii) vDS; (iii) decreases; (iv) vGS, vDS; (v) independent; (vi) second break down; (vii) Positive, paralleling; (viii) linear; (ix) rDS (ON);6.5 Switching characteristics of a MOSFET6.5.1 Circuit models of a MOSFET cell Like any other power semiconductor device a MOSFET is used as a switch in all power electronic converters. As a switch a MOSFET operates either in the cut off mode (switch off) or in the ohmic mode (switch on). While making transition between these two states it traverses through the active region. Being a majority carrier device the switching process in a MOSFET does not involve any inherent delay due to redistribution of minority charge carriers. However, formation of the conducting channel in a MOSFET and its disappearance require charging and discharging of the gate-source capacitance which contributes to the switching times. There are several other capacitors in a MOSFET structure which are also involved in the switching process. Unlike bipolar devices, however, these switching times can be controlled completely by the gate drive circuit design. Version 2 EE IIT, Kharagpur 14
  • 167. G S Gate oxide + n CGD CGS CGD p Drain body CGD1 idealized depletion CDS layer Actual n- CGD2 n+ VGS – VGS (th) = VDS VDS D (a) (b) D D D CGD CGD CGDG (cut off) G iD = f(vGS) G rDS(ON) (Active) (Ohmic) CGS CGS CGS S S S (c) Fig. 6.7: Circuit model of a MOSFET (a) MOSFET capacitances (b) Variation of CGD with VDS (c) Circuit models. Fig 6.7 (a) shows three important capacitances inherent in a MOSFET structure. The most prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the gate metallization and the n+ type source region. It has the largest value (a few nano farads) and remains more or less constant for all values of vGS and vDS. The next largest capacitor (a few hundred pico forwards) is formed by the drain – body depletion region directly below the gate metallization in the n- drain drift region. Being a depletion layer capacitance its value is a strong function of the drain source voltage vDS. For low values of vDS (vDS < (vGS – vGS (th))) the value of CGD (CGD2) is considerably higher than its value for large vDS as shown in Fig 6.7 (b). Although variation of CGD between CGD1 and CGD2 is continuous a step change in the value of CGD at vDS = vGS – vGS(th) is assumed for simplicity. The lowest value capacitance is formed between the drain and the source terminals due to the drain – body depletion layer away form the gate metallization and below the source metallization. Although this capacitance is important for some design considerations (such as snubber design, zero voltage switching etc) it does not appreciably affect the “hard switching” performance of a MOSFET. Consequently, it will be neglected in our discussion. From the Version 2 EE IIT, Kharagpur 15
  • 168. above discussion and the steady state characteristics of a MOSFET the circuit models of a MOSFET in three modes of operation can be drawn as shown in Fig 6.7 (c).6.5.2 Switching waveforms The switching behavior of a MOSFET will be described in relation to the clamped inductive circuit shown in Fig 6.8. For simplicity the load current is assumed to remain constant over the small switching interval. Also the diode DF is assumed to be ideal with no reverse recovery current. The gate is assumed to be driven by an ideal voltage source giving a step voltage between zero and Vgg in series with an external gate resistance Rg. VD DF IO if + iD CGD VDS Rg ig - Vgg + - CGS Fig. 6.8: Clamped inductive switching circuit using a MOSFET. To turn the MOSFET on, the gate drive voltage changes from zero to Vgg. The gate source voltage which was initially zero starts rising towards Vgg with a time constant τ1 = Rg (CGS + CGD1) as shown in Fig 6.9. Version 2 EE IIT, Kharagpur 16
  • 169. Vgg ∫∫ τ2 VGS VGSI0VGS(th) τ1 τ2 = Rg(CGS+CGD2) ∫∫ t ig τ1 = Rg(CGS+CGD1)VggR g igI0 ∫∫ t igI0 Vgg − Rg iD, if iD if ∫∫ I0 I0 if iD ∫∫ t VDS I0ros (ON) ∫∫ t tdON tri tfv1 tfv2 td(off) trv2 trvi tfi tON toff Fig. 6.9: Switching waveforms of a clamped inductive switching circuit using MOSFET Note that during this period the drain voltage vDS is clamped to the supply voltage VD through the free wheeling diode DF. Therefore, CGS and CGD can be assumed to be connected in parallel effectively. A part of the total gate current ig charges CGS while the other part discharges CGD. Till vGS reaches vGS (th) no drain current flows. This time period is called turn on delay time (td(ON)). Note that td(ON) can be controlled by controlling Rg. Byond td(ON) iD increases linearly with vGS and in a further time tri (current rise time) reaches Io. The corresponding value of vGS and ig are marked as VGS Io and ig Io respectively in Fig 6.9. At this point the complete load current has been transferred to the MOSFET from the free wheeling diode DF. iD does not increase byond this point. Since in the active region iD and vGS are linearly related, vGS also becomes clamped at the value vGSIo. The gate current ig now discharges CGD and the drain voltage starts falling. d d d ig V -V I v DS = ( vGS + vGD ) = v GD = = GG GS o ( 6.4 ) dt dt dt CGD CGD R g Version 2 EE IIT, Kharagpur 17
  • 170. The fall of vDS occurs in two distinct intervals. When the MOSFET is in the active region (vDS > (vGS – vGS (th)) CGD = CGD1.Since CGD1 << CGD2, vDS falls rapidly. This fast fall time of vDS is marked tfv1 in Fig 6.9. However, once in the ohmic region, CGD = CGD2 >> CGD1. Therefore, rate of fall of vDS slows down considerably (tfv2). Once vDS reaches its on state value (rDS(ON) Io) vGS becomes unclamped and increases towards Vgg with a time constant τ2 = Rg (CGS + CGD2). Note that all switching periods can be reduced by increasing Vgg or / and decreasing Rg. The total turn on time is tON = td(ON) + tri + tfv1 + tfv2. To turn the MOSFET OFF, Vgg is reduced to zero triggering the exact reverse process of turn on to take place. The corresponding waveforms and switching intervals are show in Fig 6.9. The total turn off time toff = td(off) + trv1 + trv2 + tfi.6.5.3 MOSFET Gate Drive MOSFET, being a voltage controlled device, does not require a continuous gate currentto keep it in the ON state. However, it is required to charge and discharge the gate-source and thegate-drain capacitors in each switching operation. The switching times of a MOSFET essentiallydepends on the charging and discharging rate of these capacitors. Therefore, if fast charging anddischarging of a MOSFET is desired at fast switching frequency the gate drive powerrequirement may become significant. Fig 6.10 (a) shows a typical gate drive circuit of aMOSFET. Version 2 EE IIT, Kharagpur 18
  • 171. VGG VD R1 RG + VGG (β1 +1) R1 Q1Logic level RGgate pulse RG Q2 VGG Q3 (b) (a) VD D DF IL R RG G D R S B RB G (d) S (c) Fig. 6.10: MOSFET gate drive circuit. (a) Gate drive circuit; (b) Equivalent circuit during turn on and off; (b) Effect of parasitic BJT; (d) Parallel connection of MOSFET’s. To turn the MOSFET on the logic level input to the inverting buffer is set to high state so that transistor Q3 turns off and Q1 turns on. The top circuit of Fig 6.10 (b) shows the equivalent circuit during turn on. Note that, during turn on Q1 remains in the active region. The effective gate resistance is RG + R1 / (β1 + 1). Where, β1 is the dc current gain of Q1. Version 2 EE IIT, Kharagpur 19
  • 172. To turn off the MOSFET the logic level input is set to low state. Q3 and Q2 turns on whole Q1 turns off. The corresponding equivalent circuit is given by the bottom circuit of Fig 6.10 (b) The switching time of the MOSFET can be adjusted by choosing a proper value of RG. Reducing RG will incase the switching speed of the MOSFET. However, caution should be exercised while increasing the switching speed of the MOSFET in order not to turn on the parasitic BJT in the MOSFET structure inadvertently. The drain-source capacitance (CDS) is actually connected to the base of the parasitic BJT at the p type body region. The body source short has some nonzero resistance. A very fast rising drain-source voltage will send sufficient displacement current through CDS and RB as shown in Fig 6.10 (c). The voltage drop across RB may become sufficient to turn on the parasitic BJT. This problem is largely avoided in a modern MOSFET design by increasing the effectiveness of the body-source short. The devices are now capable of dvDS/dt in excess to 10,000 V/μs. Of course, this problem can also be avoided by slowing down the MOSFET switching speed. Since MOSFET on state resistance has positive temperature coefficient they can be paralleled without taking any special precaution for equal current sharing. To parallel two MOSFETs the drain and source terminals are connected together as shown in Fig 6.10 (d). However, small resistances (R) are connected to individual gates before joining them together. This is because the gate inputs are highly capacitive with almost no losses. Some stray inductance of wiring may however be present. This stray inductance and the MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate voltage that can result in puncture of the gate qxide layer due to voltage increase during oscillations. This is avoided by the damping resistance R.Exercise 6.31. Fill in the blank(s) with the appropriate word(s) i. The Gate-Source capacitance of a MOSFET is the ________________ among all three capacitances. ii. The Gate-Drain transfer capacitance of a MOSFET has large value in the ________________ region and small value in the ________________ region. iii. During the turn on delay time the MOSFET gate source voltage rises from zero to the ________________ voltage. iv. The voltage fall time of a MOSFET is ________________ proportional to the gate charging resistance. v. Unlike BJT the switching delay times in a MOSFET can be controlled by proper design of the ________________ circuit.Answer: (i) largest; (ii) ohmic, active; (iii) threshold; (iv) inversely; (v) gate drive. Version 2 EE IIT, Kharagpur 20
  • 173. 2. A Power MOSFET has the following data CGS = 800 pF ; CGD = 150 pF; gf = 4; vGS(th) = 3V; It is used to switch a clamped inductive load (Fig 6.8) of 20 Amps with a supply voltage VD= 200V. The gate drive voltage is vgg = 15V, and gate resistance Rg = 50Ω. Find out maximum did dv DS value of and during turn ON. dt dtAnswer: During turn on i D ≈ g f ( v gs - v gs (th) ) di D dv gs ∴ = gf dt dt dv V -vBut ( CGS + CGD ) gs = gg gs dt Rg di D dv gf ∴ dt = g f gs = dt R g ( CGS + CGD ) ( Vgg - vgs ) di D gf g f ( Vgg - vgs (th) )∴ dt = R g ( CGS + CGD ) (V gg - vgs Min )= R g ( CGS + CGD ) Max di Dsince for vgs < vgs (th) iD = =0 dt di D 4 -12 (∴ = 15 - 3) = 1.01×109 A sec dt Max 50×950×10From equation (6.4) dv DS Vgg - VGS , Io = dt CGD R gFor Io = 20 A, vgs(th) = 3V, and gf = 4 I 20 VGS , Io = o + vgs (th) = + 3 = 8 volts gf 4 dv DS 15 -8∴ = = 933×106 V sec. dt 150×10-12 ×506.6 MOSFET Ratings Steady state operating limits of a MOSFET are usually specified compactly as a safe operating area (SOA) diagram. The following limits are specified. VDSS: This is the drain-source break down voltage. Exceeding this limit will destroy the device due to avalanche break down of the body-drain p-n junction. Version 2 EE IIT, Kharagpur 21
  • 174. IDM: This is the maximum current that should not be exceeded even under pulsed currentoperating condition in order to avoid permanent damage to the bonding wires.Continuous and Pulsed power dissipation limits: They indicate the maximumallowable value of the VDS, iD product for the pulse durations shown against each limit.Exceeding these limits will cause the junction temperature to rise beyond the acceptablelimit.All safe operating area limits are specified at a given case temperature. In addition, several important parameters regarding the dynamic performance of thedevice are also specified. These areGate threshold voltage (VGS (th)): The MOSFET remains in the cut off region when vGSin below this voltage. VGS (th) decreases with junction temperature.Drain Source on state resistance (rDS (ON)): This is the slope of the iD – vDScharacteristics in the ohmic region. Its value decreases with increasing vGS and increaseswith junction temperature. rDS (ON) determines the ON state power loss in the device.Forward Transconductance (gfs): It is the ratio of iD and (vGS – vGS(th)). In a MOSFETswitching circuit it determines the clamping voltage level of the gate – source voltage andthus influences dvDS/dt during turn on and turn off.Gate-Source breakdown voltage: Exceeding this limit will destroy the gate structure ofthe MOSFET due to dielectric break down of the gate oxide layer. It should be noted thatthis limit may by exceeded even by static charge deposition. Therefore, specialprecaution should be taken while handing MOSFETs.Input, output and reverse transfer capacitances (CGS, CDS & CGD): Value of thesecapacitances are specified at a given drain-source and gate-source voltage. They areuseful for designing the gate drive circuit of a MOSFET.In addition to the main MOSFET, specifications pertaining to the “body diode” are alsoprovided. Specifications given areReverse break down voltage: This is same as VDSSContinuous ON state current (IS): This is the RMS value of the continuous current thatcan flow through the diode.Pulsed ON state current (ISM): This is the maximum allowable RMS value of the ONstate current through the diode given as a function of the pulse duration.Forward voltage drop (vF): Given as an instantaneous function of the diode forwardcurrent.Reverse recovery time (trr) and Reverse recovery current (Irr): These are specified asfunctions of the diode forward current just before reverse recovery and its decreasingslope (diF/dt). Version 2 EE IIT, Kharagpur 22
  • 175. Exercise 6.4Fill in the blank(s) with the appropriate word(s) i. The maximum voltage a MOSFET can with stand is ________________ of drain current. ii. The FBSOA and RBSOA of a MOSFET are ________________. iii. The gate source threshold voltage of a MOSFET ________________ with junction temperature while the on state resistance ________________ with junction temperature. iv. The gate oxide of a MOSFET can be damaged by ________________ electricity. v. The reverse break down voltage of the body diode of a MOSFET is equal to ________________ while its RMS forward current rating is equal to ________________.Answer: (i) independent; (ii) identical; (iii) decreases, increases; (iv) static; (v) VDSS; IDM.Reference [1] “Evolution of MOS-Bipolar power semiconductor Technology”, B. Jayant Baliga, Proceedings of the IEEE, VOL.76, No-4, April 1988. [2] “Power Electronics ,Converters Application and Design” Third Edition, Mohan, Undeland, Robbins. John Wiley & Sons Publishers 2003. [3] GE – Power MOSFET data sheet. Version 2 EE IIT, Kharagpur 23
  • 176. Lesson Summary • MOSFET is a voltage controlled majority carrier device. • A Power MOSFET has a vertical structure of alternating p and n layers. • The main current carrying terminals of an n channel enhancement mode MOSFET are called the Drain and the Source and are made up of n+ type semiconductor. • The control terminal is called the Gate and is isolated form the bulk semiconductor by a thin layer of SiO2. • p type semiconductor body separates n+ type source and drain regions. • A conducting n type channel is produced in the p type body region when a positive voltage greater than a threshold voltage is applied at the gate. • Current conduction in a MOSFET occurs by flow of electron from the source to the drain through this channel. • When the gate source voltage is below threshold level a MOSFET remains in the “Cut Off” region and does not conduct any current. • With vGS > vGS (th) and vDS < (vGS – vGS (th)) the drain current in a MOSFET is proportional to vDS. This is the “Ohmic region” of the MOSFET output characteristics. • For larger values of vDS the drain current is a function of vGS alone and does not depend on vDs. This is called the “active region” of the MOSFET. • In power electronic applications a MOSFET is operated in the “Cut Off” and Ohmic regions only. • The on state resistance of a MOSFET (VDS (ON)) has a positive temperature coefficient. Therefore, MOSFETs can be easily paralleled. • A MOSFET does not undergo second break down. • The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does not have a second break down limit. • Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not depend on the drain current. • The safe operating area of a MOSFET does not change under Forward and Reverse bias conditions. • The drain – body junction in a MOSFET structure constitute an anti parallel diode connected between the source and the drain. This is called the MOSFET “body – diode.” • The body diode of a MOSFET has the same break down voltage and forward current rating as the main MOSFET. • The switching delays in a MOSFET are due to finite charging and discharging time of the input and output capacitors. • Switching times of a MOSFET can be controlled completely by external gate drive design. Version 2 EE IIT, Kharagpur 24
  • 177. • The input capacitor along with the gate drive resistance determine the current rise and fall time of a MOSFET during switching.• The transfer capacitor (Cgd) determines the drain voltage rise and fall times.• rDS (ON) of a MOSFET determines the conduction loss during ON period.• rDS (ON) reduces with higher vgs. Therefore, to minimize conduction power loss maximum permissible vgs should be used subject to dielectric break down of the gate oxide layer.• The gate oxide layer can be damaged by static charge. Therefore MOSFETs should be handled only after discharging one self through proper grounding.• For similar voltage rating, a MOSFET has a relatively higher conduction loss and lower switching loss compared to a BJT. Therefore, MOSFETs are more popular for high frequency (>50 kHz) low voltage (<100 V) circuits. Version 2 EE IIT, Kharagpur 25
  • 178. Practice Problems and Answers Version 2 EE IIT, Kharagpur 26
  • 179. Practice Problems 1. How do you expect the gate source capacitance of a MOSFET to varry with gate source voltage. Explain your answer. 2. The gate oxide layer of a MOSFET is 1000 Angstrom thick Assuming a break down field strength of 5 × 106 V/cm and a safely factor of 50%, find out the maximum allowable gate source voltage. 3. Explain why in a high voltage MOSFET switching circuit the voltage rise and fall time is always greater than current fall and rise times. 4. A MOSFET has the following parameters VGS(th) = 3V, gfs = 3, CGS = 800 PF, CGD = 250 PF. The MOSFET is used to switch an inductive load of 15 Amps from 150V supply. The switching frequency is 50 kHz. The gate drive circuit has a driving voltage of 15V and output resistance of 50Ω. Find out the switching loss in the MOSFET. Version 2 EE IIT, Kharagpur 27
  • 180. Answer to practice problems 1. When the gate voltage is zero the thickness of the gate-source capacitance is approximately equal to the thickness of the gate oxide layer. As the gate source voltage increases the width of the depletion layer in the p body region also increases. Since the depletion layer is a region of immobile charges it in effect increases the thickness of the gate-source capacitance and hence the value of this capacitances decreases with increasing vGS. However, as vGS is increased further free electrons generated by thermal ionization get attracted towards the gate oxide-semiconductor interface. These free electrons screen the depletion layer partially and the gate-source capacitance starts increasing again. When vGS is above vgs (th) the inversion layer completely screens the depletion layer and the effective thickness of the gate-source capacitance becomes once again equal to the thickness of the oxide layer. There after the value of CGS remains more or less constant. 2. From the given data the break down gate source voltage v GS BD = E BD × t gs where EBD = Break down field strength tgs = thickness of the oxide layer. So v GS BD = 5×106 ×1000×10-8 = 50V Let vgs Max be the maximum allowable gate source voltage assuming 50% factor of safety. ∴ 1.5 vgs Max = vGS BD = 50 V 50 ∴ vgs Max = V ≈ 33 Volts. 1.5 3. We Know that for MOSFET i D = g fs ( VGS - VGS (th) ) ∴ di D d = g fs vGS = g fs ( Vgg - vGS ) dt dt R g CGS During current rise Vgg >> vGS di g fs ∴ D ≈ Vgg dt R g CGS Io ∴ t ri = t fi ≈ R g CGS where Io = load current. g fs Vgg Now From equation (6.4) d Vgg - Vg s , Io Vgg v DS = ≈ dt R g CGD R g CGD Version 2 EE IIT, Kharagpur 28
  • 181. Since Vgg >> Vgs, Io V ∴ t rr = t fv ≈ D R g CGD where VD = Load voltage. Vgg t ri t I CG S ∴ = fi = o t rr t fr VD g fs CG D That is current rise and fall times are much shorter than voltage rise and fall times.4. Referring to Fig 6.9 energy loss during switching occurs during intervals tri , tfv1, tfv2, trv2,trv1,and tfi. For simplicity it will be assumed that tfv2 = trv2 = 0. Also the rise and fall of iD and vDSwill be assumed to be linear.During tri i D = g fs (vgs - vgs (th)) di D d Vgg - v gs ∴ = g fs v gs = g fs dt dt (CGS + CGD )R g di D g fs Vgg ∴ ≈ sinceVgg >> v gs during current rise dt (CGS + CGD )R g Io ∴ t ri = (CGS + CGD )R g g fs VggEnergy loss during tri is 1 V I2 E ON1 = t ri VD Io = D o (CGS + CGD )R g 2 2g fs VggDuring tfv dVDS Vgg - Vgs, Io = dt CGD R g IBut Vgs , Io = o + vgs (th) g fs I Vgg - v gs (th) - o dVDS g fs∴ = dt R g CGD VD∴ t fv = R g CGD Io Vgg - Vgs (th) - g fsEnergy loss during tfv is E ON2 = 1 t fv Io VD 2 VD 2 Io = R g CGD 2 ⎛ Vgg - vgs (th) - o ⎞ I ⎜ g fs ⎟ ⎝ ⎠∴ Energy loss during Turn on is Version 2 EE IIT, Kharagpur 29
  • 182. VD Io R g ⎡ Io ( CGS + CGD ) VD CGD ⎤ E ON = E ON1 + E ON2 = ⎢ + ⎥ 2 ⎢ ⎣ g fs Vgg ( Vgg - Vgs (th) ) ⎥ ⎦From the symmetry of the Turn ON and the Turn OFF operation of MOSFET (i.e. tri = tfi, tfv =trv) E ON = EOFF∴ Total switching energy lass is Esw = EON + EOFF = 2 EON ⎡ ⎤ ⎢ ⎥ I g ⎛ C ⎞ VD Vgg ∴ E sw = VD Io R g CGD ⎢ o fs ⎜1+ GS ⎟ + ⎥ ⎢ Vgg ⎝ CGD ⎠ Vgs (th) Io g fs ⎥ ⎢ - ⎥ ⎣ Vgg Vgg ⎦ ⎡ ⎤ ⎢ ⎥ ⎛ C ⎞I g VD Vgg∴ Psw E sw = VD Io R g CGD f sw ⎢⎜1+ GS ⎟ o fs + ⎥ ⎢⎝ CGD ⎠ Vgg v gs (th) Io g fs ⎥ ⎢ 1- - ⎥ ⎣ Vgg v gg ⎦Substituting the values given Psw = 32 mw, Version 2 EE IIT, Kharagpur 30
  • 183. Module 1Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1
  • 184. Lesson 7Insulated Gate Bipolar Transistor (IGBT) Version 2 EE IIT, Kharagpur 2
  • 185. Constructional features, operating principle and characteristics of Insulated Gate BipolarTransistors (IGBT)Instructional objectsOn completion the student will be able to • Differentiate between the constructional features of an IGBT and a MOSFET. • Draw the operational equivalent circuit of an IGBT and explain its operating principle in terms of the schematic construction and the operational equivalent circuit. • Draw and explain the steady state output and transfer characteristics of an IGBT. • Draw the switching characteristics of an IGBT and identify its differences with that of a MOSFET. • Design a basic gate drive circuit for an IGBT. • Interpret the manufacturer’s date sheet of an IGBT. Version 2 EE IIT, Kharagpur 3
  • 186. 7.1 IntroductionThe introduction of Power MOSFET was originally regarded as a major threat to the powerbipolar transistor. However, initial claims of infinite current gain for the power MOSFETs werediluted by the need to design the gate drive circuit capable of supplying the charging anddischarging current of the device input capacitance. This is especially true in high frequencycircuits where the power MOSFET is particularly valuable due to its inherently high switchingspeed. On the other hand, MOSFETs have a higher on state resistance per unit area andconsequently higher on state loss. This is particularly true for higher voltage devices (greaterthan about 500 volts) which restricted the use of MOSFETs to low voltage high frequencycircuits (eg. SMPS).With the discovery that power MOSFETs were not in a strong position to displace the BJT,many researches began to look at the possibility of combining these technologies to achieve ahybrid device which has a high input impedance and a low on state resistance. The obvious firststep was to drive an output npn BJT with an input MOSFET connected in the Darlingtonconfiguration. However, this approach required the use of a high voltage power MOSFET withconsiderable current carrying capacity (due to low current gain of the output transistor). Also,since no path for negative base current exists for the output transistor, its turn off time also tendsto get somewhat larger. An alternative hybrid approach was investigated at GE Research centerwhere a MOS gate structures was used to trigger the latch up of a four layer thyristor. However,this device was also not a true replacement of a BJT since gate control was lost once the thyristorlatched up.After several such attempts it was concluded that for better results MOSFET and BJTtechnologies are to be integrated at the cell level. This was achieved by the GE ResearchLaboratory by the introduction of the device IGT and by the RCA research laboratory with thedevice COMFET. The IGT device has undergone many improvement cycles to result in themodern Insulated Gate Bipolar Transistor (IGBT). These devices have near ideal characteristicsfor high voltage (> 100V) medium frequency (< 20 kHZ) applications. This device along withthe MOSFET (at low voltage high frequency applications) have the potential to replace the BJTcompletely.7.2 Constructional Features of an IGBTVertical cross section of a n channel IGBT cell is shown in Fig 7.1. Although p channel IGBTsare possible n channel devices are more common and will be the one discussed in this lesson. Version 2 EE IIT, Kharagpur 4
  • 187. Gate Emitter SiO2 SiO2 (Gate oxide) + - (Gate oxide) n n p Body region J3 Drain drift J2 n- region J1 n+ Buffer layer p+ Injecting layer Collector Fig. 7.1: Vertical cross section of an IGBT cell.The major difference with the corresponding MOSFET cell structure lies in the addition of a p+injecting layer. This layer forms a pn junction with the drain layer and injects minority carriersinto it. The n type drain layer itself may have two different doping levels. The lightly doped n-region is called the drain drift region. Doping level and width of this layer sets the forwardblocking voltage (determined by the reverse break down voltage of J2) of the device. However, itdoes not affect the on state voltage drop of the device due to conductivity modulation asdiscussed in connection with the power diode. This construction of the device is called “PunchTrough” (PT) design. The Non-Punch Through (NPT) construction does not have this added n+buffer layer. The PT construction does offer lower on state voltage drop compared to the NPTconstruction particularly for lower voltage rated devices. However, it does so at the cost of lowerreverse break down voltage for the device, since the reverse break down voltage of the junctionJ1 is small. The rest of the construction of the device is very similar to that of a verticalMOSFET (Link to 6.2) including the insulated gate structure and the shorted body (p type) –emitter (n+ type) structure. The doping level and physical geometry of the p type body regionhowever, is considerably different from that of a MOSFET in order to defeat the latch up actionof a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shownin Fig 7.1 are grown on a single silicon wafer and connected in parallel to form a complete IGBTdevice.The IGBT cell has a parasitic p-n-p-n thyristor structure embedded into it as shown in Fig 7.2(a).The constituent p-n-p transistor, n-p-n transistor and the driver MOSFET are shown by dottedlines in this figure. Important resistances in the current flow path are also indicated. Version 2 EE IIT, Kharagpur 5
  • 188. Gate Emitter MOSFET n+ J3 n-p-n p Body spreading resistance Drift J2 resistance p-n-p n- n+ J1 p+ Collector (a) Drift region Collector Drift resistance region Collector resistance Gate Body spreading resistance Emitter Gate (c) Emitter (b) Fig. 7.2: Parasitic thyristor in an IGBT cell. (a) Schematic structure (b) Exact equivalent circuit. (c) Approximate equivalent circuitFig 7.2(b) shows the exact static equivalent circuit of the IGBT cell structure. The top p-n-ptransistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base andthe p type body layer as the collector. The lower n-p-n transistor has the n+ type source, the ptype body and the n type drain as the emitter, base and collector respectively. The base of thelower n-p-n transistor is shorted to the emitter by the emitter metallization. However, due toimperfect shorting, the exact equivalent circuit of the IGBT includes the body spreadingresistance between the base and the emitter of the lower n-p-n transistor. If the output current islarge enough, the voltage drop across this resistance may forward bias the lower n-p-n transistorand initiate the latch up process of the p-n-p-n thyristor structure. Once this structure latches upthe gate control of IGBT is lost and the device is destroyed due to excessive power loss.A major effort in the development of IGBT has been towards prevention of latch up of theparasitic thyristor. This has been achieved by modifying the doping level and physical geometryof the body region. The modern IGBT is latch-up proof for all practical purpose. Fig 7.3(a) and(b) shows the circuit symbol and photograph of an IGBT. Version 2 EE IIT, Kharagpur 6
  • 189. C G E (a) (b) Fig. 7.3: Circuit symbol of an IGBT. (a) Circuit symbol. (b) Photograph.Exercise 7.1Fill in the blank(s) with the appropriate word(s). i. An IGBT is a __________________ device combining the advantages of a __________________ and a __________________. ii. IGBT is suitable for __________________ voltage __________________ frequency applications. iii. In an IGBT cell structure a __________________ type injecting layer is added on top of the drain of an n channel MOSFET. iv. The forward blocking voltage of an IGBT is determined by the __________________ and __________________ of the drain drift layer. v. A “punch through” IGBT has __________________ reverse break down voltage while the “Non punch through” IGBT has __________________ voltage blocking capacity. vi. The IGBT cell has a parasitic __________________ structure embedded into it. vii. The parasitic __________________ structure of an IGBT cell can __________________ at large collector current due to imperfect body emitter shorting. viii. The doping level and physical geometry of the IGBT __________________ region is designed to be considerably different from that of a MOSFET to prevent its __________________.Answers:i) hybrid, MOSFET, BJT ; ii) high, medium ; iii) p+ ; iv) thickness, doping level ; v) low,symmetrical ; vi) thyristor; vii) thryistor, latch up ; viii) body, latch up.7.3 Operating principle of an IGBTOperating principle of an IGBT can be explained in terms of the schematic cell structure andequivalent circuit of Fig 7.2(a) and (c). From the input side the IGBT behaves essentially as a Version 2 EE IIT, Kharagpur 7
  • 190. MOSFET. Therefore, when the gate emitter voltage is less then the threshold voltage noinversion layer is formed in the p type body region and the device is in the off state. The forwardvoltage applied between the collector and the emitter drops almost entirely across the junction J2.Very small leakage current flows through the device under this condition. In terms of theequivalent current of Fig 7.2(c), when the gate emitter voltage is lower than the threshold voltagethe driving MOSFET of the Darlington configuration remains off and hence the output p-n-ptransistor also remains off.When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type bodyregion under the gate. This inversion layer (channel) shorts the emitter and the drain drift layerand an electron current flows from the emitter through this channel to the drain drift region. Thisin turn causes substantial hole injection from the p+ type collector to the drain drift region. Aportion of these holes recombine with the electrons arriving at the drain drift region through thechannel. The rest of the holes cross the drift region to reach the p type body where they arecollected by the source metallization.From the above discussion it is clear that the n type drain drift region acts as the base of theoutput p-n-p transistor. The doping level and the thickness of this layer determines the currentgain “∝” of the p-n-p transistor. This is intentionally kept low so that most of the device currentflows through the MOSFET and not the output p-n-p transistor collector. This helps to reducedthe voltage drop across the “body” spreading resistance shown in Fig 7.2 (b) and eliminate thepossibility of static latch up of the IGBT. The total on state voltage drop across a conducting IGBT has three components. Thevoltage drop across J1 follows the usual exponential law of a pn junction. The next component ofthe voltage drop is due to the drain drift region resistance. This component in an IGBT isconsiderably lower compared to a MOSFET due to strong conductivity modulation by theinjected minority carriers from the collector. This is the main reason for reduced voltage dropacross an IGBT compared to an equivalent MOSFET. The last component of the voltage dropacross an IGBT is due to the channel resistance and its magnitude is equal to that of acomparable MOSFET.7.4 Steady state characteristics of an IGBT The i-v characteristics of an n channel IGBT is shown in Fig 7.4 (a). They appearqualitatively similar to those of a logic level BJT except that the controlling parameter is not abase current but the gate-emitter voltage. Version 2 EE IIT, Kharagpur 8
  • 191. VCC iC Increasing iC Saturation V VCC VgE6 gE RL Active F ic + RL VgE5 C Load line Fault G VcE A Load line E VgE4 VgE - VgE3 B VgE2 gfs VgE1 VRM C Cut off VCC VCES VCE VgE (th) VgE (a) (b) Fig. 7.4: Static characteristics of an IGBT (a) Output characteristics; (b) Transfer characteristics When the gate emitter voltage is below the threshold voltage only a very small leakagecurrent flows though the device while the collector – emitter voltage almost equals the supplyvoltage (point C in Fig 7.4(a)). The device, under this condition is said to be operating in the cutoff region. The maximum forward voltage the device can withstand in this mode (marked VCESin Fig 7.4 (a)) is determined by the avalanche break down voltage of the body – drain p-njunction. Unlike a BJT, however, this break down voltage is independent of the collector currentas shown in Fig 7.4(a). IGBTs of Non-punch through design can block a maximum reversevoltage (VRM) equal to VCES in the cut off mode. However, for Punch Through IGBTs VRM isnegligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer.As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into theactive region of operation. In this mode, the collector current ic is determined by the transfercharacteristics of the device as shown in Fig 7.4(b). This characteristic is qualitatively similar tothat of a power MOSFET and is reasonably linear over most of the collector current range. Theratio of ic to (VgE – vgE(th)) is called the forward transconductance (gfs) of the device and is animportant parameter in the gate drive circuit design. The collector emitter voltage, on the otherhand, is determined by the external load line ABC as shown in Fig 7.4(a).As the gate emitter voltage is increased further ic also increases and for a given load resistance(RL) vCE decreases. At one point vCE becomes less than vgE – vgE(th). Under this condition thedriving MOSFET part of the IGBT (Fig 7.2(c)) enters into the ohmic region and drives theoutput p-n-p transistor to saturation. Under this condition the device is said to be in thesaturation mode. In the saturation mode the voltage drop across the IGBT remains almostconstant reducing only slightly with increasing vgE. In power electronic applications an IGBT is operated either in the cut off or in the saturationregion of the output characteristics. Since vCE decreases with increasing vgE, it is desirable to usethe maximum permissible value of vgE in the ON state of the device. vgE(Max) is limited by themaximum collector current that should be permitted to flow in the IGBT as dictated by the“latch-up” condition discussed earlier. Limiting VgE also helps to limit the fault current through Version 2 EE IIT, Kharagpur 9
  • 192. the device. If a short circuit fault occurs in the load resistance RL (shown in the inset of Fig7.4(a)) the fault load line is given by CF. Limiting vgE to vgE6 restricts the fault currentcorresponding to the operating point F. Most IGBTs are designed to with stand this fault currentfor a few microseconds within which the device must be turned off to prevent destruction of thedevice.It is interesting to note that an IGBT does not exibit a BJT-like second break down failure. Since,in an IGBT most of the collector current flows through the drive MOSFET with positivetemperature coefficient the effective temperature coefficient of vCE in an IGBT is slightlypositive. This helps to prevent second break down failure of the device and also facilitatesparalleling of IGBTs.Exercise 7.2Fill in the blank(s) with the appropriate word(s). i. From the input side the IGBT behaves essentially as a __________________. ii. When the gate emitter voltage is below __________________ no __________________ layer is formed in the p type body region. iii. Electrons arriving through the drive MOSFET causes __________________ injection from the __________________ to the drain drift region. iv. In an IGBT most of the collector current flows through the __________________ and not through the __________________. v. When the gate-emitter voltage of an IGBT is below threshold if operates in the __________________ region. vi. In the active region of operation the collector current of an IGBT is determined by the __________________ characteristics which is reasonably __________________ over most of the collector current range. vii. For the same load resistance as the vgE of an IGBT is increased it enters __________________ region. viii. The forward voltage drop of an IGBT in the saturation region remains approximately __________________. ix. An IGBT has small __________________ temperature coefficient of on state voltage drop. x. An IGBT does not exhibit __________________ failure mode.Answers:i) MOSFET; ii) threshold, inversion; iii) hole, collector; iv) MOSFET, BJT; v) cut-off; vi)transfer, linear; vii)saturation; viii) constant; ix) positive; x) second break down. Version 2 EE IIT, Kharagpur 10
  • 193. 7.5 Switching characteristics of IGBTSwitching characteristics of the IGBT will be analyzed with respect to the clamped inductiveswitching circuit shown in Fig 7.5(a). The equivalent circuit of the IGBT shown in Fig 7.5 (b)will be used to explain the switching waveforms. VCC C iL iD DF D iC + CGD C VCE Rg ig G Q1 G S E CgE E - Vgg (b) (a) Fig. 7.5: Inductive switching circuit using an IGBT (a) Switching circuit; (b) Equivalent circuit of the IGBTThe switching waveforms of an IGBT is, in many respects, similar to that of a Power MOSFET.This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig 7.5(b). Also ina modern IGBT a major portion of the total device current flows through the MOSFET.Therefore, the switching voltage and current waveforms exhibit a strong similarity with those ofa MOSFET. However, the output p-n-p transistor does have a significant effect on the switchingcharacteristics of the device, particularly during turn off. Another important difference is in thegate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emittervoltage of an IGBT is maintained at a negative value when the device is off. Version 2 EE IIT, Kharagpur 11
  • 194. Vgg ∫∫ VgE(th) VgE(th) τ2 = Rg(CGS+CGD2) VgE VgE,IL VgE,IL ∫∫ t τ1 = Rg(CGS+CGD1) VCE VCE(sat) VCC VCC ∫∫ t iC ∫∫ iD IL IL IL IL ∫∫ t tdON tri tfv1 tfv2 trv1 trv2 tfi2 tfi1 Fig. 7.6: Switching waveforms of an IGBT.The switching waveforms of an IGBT is shown in Fig 7.6. Similarity of these waveforms withthose of a MOSFET is obvious. To turn on the IGBT the gate drive voltage changes from –Vgg to+Vgg. The gate emitter voltage vgE follows Vgg with a time constant τ1. Since the drain sourcevoltage of the drive MOSFET is large the gate drain capacitor assumes the lower value CGD1.The collector current ic does not start increasing till vgE reaches the threshold voltage vgE(th).Thereafter, ic increases following the transfer characteristics of the device till vgE reaches a valuevgEIL corresponding to ic = iL. This period is called the current rise time tri. The free wheelingdiode current falls from IL to zero during this period. After ic reaches IL, vgE becomes clamped atvgE IL similar to a MOSFET. vCE also starts falling during this period. First vCE falls rapidly (tfv1)and afterwards the fall of vCE slows down considerably. Two factors contribute to the slowingdown of voltage fall. First the gate-drain capacitance Cgd will increase in the MOSFET portion ofthe IGBT at low drain-source voltages. Second, the pnp transistor portion of the IGBT traversesthe active region to its on state more slowly than the MOSFET portion of the IGBT. Once thepnp transistor is fully on after tfv2, the on state voltage of the device settles down to vCE(sat). Theturn ON process ends here.The turn off process of an IGBT follows the inverse sequence of turn ON with one majordifference. Once vgE goes below vgE(th) the drive MOSFET of the IGBT equivalent circuit turnsoff. During this period (tfi1) the device current falls rapidly. However, when the drive MOSFETturns off, some amount of current continues of flow through the output p-n-p transistor due tostored charge in its base. Since there is no reverse voltage applied to the IGBT terminals thatcould generate a negative drain current, there is no possibility for removing the stored charge bycarrier sweep-out. The only way these excess carriers can be removed is by recombination withinthe IGBT. During this recombination period (tfi2) the remaining current in the IGBT decaysrelatively slowly forming a current fail. A long tfi2 is undesirable, because the power dissipation Version 2 EE IIT, Kharagpur 12
  • 195. in this interval will be large due to full collector-emitter voltage. tfi2 can be reduced bydecreasing the excess carrier life time in the p-n-p transistor base. However, in the process, onstate losses will increase. Therefore, judicious design trade offs are made in a practical IGBT togive minimum total loss.The gate drive circuit of an IGBT should ensure fast and reliable switching of the device. Inparticular, it should. • Apply maximum permissible VgE during ON period. • Apply a negative voltage during off period. • Control dic dt during turn ON and turn off to avoid excessive Electro magnetic interference (EMI). • Control dvce dt during switching to avoid IGBT latch up. • Minimize switching loss. • Provide protection against short circuit fault.Detailed discussion on IGBT gate drive circuit is beyond the scope of this lesson. References [4]& [5] provide good discussion on this subject. Fig 7.7(a) shows a simplified IGBT gate drivecircuit. RC +Vcc +Vgg Ri Q1 - RB R G IGBT Vi + Q2 (Logic level) E Opto isolator Level Totem pole Shifting -Vgg -Vcc gate drive Comparator amplifier (a) RB RB R β1 +1 R β2 +1 G G Vgg To IGBT To IGBT Gate -Vgg Gate E E Turn on equivalent circuit Turn off equivalent circuit (b) Fig. 7.7: IGBT gate drive circuit (a) Gate drive (b) Equivalent circuit of the gate drive during turn on and turn off. Version 2 EE IIT, Kharagpur 13
  • 196. The logic level gate drive signal is first opto-isolated and fed to a level shifting comparator. Thisstage converts the unipolar (usually positive) out put voltage of the opto-isolator to a bipolar(±Vgg) signal compatible to the IGBT gate drive levels. The output of the comparator feeds atotem pole output amplifier stage which drives the IGBT. The equivalent circuit of the gate driveduring turn on and off are shown in Fig 7.7(b). If VCC > Vgg then both Q1 and Q2 will operatein the active region and reasonably constant value of β1 & β2 of these two transistors can be usedfor analysis purpose. These equivalent circuits along with the model of the IGBT input MOSFETcan be used to analyze the switching performance of the device. Conversely, for a desiredswitching performance a suitable gate drive circuit can be designed.7.6 IGBT ratings and safe operating areaMaximum collector-emitter voltage (VCES): This rating should not be exceeded even oninstantaneous basis in order to prevent avalanche break down of the drain-body p-n junction.This is specified at a given negative gate emitter voltage or a specified resistance connectedbetween the gate and the emitter.Maximum continuous collector current (IC): This is the maximum current the IGBT canhandle on a continuous basis during ON condition. It is specified at a given case temperaturewith derating curves provided for other case temperatures.Maximum pulsed collector current (ICM): This is the maximum collector current that can flowfor a specified pulse duration. This current is limited by specifying a maximum gate-emittervoltage.Maximum gate-emitter voltage (VgES): This is the maximum allowable magnitude of the gate-emitter voltage (of both positive and negative polarity) in order to • Prevent break down of the gate oxide insulation. • Restrict collector current to ICM.Collector leakage current (ICES): This is the leakage collector current during off state of thedevice at a given junction temperature. This is usually specified at VgE = 0V and vCE = VCES.Gate-emitter leakage current (IGES): Usually specified at vCE = 0V & vgE = vgES.Collector emitter saturation voltage (VCE(sat)): This is specified at a given junctiontemperature, gate-emitter voltage and collector current. For more detailed data the outputcharacteristics of the device for different vgE and expanded near the saturation zone is alsoprovided.Gate-emitter threshold voltage (vgE(th)): It is specified at a low collector emitter voltage andcollector current.Forward Transconductance (gfs): This is again specified at a low value of vCE. For moredetailed data the transfer characteristics of the device (ic vs vgE) is also provided. Version 2 EE IIT, Kharagpur 14
  • 197. Input, output and transfer capacitances (Cies, Coes & Cres): These are, gate-emitter, collector-emitter and gate-drain capacitances of the device respectively, specified at a given collector-emitter voltage. Variation of these parameters as functions of vCE are also supplied.Switching times (td(ON) tri, tfv, trv, tfi): These times are specified for inductive load switching asfunctions of gate charging resistance and collector current. In addition turn on and turn offenergy losses per switching operation are also specified.Maximum total power dissipation (Ptmax): This is the maximum allowable power lass in thedevice (both switching and conduction) on a continuous basis at a given case temperature.Derating curve at other temperatures are also specified.The IGBT has robust SOA both during turn on and turn off. Fig 7.8 (a) shows the FBSOA. Onthe left side it is restricted by the forward voltage drop characteristics. Up to maximumcontinuous collector current this voltage remains reasonably constant at a low value. However, atICM this voltage starts increasing as the IGBT starts entering active region. On the top theFBSOA is restricted by ICM. iC iC ICM ICM 1000V/μS IC 10-5sec 10-4sec 2000V/μS 10-3sec 10-2sec 3000V/μS DC VCES VCE VCES VCE (a) (b) Fig. 7.8: Safe operating area of an IGBT (a) FBSOA; (b) RBSOA.The other two limits are formed by the maximum power dissipation limit and the maximumforward voltage limit. Like other devices the maximum power dissipation limit increases withreduction in the on pulse width.The RBSOA for low values of dvCE dt is rectangular. However, for increased dvCE dt the upper-righthand corner is progressively cut out. The reason for this restriction on the RBSOA is to avoiddynamic latch up. The device user can easily control dvCE dt by proper choice of Vgg and the gatedrive resistance.Exercise 7.3Fill in the blank(s) with the appropriate word(s). i. In a modern IGBT most of the collector current flows through the _________________ and not the _________________. Version 2 EE IIT, Kharagpur 15
  • 198. ii. To avoid _________________ the gate emitter voltage of an IGBT is maintained at a _________________ value when the device is off. iii. During turn on of an IGBT the rate of fall of voltage slows down towords the end since the output p-n-p transistor traverses its _________________ region more _________________ compared to the drive MOSFET. iv. During turn off of an IGBT a _________________ is formed due to excess stored charge in the _________________ region of the output p-n-p transistor. v. The gate drive circuit of an IGBT should control dic dt to avoid excessive _________________. dvCE vi. dt of an IGBT during turn off should be controlled to prevent _________________ of the device.vii. A specified maximum gate emitter voltage of an IGBT helps to limit the collector current during _________________ fault.viii. Collector emitter saturation voltage of an IGBT _________________ with increasing gate-emitter voltage. ix. The FBSOA of an IGBT is similar to that of a _________________ except that the on state voltage drop is much _________________. x. The upper right hand corner of the IGBT RBSOA is gradually cut out with increasing _________________ to avoid _________________ of the device.Answer: (i) MOSFET, BJT; (ii) latch up, negative; (iii) active, slowly; (iv) current tail, base; (v)EMI; (vi) Latch up; (vii) short circuit; (viii) decreases; (ix) MOSFET, lower; (x) dvCE dt , latch up.Reference [1] B. Jayanta Baliga, “Evolution of MOS Bipolar Power Semiconductor Technology”, Proceedings of the IEEE, vol. 76, No. 4, April 1988, pp 409-418. [2] “Power electronics, Converters, Applications and Design”, Mohan, Undeland, Robbins; John Wiley & Sons, 2003 [3] B. Jayanta Baliga et. al, “The Insulated Gate Transistor: A new Three-Terminal MOS- Controlled Bipolar. Power Device”, IEEE transaction on Electron Devices, vol. ED-31, No. 6 June 1984 pp 421-828. [4] Allen R. Hefner, “An Investigation of the drive circuit requirements for the Power Insulated Gate Bipolar Transistor”, IEEE Transactions on Power Electronics. Vol. 6 No. 2. April 1991. Version 2 EE IIT, Kharagpur 16
  • 199. [5] Carmelo Licitra et. al, “A New Driving circuit for IGBT Devices”, IEEE Transaction on Power Electronics, Vol. 10, No-3 may 1995. [6] “SEMIKRON Power Electronics News 2001”, SEMIKRON International, Germany.Lesson Summary • IGBT is a hybrid device which combines the advantages of MOSFET and BJT. • An IGBT is formed by adding a p+ collector layer on the drain drift layer of a Power MOSFET. • Punch through IGBT has a thin n+ buffer layer between the p+ collector layer and n- drain drift layer. They have significantly lower conduction loss. • The IGBT cell structure embeds a parasitic thyristor in it. Latching up of this thyristor is prevented by special structuring of the body region and increasing the effectiveness of the body shorting. • From the operational point of view an IGBT is a voltage controlled bipolar device. • The operational equivalent circuit of an IGBT has an n channel MOSFET driving a p-n-p BJT. • Like other semiconductor devices on IGBT can also operate in the cut off active and saturation regions. • When the gate-emitter voltage of an IGBT is below threshold it operates in the cut off region. • For a given load resistance the operating point of an IGBT can be moved from cut off to saturation through the active region by increasing the gate-emitter voltage. • In the active region, the collector current of an IGBT is determined by the gate-emitter voltage which can be limited to a given maximum value to limit the fault current through the device in the event of a load short circuit. • The IGBTs have a slightly positive temperature coefficient of the on-state voltage drop which makes paralleling of these devices simpler. • An IGBT does not exhibit second break down phenomena as in the case of a BJT. • The switching characteristics of an IGBT is similar to that of a MOSFET. • To avoid dynamic latch up of the parasitic thryrstor in an IGBT, the gate emitter voltage of the device is maintained at a negative value during it’s off period. • During turn off, the collector current of an IGBT can exhibit “current tailing” due to stored base change in the base region of the output p-n-p transistor. • The forward bias SOA of an IGBT is similar to that of a MOSFET except the on state voltage drop being much lower. • The maximum allowable collector current in an IGBT is restricted by the static latch up consideration. Version 2 EE IIT, Kharagpur 17
  • 200. dv• The RBSOA of an IGBT is rectangular for low values of dt . For higher dvCE dt the upper CE right half corner of the RBSOA is progressively cut-out to prevent “dynamic latch up of the device”.• The IGBT can switch at moderately high frequency (<20 kHZ) and in this range is likely to replace the BJTs in all medium to high power applications. Version 2 EE IIT, Kharagpur 18
  • 201. Practice Problems and Answers Version 2 EE IIT, Kharagpur 19
  • 202. Q1. What effects do the width and doping level of the drain drift region of an IGBT have on its performance.Q2. (a) In an IGBT a major portion of the collector current flow through the driver MOSFET section which has a voltage rating almost same as the device. Then how does the on state voltage drop of an IGBT remain low compared to an equivalent MOSFET? (b) An IGBT is used to switch a resistive load of 5Ω from a DC supply of 350 volts as shown in the inset of Fig 7.4 (a). The ON state gate voltage is vgE = 15v. For the IGBT, vgE (th) = 4 volts and gts = 25. Find out the maximum current flowing through the IGBT in the event of a short circuit fault across the load. Also find out the power dissipation inside the device.Q3. What do you under stand by “dynamic latch up” of an IGBT. How can it be prevented?Q4. What steps are taken in the cell structure design of an IGBT to minimize the “tail current” during turn off operation.Q5. In the basic gate drive circuit of an IGBT shown in Fig 7.7 (a) following data are given Vgg = 15 V, Vcc = 20 V, β1 for Q1 = 50, β2 for Q2 = 50. RB = 2.2 KΩ, R = 30Ω, VgE (th) of IGBT = 4V, gfs = 40 CgE = 4nF, CgD = 500pF,The IGBT is used to switch a clamed inductive load of 50 Amps from a 400 volts supply. dvCEFind out maximum values of dic dt and dt during Turn on and Turn off of the IGBT. Version 2 EE IIT, Kharagpur 20
  • 203. Answers to Practice Problems1. The width and doping level of the drain drift layer of an IGBT affects the performance of the IGBT in several ways. • They determine the forward break down voltage of the IGBT. • Referring to Fig 7.2 (b), the drain drift region constitutes the base of the upper p-n-p transistor. The width and the doping level of this layer determines the current gain “∝” of this transistor. This is intentionally kept low so that most of the device current flows through the MOSFET and not the output p-n-p transistor collector. This helps to reduce the voltage drop across the body spreading resistance between the base and emitter of the lower p-n-p transistor. Thus the possibility of turning on this transistor and consequent latch up of the device is minimized. • Since the major part of the device current flows through the MOSFET which has a positive temperature coefficient of drain source voltage drop, the collector-emitter voltage drop across the device exhibits a slightly positive temperature coefficient. This eliminates the possibility of second break down failure in IGBTs and simplifies paralleling of these devices. 2. (a) The total voltage drop across a conducting IGBT has three components. The voltage drop across the emitter-base junction of the output p-n-p transistor follows the usual exponential low of a p-n junction. The next component of the voltage drop is due to the drain drift region resistance. In a normal high voltage MOSFET this component of the voltage drop is large due to lower doping level (necessary for blocking high voltage) of this region. However, in a conducting IGBT electrons arriving at the drain drift region through the MOSFET channel causes large minority carrier injection from the p+ collector. The consequent conductivity modulation reduces the resistance (and hence the voltage drop) in this region. The third component of the IGBT voltage drop occurs across the channel of the driving MOSFET and is same as that of an equivalent high voltage MOSFET. Therefore, the reduced voltage drop across a conducting IGBT is due to reduction of the drain drift region resistance by “conductivity modulation”. (b) In the event of a short circuit across the load the voltage across the device will be 350 volts and the IGBT will operate in the active region. In this region iC = gfs ( vgE - vgE (th) ) Substituting the given values iC Max = 25 (15 - 4 ) = 275 Amps Power dissipation inside the device will be PD = vCE iC Max = 350 × 275 = 96.25 kW Version 2 EE IIT, Kharagpur 21
  • 204. 3. Static latch up in an IGBT occurs when the continuous ON state current exceeds a critical value. However, under dynamic conditions, when the IGBT is switching from on to off state if may latch up at drain current less than this value. During turn off, the voltage across the driver MOSFET increases rapidly. This voltage is blocked by the drain-body p-n junction. To block the rapid build up of the voltage the width of the depletion region in the drain drift layer also increases rapidly. This rapid increase in the depletion layer width temporally increases the current gain “∝” of the output p-n-p transistor and causes latch up of the device at a lower collector current than would have been necessary for static latch up.4. Punch Through and Non-punch through IGBTs solve the problem of tail current by two different approaches. Punch through IGBT s attempt to minimize the current tailing problem by shortening the duration of the tailing time. This is done by reducing the excess carrier life time in the n+ buffer layer compared to the n- drain drift layer. This n+ buffer layer acts as a sink for excess holes and greatly enhances the removal rate of holes from the drain drift layer. Thus the tail time is reduced. Non punch through IGBTs attack the current tailing problem by minimizing the magnitude of the current during the failing interval. This is done by designing the IGBT so that the MOSFET section carries as much of the total current as possible. Newer NPT IGBT designs have more than 90% of the total current carried by the MOSFET section of the device.5. During turn on and turn off the IGBT passes through the active region. When vgE is greater than vgE(th) the collector current is given by iC = gfs ( vgE - vgE (th) ) dic d ∴ = gfs vgE dt dt But from the equivalent circuit of the IGBT gate drive circuit during turn on d Vgg - vgE vgE = dt ( ( CgE + CgD ) R + βR+1 1 B ) dic d gfs ( Vgg - vgE ) ∴ = gfs vgE = dt dt ( CgE + CgD ) R + βR+1 ( 1 B ) In the active region Vgg >> vgE Also since Vcc > Vgg, Q1 & Q2 operates in the active region. Substituting the given values Version 2 EE IIT, Kharagpur 22